resource_tracker.c 68 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies.
  4. * All rights reserved.
  5. * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
  6. *
  7. * This software is available to you under a choice of one of two
  8. * licenses. You may choose to be licensed under the terms of the GNU
  9. * General Public License (GPL) Version 2, available from the file
  10. * COPYING in the main directory of this source tree, or the
  11. * OpenIB.org BSD license below:
  12. *
  13. * Redistribution and use in source and binary forms, with or
  14. * without modification, are permitted provided that the following
  15. * conditions are met:
  16. *
  17. * - Redistributions of source code must retain the above
  18. * copyright notice, this list of conditions and the following
  19. * disclaimer.
  20. *
  21. * - Redistributions in binary form must reproduce the above
  22. * copyright notice, this list of conditions and the following
  23. * disclaimer in the documentation and/or other materials
  24. * provided with the distribution.
  25. *
  26. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33. * SOFTWARE.
  34. */
  35. #include <linux/sched.h>
  36. #include <linux/pci.h>
  37. #include <linux/errno.h>
  38. #include <linux/kernel.h>
  39. #include <linux/io.h>
  40. #include <linux/slab.h>
  41. #include <linux/mlx4/cmd.h>
  42. #include <linux/mlx4/qp.h>
  43. #include "mlx4.h"
  44. #include "fw.h"
  45. #define MLX4_MAC_VALID (1ull << 63)
  46. #define MLX4_MAC_MASK 0x7fffffffffffffffULL
  47. #define ETH_ALEN 6
  48. struct mac_res {
  49. struct list_head list;
  50. u64 mac;
  51. u8 port;
  52. };
  53. struct res_common {
  54. struct list_head list;
  55. u32 res_id;
  56. int owner;
  57. int state;
  58. int from_state;
  59. int to_state;
  60. int removing;
  61. };
  62. enum {
  63. RES_ANY_BUSY = 1
  64. };
  65. struct res_gid {
  66. struct list_head list;
  67. u8 gid[16];
  68. enum mlx4_protocol prot;
  69. };
  70. enum res_qp_states {
  71. RES_QP_BUSY = RES_ANY_BUSY,
  72. /* QP number was allocated */
  73. RES_QP_RESERVED,
  74. /* ICM memory for QP context was mapped */
  75. RES_QP_MAPPED,
  76. /* QP is in hw ownership */
  77. RES_QP_HW
  78. };
  79. static inline const char *qp_states_str(enum res_qp_states state)
  80. {
  81. switch (state) {
  82. case RES_QP_BUSY: return "RES_QP_BUSY";
  83. case RES_QP_RESERVED: return "RES_QP_RESERVED";
  84. case RES_QP_MAPPED: return "RES_QP_MAPPED";
  85. case RES_QP_HW: return "RES_QP_HW";
  86. default: return "Unknown";
  87. }
  88. }
  89. struct res_qp {
  90. struct res_common com;
  91. struct res_mtt *mtt;
  92. struct res_cq *rcq;
  93. struct res_cq *scq;
  94. struct res_srq *srq;
  95. struct list_head mcg_list;
  96. spinlock_t mcg_spl;
  97. int local_qpn;
  98. };
  99. enum res_mtt_states {
  100. RES_MTT_BUSY = RES_ANY_BUSY,
  101. RES_MTT_ALLOCATED,
  102. };
  103. static inline const char *mtt_states_str(enum res_mtt_states state)
  104. {
  105. switch (state) {
  106. case RES_MTT_BUSY: return "RES_MTT_BUSY";
  107. case RES_MTT_ALLOCATED: return "RES_MTT_ALLOCATED";
  108. default: return "Unknown";
  109. }
  110. }
  111. struct res_mtt {
  112. struct res_common com;
  113. int order;
  114. atomic_t ref_count;
  115. };
  116. enum res_mpt_states {
  117. RES_MPT_BUSY = RES_ANY_BUSY,
  118. RES_MPT_RESERVED,
  119. RES_MPT_MAPPED,
  120. RES_MPT_HW,
  121. };
  122. struct res_mpt {
  123. struct res_common com;
  124. struct res_mtt *mtt;
  125. int key;
  126. };
  127. enum res_eq_states {
  128. RES_EQ_BUSY = RES_ANY_BUSY,
  129. RES_EQ_RESERVED,
  130. RES_EQ_HW,
  131. };
  132. struct res_eq {
  133. struct res_common com;
  134. struct res_mtt *mtt;
  135. };
  136. enum res_cq_states {
  137. RES_CQ_BUSY = RES_ANY_BUSY,
  138. RES_CQ_ALLOCATED,
  139. RES_CQ_HW,
  140. };
  141. struct res_cq {
  142. struct res_common com;
  143. struct res_mtt *mtt;
  144. atomic_t ref_count;
  145. };
  146. enum res_srq_states {
  147. RES_SRQ_BUSY = RES_ANY_BUSY,
  148. RES_SRQ_ALLOCATED,
  149. RES_SRQ_HW,
  150. };
  151. static inline const char *srq_states_str(enum res_srq_states state)
  152. {
  153. switch (state) {
  154. case RES_SRQ_BUSY: return "RES_SRQ_BUSY";
  155. case RES_SRQ_ALLOCATED: return "RES_SRQ_ALLOCATED";
  156. case RES_SRQ_HW: return "RES_SRQ_HW";
  157. default: return "Unknown";
  158. }
  159. }
  160. struct res_srq {
  161. struct res_common com;
  162. struct res_mtt *mtt;
  163. struct res_cq *cq;
  164. atomic_t ref_count;
  165. };
  166. enum res_counter_states {
  167. RES_COUNTER_BUSY = RES_ANY_BUSY,
  168. RES_COUNTER_ALLOCATED,
  169. };
  170. static inline const char *counter_states_str(enum res_counter_states state)
  171. {
  172. switch (state) {
  173. case RES_COUNTER_BUSY: return "RES_COUNTER_BUSY";
  174. case RES_COUNTER_ALLOCATED: return "RES_COUNTER_ALLOCATED";
  175. default: return "Unknown";
  176. }
  177. }
  178. struct res_counter {
  179. struct res_common com;
  180. int port;
  181. };
  182. /* For Debug uses */
  183. static const char *ResourceType(enum mlx4_resource rt)
  184. {
  185. switch (rt) {
  186. case RES_QP: return "RES_QP";
  187. case RES_CQ: return "RES_CQ";
  188. case RES_SRQ: return "RES_SRQ";
  189. case RES_MPT: return "RES_MPT";
  190. case RES_MTT: return "RES_MTT";
  191. case RES_MAC: return "RES_MAC";
  192. case RES_EQ: return "RES_EQ";
  193. case RES_COUNTER: return "RES_COUNTER";
  194. default: return "Unknown resource type !!!";
  195. };
  196. }
  197. int mlx4_init_resource_tracker(struct mlx4_dev *dev)
  198. {
  199. struct mlx4_priv *priv = mlx4_priv(dev);
  200. int i;
  201. int t;
  202. priv->mfunc.master.res_tracker.slave_list =
  203. kzalloc(dev->num_slaves * sizeof(struct slave_list),
  204. GFP_KERNEL);
  205. if (!priv->mfunc.master.res_tracker.slave_list)
  206. return -ENOMEM;
  207. for (i = 0 ; i < dev->num_slaves; i++) {
  208. for (t = 0; t < MLX4_NUM_OF_RESOURCE_TYPE; ++t)
  209. INIT_LIST_HEAD(&priv->mfunc.master.res_tracker.
  210. slave_list[i].res_list[t]);
  211. mutex_init(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
  212. }
  213. mlx4_dbg(dev, "Started init_resource_tracker: %ld slaves\n",
  214. dev->num_slaves);
  215. for (i = 0 ; i < MLX4_NUM_OF_RESOURCE_TYPE; i++)
  216. INIT_RADIX_TREE(&priv->mfunc.master.res_tracker.res_tree[i],
  217. GFP_ATOMIC|__GFP_NOWARN);
  218. spin_lock_init(&priv->mfunc.master.res_tracker.lock);
  219. return 0 ;
  220. }
  221. void mlx4_free_resource_tracker(struct mlx4_dev *dev)
  222. {
  223. struct mlx4_priv *priv = mlx4_priv(dev);
  224. int i;
  225. if (priv->mfunc.master.res_tracker.slave_list) {
  226. for (i = 0 ; i < dev->num_slaves; i++)
  227. mlx4_delete_all_resources_for_slave(dev, i);
  228. kfree(priv->mfunc.master.res_tracker.slave_list);
  229. }
  230. }
  231. static void update_ud_gid(struct mlx4_dev *dev,
  232. struct mlx4_qp_context *qp_ctx, u8 slave)
  233. {
  234. u32 ts = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
  235. if (MLX4_QP_ST_UD == ts)
  236. qp_ctx->pri_path.mgid_index = 0x80 | slave;
  237. mlx4_dbg(dev, "slave %d, new gid index: 0x%x ",
  238. slave, qp_ctx->pri_path.mgid_index);
  239. }
  240. static int mpt_mask(struct mlx4_dev *dev)
  241. {
  242. return dev->caps.num_mpts - 1;
  243. }
  244. static void *find_res(struct mlx4_dev *dev, int res_id,
  245. enum mlx4_resource type)
  246. {
  247. struct mlx4_priv *priv = mlx4_priv(dev);
  248. return radix_tree_lookup(&priv->mfunc.master.res_tracker.res_tree[type],
  249. res_id);
  250. }
  251. static int get_res(struct mlx4_dev *dev, int slave, int res_id,
  252. enum mlx4_resource type,
  253. void *res)
  254. {
  255. struct res_common *r;
  256. int err = 0;
  257. spin_lock_irq(mlx4_tlock(dev));
  258. r = find_res(dev, res_id, type);
  259. if (!r) {
  260. err = -ENONET;
  261. goto exit;
  262. }
  263. if (r->state == RES_ANY_BUSY) {
  264. err = -EBUSY;
  265. goto exit;
  266. }
  267. if (r->owner != slave) {
  268. err = -EPERM;
  269. goto exit;
  270. }
  271. r->from_state = r->state;
  272. r->state = RES_ANY_BUSY;
  273. mlx4_dbg(dev, "res %s id 0x%x to busy\n",
  274. ResourceType(type), r->res_id);
  275. if (res)
  276. *((struct res_common **)res) = r;
  277. exit:
  278. spin_unlock_irq(mlx4_tlock(dev));
  279. return err;
  280. }
  281. int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
  282. enum mlx4_resource type,
  283. int res_id, int *slave)
  284. {
  285. struct res_common *r;
  286. int err = -ENOENT;
  287. int id = res_id;
  288. if (type == RES_QP)
  289. id &= 0x7fffff;
  290. spin_lock(mlx4_tlock(dev));
  291. r = find_res(dev, id, type);
  292. if (r) {
  293. *slave = r->owner;
  294. err = 0;
  295. }
  296. spin_unlock(mlx4_tlock(dev));
  297. return err;
  298. }
  299. static void put_res(struct mlx4_dev *dev, int slave, int res_id,
  300. enum mlx4_resource type)
  301. {
  302. struct res_common *r;
  303. spin_lock_irq(mlx4_tlock(dev));
  304. r = find_res(dev, res_id, type);
  305. if (r)
  306. r->state = r->from_state;
  307. spin_unlock_irq(mlx4_tlock(dev));
  308. }
  309. static struct res_common *alloc_qp_tr(int id)
  310. {
  311. struct res_qp *ret;
  312. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  313. if (!ret)
  314. return NULL;
  315. ret->com.res_id = id;
  316. ret->com.state = RES_QP_RESERVED;
  317. INIT_LIST_HEAD(&ret->mcg_list);
  318. spin_lock_init(&ret->mcg_spl);
  319. return &ret->com;
  320. }
  321. static struct res_common *alloc_mtt_tr(int id, int order)
  322. {
  323. struct res_mtt *ret;
  324. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  325. if (!ret)
  326. return NULL;
  327. ret->com.res_id = id;
  328. ret->order = order;
  329. ret->com.state = RES_MTT_ALLOCATED;
  330. atomic_set(&ret->ref_count, 0);
  331. return &ret->com;
  332. }
  333. static struct res_common *alloc_mpt_tr(int id, int key)
  334. {
  335. struct res_mpt *ret;
  336. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  337. if (!ret)
  338. return NULL;
  339. ret->com.res_id = id;
  340. ret->com.state = RES_MPT_RESERVED;
  341. ret->key = key;
  342. return &ret->com;
  343. }
  344. static struct res_common *alloc_eq_tr(int id)
  345. {
  346. struct res_eq *ret;
  347. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  348. if (!ret)
  349. return NULL;
  350. ret->com.res_id = id;
  351. ret->com.state = RES_EQ_RESERVED;
  352. return &ret->com;
  353. }
  354. static struct res_common *alloc_cq_tr(int id)
  355. {
  356. struct res_cq *ret;
  357. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  358. if (!ret)
  359. return NULL;
  360. ret->com.res_id = id;
  361. ret->com.state = RES_CQ_ALLOCATED;
  362. atomic_set(&ret->ref_count, 0);
  363. return &ret->com;
  364. }
  365. static struct res_common *alloc_srq_tr(int id)
  366. {
  367. struct res_srq *ret;
  368. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  369. if (!ret)
  370. return NULL;
  371. ret->com.res_id = id;
  372. ret->com.state = RES_SRQ_ALLOCATED;
  373. atomic_set(&ret->ref_count, 0);
  374. return &ret->com;
  375. }
  376. static struct res_common *alloc_counter_tr(int id)
  377. {
  378. struct res_counter *ret;
  379. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  380. if (!ret)
  381. return NULL;
  382. ret->com.res_id = id;
  383. ret->com.state = RES_COUNTER_ALLOCATED;
  384. return &ret->com;
  385. }
  386. static struct res_common *alloc_tr(int id, enum mlx4_resource type, int slave,
  387. int extra)
  388. {
  389. struct res_common *ret;
  390. switch (type) {
  391. case RES_QP:
  392. ret = alloc_qp_tr(id);
  393. break;
  394. case RES_MPT:
  395. ret = alloc_mpt_tr(id, extra);
  396. break;
  397. case RES_MTT:
  398. ret = alloc_mtt_tr(id, extra);
  399. break;
  400. case RES_EQ:
  401. ret = alloc_eq_tr(id);
  402. break;
  403. case RES_CQ:
  404. ret = alloc_cq_tr(id);
  405. break;
  406. case RES_SRQ:
  407. ret = alloc_srq_tr(id);
  408. break;
  409. case RES_MAC:
  410. printk(KERN_ERR "implementation missing\n");
  411. return NULL;
  412. case RES_COUNTER:
  413. ret = alloc_counter_tr(id);
  414. break;
  415. default:
  416. return NULL;
  417. }
  418. if (ret)
  419. ret->owner = slave;
  420. return ret;
  421. }
  422. static int add_res_range(struct mlx4_dev *dev, int slave, int base, int count,
  423. enum mlx4_resource type, int extra)
  424. {
  425. int i;
  426. int err;
  427. struct mlx4_priv *priv = mlx4_priv(dev);
  428. struct res_common **res_arr;
  429. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  430. struct radix_tree_root *root = &tracker->res_tree[type];
  431. res_arr = kzalloc(count * sizeof *res_arr, GFP_KERNEL);
  432. if (!res_arr)
  433. return -ENOMEM;
  434. for (i = 0; i < count; ++i) {
  435. res_arr[i] = alloc_tr(base + i, type, slave, extra);
  436. if (!res_arr[i]) {
  437. for (--i; i >= 0; --i)
  438. kfree(res_arr[i]);
  439. kfree(res_arr);
  440. return -ENOMEM;
  441. }
  442. }
  443. spin_lock_irq(mlx4_tlock(dev));
  444. for (i = 0; i < count; ++i) {
  445. if (find_res(dev, base + i, type)) {
  446. err = -EEXIST;
  447. goto undo;
  448. }
  449. err = radix_tree_insert(root, base + i, res_arr[i]);
  450. if (err)
  451. goto undo;
  452. list_add_tail(&res_arr[i]->list,
  453. &tracker->slave_list[slave].res_list[type]);
  454. }
  455. spin_unlock_irq(mlx4_tlock(dev));
  456. kfree(res_arr);
  457. return 0;
  458. undo:
  459. for (--i; i >= base; --i)
  460. radix_tree_delete(&tracker->res_tree[type], i);
  461. spin_unlock_irq(mlx4_tlock(dev));
  462. for (i = 0; i < count; ++i)
  463. kfree(res_arr[i]);
  464. kfree(res_arr);
  465. return err;
  466. }
  467. static int remove_qp_ok(struct res_qp *res)
  468. {
  469. if (res->com.state == RES_QP_BUSY)
  470. return -EBUSY;
  471. else if (res->com.state != RES_QP_RESERVED)
  472. return -EPERM;
  473. return 0;
  474. }
  475. static int remove_mtt_ok(struct res_mtt *res, int order)
  476. {
  477. if (res->com.state == RES_MTT_BUSY ||
  478. atomic_read(&res->ref_count)) {
  479. printk(KERN_DEBUG "%s-%d: state %s, ref_count %d\n",
  480. __func__, __LINE__,
  481. mtt_states_str(res->com.state),
  482. atomic_read(&res->ref_count));
  483. return -EBUSY;
  484. } else if (res->com.state != RES_MTT_ALLOCATED)
  485. return -EPERM;
  486. else if (res->order != order)
  487. return -EINVAL;
  488. return 0;
  489. }
  490. static int remove_mpt_ok(struct res_mpt *res)
  491. {
  492. if (res->com.state == RES_MPT_BUSY)
  493. return -EBUSY;
  494. else if (res->com.state != RES_MPT_RESERVED)
  495. return -EPERM;
  496. return 0;
  497. }
  498. static int remove_eq_ok(struct res_eq *res)
  499. {
  500. if (res->com.state == RES_MPT_BUSY)
  501. return -EBUSY;
  502. else if (res->com.state != RES_MPT_RESERVED)
  503. return -EPERM;
  504. return 0;
  505. }
  506. static int remove_counter_ok(struct res_counter *res)
  507. {
  508. if (res->com.state == RES_COUNTER_BUSY)
  509. return -EBUSY;
  510. else if (res->com.state != RES_COUNTER_ALLOCATED)
  511. return -EPERM;
  512. return 0;
  513. }
  514. static int remove_cq_ok(struct res_cq *res)
  515. {
  516. if (res->com.state == RES_CQ_BUSY)
  517. return -EBUSY;
  518. else if (res->com.state != RES_CQ_ALLOCATED)
  519. return -EPERM;
  520. return 0;
  521. }
  522. static int remove_srq_ok(struct res_srq *res)
  523. {
  524. if (res->com.state == RES_SRQ_BUSY)
  525. return -EBUSY;
  526. else if (res->com.state != RES_SRQ_ALLOCATED)
  527. return -EPERM;
  528. return 0;
  529. }
  530. static int remove_ok(struct res_common *res, enum mlx4_resource type, int extra)
  531. {
  532. switch (type) {
  533. case RES_QP:
  534. return remove_qp_ok((struct res_qp *)res);
  535. case RES_CQ:
  536. return remove_cq_ok((struct res_cq *)res);
  537. case RES_SRQ:
  538. return remove_srq_ok((struct res_srq *)res);
  539. case RES_MPT:
  540. return remove_mpt_ok((struct res_mpt *)res);
  541. case RES_MTT:
  542. return remove_mtt_ok((struct res_mtt *)res, extra);
  543. case RES_MAC:
  544. return -ENOSYS;
  545. case RES_EQ:
  546. return remove_eq_ok((struct res_eq *)res);
  547. case RES_COUNTER:
  548. return remove_counter_ok((struct res_counter *)res);
  549. default:
  550. return -EINVAL;
  551. }
  552. }
  553. static int rem_res_range(struct mlx4_dev *dev, int slave, int base, int count,
  554. enum mlx4_resource type, int extra)
  555. {
  556. int i;
  557. int err;
  558. struct mlx4_priv *priv = mlx4_priv(dev);
  559. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  560. struct res_common *r;
  561. spin_lock_irq(mlx4_tlock(dev));
  562. for (i = base; i < base + count; ++i) {
  563. r = radix_tree_lookup(&tracker->res_tree[type], i);
  564. if (!r) {
  565. err = -ENOENT;
  566. goto out;
  567. }
  568. if (r->owner != slave) {
  569. err = -EPERM;
  570. goto out;
  571. }
  572. err = remove_ok(r, type, extra);
  573. if (err)
  574. goto out;
  575. }
  576. for (i = base; i < base + count; ++i) {
  577. r = radix_tree_lookup(&tracker->res_tree[type], i);
  578. radix_tree_delete(&tracker->res_tree[type], i);
  579. list_del(&r->list);
  580. kfree(r);
  581. }
  582. err = 0;
  583. out:
  584. spin_unlock_irq(mlx4_tlock(dev));
  585. return err;
  586. }
  587. static int qp_res_start_move_to(struct mlx4_dev *dev, int slave, int qpn,
  588. enum res_qp_states state, struct res_qp **qp,
  589. int alloc)
  590. {
  591. struct mlx4_priv *priv = mlx4_priv(dev);
  592. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  593. struct res_qp *r;
  594. int err = 0;
  595. spin_lock_irq(mlx4_tlock(dev));
  596. r = radix_tree_lookup(&tracker->res_tree[RES_QP], qpn);
  597. if (!r)
  598. err = -ENOENT;
  599. else if (r->com.owner != slave)
  600. err = -EPERM;
  601. else {
  602. switch (state) {
  603. case RES_QP_BUSY:
  604. mlx4_dbg(dev, "%s: failed RES_QP, 0x%x\n",
  605. __func__, r->com.res_id);
  606. err = -EBUSY;
  607. break;
  608. case RES_QP_RESERVED:
  609. if (r->com.state == RES_QP_MAPPED && !alloc)
  610. break;
  611. mlx4_dbg(dev, "failed RES_QP, 0x%x\n", r->com.res_id);
  612. err = -EINVAL;
  613. break;
  614. case RES_QP_MAPPED:
  615. if ((r->com.state == RES_QP_RESERVED && alloc) ||
  616. r->com.state == RES_QP_HW)
  617. break;
  618. else {
  619. mlx4_dbg(dev, "failed RES_QP, 0x%x\n",
  620. r->com.res_id);
  621. err = -EINVAL;
  622. }
  623. break;
  624. case RES_QP_HW:
  625. if (r->com.state != RES_QP_MAPPED)
  626. err = -EINVAL;
  627. break;
  628. default:
  629. err = -EINVAL;
  630. }
  631. if (!err) {
  632. r->com.from_state = r->com.state;
  633. r->com.to_state = state;
  634. r->com.state = RES_QP_BUSY;
  635. if (qp)
  636. *qp = (struct res_qp *)r;
  637. }
  638. }
  639. spin_unlock_irq(mlx4_tlock(dev));
  640. return err;
  641. }
  642. static int mr_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  643. enum res_mpt_states state, struct res_mpt **mpt)
  644. {
  645. struct mlx4_priv *priv = mlx4_priv(dev);
  646. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  647. struct res_mpt *r;
  648. int err = 0;
  649. spin_lock_irq(mlx4_tlock(dev));
  650. r = radix_tree_lookup(&tracker->res_tree[RES_MPT], index);
  651. if (!r)
  652. err = -ENOENT;
  653. else if (r->com.owner != slave)
  654. err = -EPERM;
  655. else {
  656. switch (state) {
  657. case RES_MPT_BUSY:
  658. err = -EINVAL;
  659. break;
  660. case RES_MPT_RESERVED:
  661. if (r->com.state != RES_MPT_MAPPED)
  662. err = -EINVAL;
  663. break;
  664. case RES_MPT_MAPPED:
  665. if (r->com.state != RES_MPT_RESERVED &&
  666. r->com.state != RES_MPT_HW)
  667. err = -EINVAL;
  668. break;
  669. case RES_MPT_HW:
  670. if (r->com.state != RES_MPT_MAPPED)
  671. err = -EINVAL;
  672. break;
  673. default:
  674. err = -EINVAL;
  675. }
  676. if (!err) {
  677. r->com.from_state = r->com.state;
  678. r->com.to_state = state;
  679. r->com.state = RES_MPT_BUSY;
  680. if (mpt)
  681. *mpt = (struct res_mpt *)r;
  682. }
  683. }
  684. spin_unlock_irq(mlx4_tlock(dev));
  685. return err;
  686. }
  687. static int eq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  688. enum res_eq_states state, struct res_eq **eq)
  689. {
  690. struct mlx4_priv *priv = mlx4_priv(dev);
  691. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  692. struct res_eq *r;
  693. int err = 0;
  694. spin_lock_irq(mlx4_tlock(dev));
  695. r = radix_tree_lookup(&tracker->res_tree[RES_EQ], index);
  696. if (!r)
  697. err = -ENOENT;
  698. else if (r->com.owner != slave)
  699. err = -EPERM;
  700. else {
  701. switch (state) {
  702. case RES_EQ_BUSY:
  703. err = -EINVAL;
  704. break;
  705. case RES_EQ_RESERVED:
  706. if (r->com.state != RES_EQ_HW)
  707. err = -EINVAL;
  708. break;
  709. case RES_EQ_HW:
  710. if (r->com.state != RES_EQ_RESERVED)
  711. err = -EINVAL;
  712. break;
  713. default:
  714. err = -EINVAL;
  715. }
  716. if (!err) {
  717. r->com.from_state = r->com.state;
  718. r->com.to_state = state;
  719. r->com.state = RES_EQ_BUSY;
  720. if (eq)
  721. *eq = r;
  722. }
  723. }
  724. spin_unlock_irq(mlx4_tlock(dev));
  725. return err;
  726. }
  727. static int cq_res_start_move_to(struct mlx4_dev *dev, int slave, int cqn,
  728. enum res_cq_states state, struct res_cq **cq)
  729. {
  730. struct mlx4_priv *priv = mlx4_priv(dev);
  731. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  732. struct res_cq *r;
  733. int err;
  734. spin_lock_irq(mlx4_tlock(dev));
  735. r = radix_tree_lookup(&tracker->res_tree[RES_CQ], cqn);
  736. if (!r)
  737. err = -ENOENT;
  738. else if (r->com.owner != slave)
  739. err = -EPERM;
  740. else {
  741. switch (state) {
  742. case RES_CQ_BUSY:
  743. err = -EBUSY;
  744. break;
  745. case RES_CQ_ALLOCATED:
  746. if (r->com.state != RES_CQ_HW)
  747. err = -EINVAL;
  748. else if (atomic_read(&r->ref_count))
  749. err = -EBUSY;
  750. else
  751. err = 0;
  752. break;
  753. case RES_CQ_HW:
  754. if (r->com.state != RES_CQ_ALLOCATED)
  755. err = -EINVAL;
  756. else
  757. err = 0;
  758. break;
  759. default:
  760. err = -EINVAL;
  761. }
  762. if (!err) {
  763. r->com.from_state = r->com.state;
  764. r->com.to_state = state;
  765. r->com.state = RES_CQ_BUSY;
  766. if (cq)
  767. *cq = r;
  768. }
  769. }
  770. spin_unlock_irq(mlx4_tlock(dev));
  771. return err;
  772. }
  773. static int srq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  774. enum res_cq_states state, struct res_srq **srq)
  775. {
  776. struct mlx4_priv *priv = mlx4_priv(dev);
  777. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  778. struct res_srq *r;
  779. int err = 0;
  780. spin_lock_irq(mlx4_tlock(dev));
  781. r = radix_tree_lookup(&tracker->res_tree[RES_SRQ], index);
  782. if (!r)
  783. err = -ENOENT;
  784. else if (r->com.owner != slave)
  785. err = -EPERM;
  786. else {
  787. switch (state) {
  788. case RES_SRQ_BUSY:
  789. err = -EINVAL;
  790. break;
  791. case RES_SRQ_ALLOCATED:
  792. if (r->com.state != RES_SRQ_HW)
  793. err = -EINVAL;
  794. else if (atomic_read(&r->ref_count))
  795. err = -EBUSY;
  796. break;
  797. case RES_SRQ_HW:
  798. if (r->com.state != RES_SRQ_ALLOCATED)
  799. err = -EINVAL;
  800. break;
  801. default:
  802. err = -EINVAL;
  803. }
  804. if (!err) {
  805. r->com.from_state = r->com.state;
  806. r->com.to_state = state;
  807. r->com.state = RES_SRQ_BUSY;
  808. if (srq)
  809. *srq = r;
  810. }
  811. }
  812. spin_unlock_irq(mlx4_tlock(dev));
  813. return err;
  814. }
  815. static void res_abort_move(struct mlx4_dev *dev, int slave,
  816. enum mlx4_resource type, int id)
  817. {
  818. struct mlx4_priv *priv = mlx4_priv(dev);
  819. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  820. struct res_common *r;
  821. spin_lock_irq(mlx4_tlock(dev));
  822. r = radix_tree_lookup(&tracker->res_tree[type], id);
  823. if (r && (r->owner == slave))
  824. r->state = r->from_state;
  825. spin_unlock_irq(mlx4_tlock(dev));
  826. }
  827. static void res_end_move(struct mlx4_dev *dev, int slave,
  828. enum mlx4_resource type, int id)
  829. {
  830. struct mlx4_priv *priv = mlx4_priv(dev);
  831. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  832. struct res_common *r;
  833. spin_lock_irq(mlx4_tlock(dev));
  834. r = radix_tree_lookup(&tracker->res_tree[type], id);
  835. if (r && (r->owner == slave))
  836. r->state = r->to_state;
  837. spin_unlock_irq(mlx4_tlock(dev));
  838. }
  839. static int valid_reserved(struct mlx4_dev *dev, int slave, int qpn)
  840. {
  841. return mlx4_is_qp_reserved(dev, qpn);
  842. }
  843. static int qp_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  844. u64 in_param, u64 *out_param)
  845. {
  846. int err;
  847. int count;
  848. int align;
  849. int base;
  850. int qpn;
  851. switch (op) {
  852. case RES_OP_RESERVE:
  853. count = get_param_l(&in_param);
  854. align = get_param_h(&in_param);
  855. err = __mlx4_qp_reserve_range(dev, count, align, &base);
  856. if (err)
  857. return err;
  858. err = add_res_range(dev, slave, base, count, RES_QP, 0);
  859. if (err) {
  860. __mlx4_qp_release_range(dev, base, count);
  861. return err;
  862. }
  863. set_param_l(out_param, base);
  864. break;
  865. case RES_OP_MAP_ICM:
  866. qpn = get_param_l(&in_param) & 0x7fffff;
  867. if (valid_reserved(dev, slave, qpn)) {
  868. err = add_res_range(dev, slave, qpn, 1, RES_QP, 0);
  869. if (err)
  870. return err;
  871. }
  872. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED,
  873. NULL, 1);
  874. if (err)
  875. return err;
  876. if (!valid_reserved(dev, slave, qpn)) {
  877. err = __mlx4_qp_alloc_icm(dev, qpn);
  878. if (err) {
  879. res_abort_move(dev, slave, RES_QP, qpn);
  880. return err;
  881. }
  882. }
  883. res_end_move(dev, slave, RES_QP, qpn);
  884. break;
  885. default:
  886. err = -EINVAL;
  887. break;
  888. }
  889. return err;
  890. }
  891. static int mtt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  892. u64 in_param, u64 *out_param)
  893. {
  894. int err = -EINVAL;
  895. int base;
  896. int order;
  897. if (op != RES_OP_RESERVE_AND_MAP)
  898. return err;
  899. order = get_param_l(&in_param);
  900. base = __mlx4_alloc_mtt_range(dev, order);
  901. if (base == -1)
  902. return -ENOMEM;
  903. err = add_res_range(dev, slave, base, 1, RES_MTT, order);
  904. if (err)
  905. __mlx4_free_mtt_range(dev, base, order);
  906. else
  907. set_param_l(out_param, base);
  908. return err;
  909. }
  910. static int mpt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  911. u64 in_param, u64 *out_param)
  912. {
  913. int err = -EINVAL;
  914. int index;
  915. int id;
  916. struct res_mpt *mpt;
  917. switch (op) {
  918. case RES_OP_RESERVE:
  919. index = __mlx4_mr_reserve(dev);
  920. if (index == -1)
  921. break;
  922. id = index & mpt_mask(dev);
  923. err = add_res_range(dev, slave, id, 1, RES_MPT, index);
  924. if (err) {
  925. __mlx4_mr_release(dev, index);
  926. break;
  927. }
  928. set_param_l(out_param, index);
  929. break;
  930. case RES_OP_MAP_ICM:
  931. index = get_param_l(&in_param);
  932. id = index & mpt_mask(dev);
  933. err = mr_res_start_move_to(dev, slave, id,
  934. RES_MPT_MAPPED, &mpt);
  935. if (err)
  936. return err;
  937. err = __mlx4_mr_alloc_icm(dev, mpt->key);
  938. if (err) {
  939. res_abort_move(dev, slave, RES_MPT, id);
  940. return err;
  941. }
  942. res_end_move(dev, slave, RES_MPT, id);
  943. break;
  944. }
  945. return err;
  946. }
  947. static int cq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  948. u64 in_param, u64 *out_param)
  949. {
  950. int cqn;
  951. int err;
  952. switch (op) {
  953. case RES_OP_RESERVE_AND_MAP:
  954. err = __mlx4_cq_alloc_icm(dev, &cqn);
  955. if (err)
  956. break;
  957. err = add_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  958. if (err) {
  959. __mlx4_cq_free_icm(dev, cqn);
  960. break;
  961. }
  962. set_param_l(out_param, cqn);
  963. break;
  964. default:
  965. err = -EINVAL;
  966. }
  967. return err;
  968. }
  969. static int srq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  970. u64 in_param, u64 *out_param)
  971. {
  972. int srqn;
  973. int err;
  974. switch (op) {
  975. case RES_OP_RESERVE_AND_MAP:
  976. err = __mlx4_srq_alloc_icm(dev, &srqn);
  977. if (err)
  978. break;
  979. err = add_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  980. if (err) {
  981. __mlx4_srq_free_icm(dev, srqn);
  982. break;
  983. }
  984. set_param_l(out_param, srqn);
  985. break;
  986. default:
  987. err = -EINVAL;
  988. }
  989. return err;
  990. }
  991. static int mac_add_to_slave(struct mlx4_dev *dev, int slave, u64 mac, int port)
  992. {
  993. struct mlx4_priv *priv = mlx4_priv(dev);
  994. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  995. struct mac_res *res;
  996. res = kzalloc(sizeof *res, GFP_KERNEL);
  997. if (!res)
  998. return -ENOMEM;
  999. res->mac = mac;
  1000. res->port = (u8) port;
  1001. list_add_tail(&res->list,
  1002. &tracker->slave_list[slave].res_list[RES_MAC]);
  1003. return 0;
  1004. }
  1005. static void mac_del_from_slave(struct mlx4_dev *dev, int slave, u64 mac,
  1006. int port)
  1007. {
  1008. struct mlx4_priv *priv = mlx4_priv(dev);
  1009. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1010. struct list_head *mac_list =
  1011. &tracker->slave_list[slave].res_list[RES_MAC];
  1012. struct mac_res *res, *tmp;
  1013. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1014. if (res->mac == mac && res->port == (u8) port) {
  1015. list_del(&res->list);
  1016. kfree(res);
  1017. break;
  1018. }
  1019. }
  1020. }
  1021. static void rem_slave_macs(struct mlx4_dev *dev, int slave)
  1022. {
  1023. struct mlx4_priv *priv = mlx4_priv(dev);
  1024. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1025. struct list_head *mac_list =
  1026. &tracker->slave_list[slave].res_list[RES_MAC];
  1027. struct mac_res *res, *tmp;
  1028. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1029. list_del(&res->list);
  1030. __mlx4_unregister_mac(dev, res->port, res->mac);
  1031. kfree(res);
  1032. }
  1033. }
  1034. static int mac_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1035. u64 in_param, u64 *out_param)
  1036. {
  1037. int err = -EINVAL;
  1038. int port;
  1039. u64 mac;
  1040. if (op != RES_OP_RESERVE_AND_MAP)
  1041. return err;
  1042. port = get_param_l(out_param);
  1043. mac = in_param;
  1044. err = __mlx4_register_mac(dev, port, mac);
  1045. if (err >= 0) {
  1046. set_param_l(out_param, err);
  1047. err = 0;
  1048. }
  1049. if (!err) {
  1050. err = mac_add_to_slave(dev, slave, mac, port);
  1051. if (err)
  1052. __mlx4_unregister_mac(dev, port, mac);
  1053. }
  1054. return err;
  1055. }
  1056. static int vlan_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1057. u64 in_param, u64 *out_param)
  1058. {
  1059. return 0;
  1060. }
  1061. int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
  1062. struct mlx4_vhcr *vhcr,
  1063. struct mlx4_cmd_mailbox *inbox,
  1064. struct mlx4_cmd_mailbox *outbox,
  1065. struct mlx4_cmd_info *cmd)
  1066. {
  1067. int err;
  1068. int alop = vhcr->op_modifier;
  1069. switch (vhcr->in_modifier) {
  1070. case RES_QP:
  1071. err = qp_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1072. vhcr->in_param, &vhcr->out_param);
  1073. break;
  1074. case RES_MTT:
  1075. err = mtt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1076. vhcr->in_param, &vhcr->out_param);
  1077. break;
  1078. case RES_MPT:
  1079. err = mpt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1080. vhcr->in_param, &vhcr->out_param);
  1081. break;
  1082. case RES_CQ:
  1083. err = cq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1084. vhcr->in_param, &vhcr->out_param);
  1085. break;
  1086. case RES_SRQ:
  1087. err = srq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1088. vhcr->in_param, &vhcr->out_param);
  1089. break;
  1090. case RES_MAC:
  1091. err = mac_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1092. vhcr->in_param, &vhcr->out_param);
  1093. break;
  1094. case RES_VLAN:
  1095. err = vlan_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1096. vhcr->in_param, &vhcr->out_param);
  1097. break;
  1098. default:
  1099. err = -EINVAL;
  1100. break;
  1101. }
  1102. return err;
  1103. }
  1104. static int qp_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1105. u64 in_param)
  1106. {
  1107. int err;
  1108. int count;
  1109. int base;
  1110. int qpn;
  1111. switch (op) {
  1112. case RES_OP_RESERVE:
  1113. base = get_param_l(&in_param) & 0x7fffff;
  1114. count = get_param_h(&in_param);
  1115. err = rem_res_range(dev, slave, base, count, RES_QP, 0);
  1116. if (err)
  1117. break;
  1118. __mlx4_qp_release_range(dev, base, count);
  1119. break;
  1120. case RES_OP_MAP_ICM:
  1121. qpn = get_param_l(&in_param) & 0x7fffff;
  1122. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_RESERVED,
  1123. NULL, 0);
  1124. if (err)
  1125. return err;
  1126. if (!valid_reserved(dev, slave, qpn))
  1127. __mlx4_qp_free_icm(dev, qpn);
  1128. res_end_move(dev, slave, RES_QP, qpn);
  1129. if (valid_reserved(dev, slave, qpn))
  1130. err = rem_res_range(dev, slave, qpn, 1, RES_QP, 0);
  1131. break;
  1132. default:
  1133. err = -EINVAL;
  1134. break;
  1135. }
  1136. return err;
  1137. }
  1138. static int mtt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1139. u64 in_param, u64 *out_param)
  1140. {
  1141. int err = -EINVAL;
  1142. int base;
  1143. int order;
  1144. if (op != RES_OP_RESERVE_AND_MAP)
  1145. return err;
  1146. base = get_param_l(&in_param);
  1147. order = get_param_h(&in_param);
  1148. err = rem_res_range(dev, slave, base, 1, RES_MTT, order);
  1149. if (!err)
  1150. __mlx4_free_mtt_range(dev, base, order);
  1151. return err;
  1152. }
  1153. static int mpt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1154. u64 in_param)
  1155. {
  1156. int err = -EINVAL;
  1157. int index;
  1158. int id;
  1159. struct res_mpt *mpt;
  1160. switch (op) {
  1161. case RES_OP_RESERVE:
  1162. index = get_param_l(&in_param);
  1163. id = index & mpt_mask(dev);
  1164. err = get_res(dev, slave, id, RES_MPT, &mpt);
  1165. if (err)
  1166. break;
  1167. index = mpt->key;
  1168. put_res(dev, slave, id, RES_MPT);
  1169. err = rem_res_range(dev, slave, id, 1, RES_MPT, 0);
  1170. if (err)
  1171. break;
  1172. __mlx4_mr_release(dev, index);
  1173. break;
  1174. case RES_OP_MAP_ICM:
  1175. index = get_param_l(&in_param);
  1176. id = index & mpt_mask(dev);
  1177. err = mr_res_start_move_to(dev, slave, id,
  1178. RES_MPT_RESERVED, &mpt);
  1179. if (err)
  1180. return err;
  1181. __mlx4_mr_free_icm(dev, mpt->key);
  1182. res_end_move(dev, slave, RES_MPT, id);
  1183. return err;
  1184. break;
  1185. default:
  1186. err = -EINVAL;
  1187. break;
  1188. }
  1189. return err;
  1190. }
  1191. static int cq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1192. u64 in_param, u64 *out_param)
  1193. {
  1194. int cqn;
  1195. int err;
  1196. switch (op) {
  1197. case RES_OP_RESERVE_AND_MAP:
  1198. cqn = get_param_l(&in_param);
  1199. err = rem_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  1200. if (err)
  1201. break;
  1202. __mlx4_cq_free_icm(dev, cqn);
  1203. break;
  1204. default:
  1205. err = -EINVAL;
  1206. break;
  1207. }
  1208. return err;
  1209. }
  1210. static int srq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1211. u64 in_param, u64 *out_param)
  1212. {
  1213. int srqn;
  1214. int err;
  1215. switch (op) {
  1216. case RES_OP_RESERVE_AND_MAP:
  1217. srqn = get_param_l(&in_param);
  1218. err = rem_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  1219. if (err)
  1220. break;
  1221. __mlx4_srq_free_icm(dev, srqn);
  1222. break;
  1223. default:
  1224. err = -EINVAL;
  1225. break;
  1226. }
  1227. return err;
  1228. }
  1229. static int mac_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1230. u64 in_param, u64 *out_param)
  1231. {
  1232. int port;
  1233. int err = 0;
  1234. switch (op) {
  1235. case RES_OP_RESERVE_AND_MAP:
  1236. port = get_param_l(out_param);
  1237. mac_del_from_slave(dev, slave, in_param, port);
  1238. __mlx4_unregister_mac(dev, port, in_param);
  1239. break;
  1240. default:
  1241. err = -EINVAL;
  1242. break;
  1243. }
  1244. return err;
  1245. }
  1246. static int vlan_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1247. u64 in_param, u64 *out_param)
  1248. {
  1249. return 0;
  1250. }
  1251. int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
  1252. struct mlx4_vhcr *vhcr,
  1253. struct mlx4_cmd_mailbox *inbox,
  1254. struct mlx4_cmd_mailbox *outbox,
  1255. struct mlx4_cmd_info *cmd)
  1256. {
  1257. int err = -EINVAL;
  1258. int alop = vhcr->op_modifier;
  1259. switch (vhcr->in_modifier) {
  1260. case RES_QP:
  1261. err = qp_free_res(dev, slave, vhcr->op_modifier, alop,
  1262. vhcr->in_param);
  1263. break;
  1264. case RES_MTT:
  1265. err = mtt_free_res(dev, slave, vhcr->op_modifier, alop,
  1266. vhcr->in_param, &vhcr->out_param);
  1267. break;
  1268. case RES_MPT:
  1269. err = mpt_free_res(dev, slave, vhcr->op_modifier, alop,
  1270. vhcr->in_param);
  1271. break;
  1272. case RES_CQ:
  1273. err = cq_free_res(dev, slave, vhcr->op_modifier, alop,
  1274. vhcr->in_param, &vhcr->out_param);
  1275. break;
  1276. case RES_SRQ:
  1277. err = srq_free_res(dev, slave, vhcr->op_modifier, alop,
  1278. vhcr->in_param, &vhcr->out_param);
  1279. break;
  1280. case RES_MAC:
  1281. err = mac_free_res(dev, slave, vhcr->op_modifier, alop,
  1282. vhcr->in_param, &vhcr->out_param);
  1283. break;
  1284. case RES_VLAN:
  1285. err = vlan_free_res(dev, slave, vhcr->op_modifier, alop,
  1286. vhcr->in_param, &vhcr->out_param);
  1287. break;
  1288. default:
  1289. break;
  1290. }
  1291. return err;
  1292. }
  1293. /* ugly but other choices are uglier */
  1294. static int mr_phys_mpt(struct mlx4_mpt_entry *mpt)
  1295. {
  1296. return (be32_to_cpu(mpt->flags) >> 9) & 1;
  1297. }
  1298. static int mr_get_mtt_addr(struct mlx4_mpt_entry *mpt)
  1299. {
  1300. return (int)be64_to_cpu(mpt->mtt_addr) & 0xfffffff8;
  1301. }
  1302. static int mr_get_mtt_size(struct mlx4_mpt_entry *mpt)
  1303. {
  1304. return be32_to_cpu(mpt->mtt_sz);
  1305. }
  1306. static int mr_get_pdn(struct mlx4_mpt_entry *mpt)
  1307. {
  1308. return be32_to_cpu(mpt->pd_flags) & 0xffffff;
  1309. }
  1310. static int qp_get_mtt_addr(struct mlx4_qp_context *qpc)
  1311. {
  1312. return be32_to_cpu(qpc->mtt_base_addr_l) & 0xfffffff8;
  1313. }
  1314. static int srq_get_mtt_addr(struct mlx4_srq_context *srqc)
  1315. {
  1316. return be32_to_cpu(srqc->mtt_base_addr_l) & 0xfffffff8;
  1317. }
  1318. static int qp_get_mtt_size(struct mlx4_qp_context *qpc)
  1319. {
  1320. int page_shift = (qpc->log_page_size & 0x3f) + 12;
  1321. int log_sq_size = (qpc->sq_size_stride >> 3) & 0xf;
  1322. int log_sq_sride = qpc->sq_size_stride & 7;
  1323. int log_rq_size = (qpc->rq_size_stride >> 3) & 0xf;
  1324. int log_rq_stride = qpc->rq_size_stride & 7;
  1325. int srq = (be32_to_cpu(qpc->srqn) >> 24) & 1;
  1326. int rss = (be32_to_cpu(qpc->flags) >> 13) & 1;
  1327. int xrc = (be32_to_cpu(qpc->local_qpn) >> 23) & 1;
  1328. int sq_size;
  1329. int rq_size;
  1330. int total_pages;
  1331. int total_mem;
  1332. int page_offset = (be32_to_cpu(qpc->params2) >> 6) & 0x3f;
  1333. sq_size = 1 << (log_sq_size + log_sq_sride + 4);
  1334. rq_size = (srq|rss|xrc) ? 0 : (1 << (log_rq_size + log_rq_stride + 4));
  1335. total_mem = sq_size + rq_size;
  1336. total_pages =
  1337. roundup_pow_of_two((total_mem + (page_offset << 6)) >>
  1338. page_shift);
  1339. return total_pages;
  1340. }
  1341. static int qp_get_pdn(struct mlx4_qp_context *qpc)
  1342. {
  1343. return be32_to_cpu(qpc->pd) & 0xffffff;
  1344. }
  1345. static int pdn2slave(int pdn)
  1346. {
  1347. return (pdn >> NOT_MASKED_PD_BITS) - 1;
  1348. }
  1349. static int check_mtt_range(struct mlx4_dev *dev, int slave, int start,
  1350. int size, struct res_mtt *mtt)
  1351. {
  1352. int res_start = mtt->com.res_id;
  1353. int res_size = (1 << mtt->order);
  1354. if (start < res_start || start + size > res_start + res_size)
  1355. return -EPERM;
  1356. return 0;
  1357. }
  1358. int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1359. struct mlx4_vhcr *vhcr,
  1360. struct mlx4_cmd_mailbox *inbox,
  1361. struct mlx4_cmd_mailbox *outbox,
  1362. struct mlx4_cmd_info *cmd)
  1363. {
  1364. int err;
  1365. int index = vhcr->in_modifier;
  1366. struct res_mtt *mtt;
  1367. struct res_mpt *mpt;
  1368. int mtt_base = mr_get_mtt_addr(inbox->buf) / dev->caps.mtt_entry_sz;
  1369. int phys;
  1370. int id;
  1371. id = index & mpt_mask(dev);
  1372. err = mr_res_start_move_to(dev, slave, id, RES_MPT_HW, &mpt);
  1373. if (err)
  1374. return err;
  1375. phys = mr_phys_mpt(inbox->buf);
  1376. if (!phys) {
  1377. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1378. if (err)
  1379. goto ex_abort;
  1380. err = check_mtt_range(dev, slave, mtt_base,
  1381. mr_get_mtt_size(inbox->buf), mtt);
  1382. if (err)
  1383. goto ex_put;
  1384. mpt->mtt = mtt;
  1385. }
  1386. if (pdn2slave(mr_get_pdn(inbox->buf)) != slave) {
  1387. err = -EPERM;
  1388. goto ex_put;
  1389. }
  1390. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1391. if (err)
  1392. goto ex_put;
  1393. if (!phys) {
  1394. atomic_inc(&mtt->ref_count);
  1395. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1396. }
  1397. res_end_move(dev, slave, RES_MPT, id);
  1398. return 0;
  1399. ex_put:
  1400. if (!phys)
  1401. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1402. ex_abort:
  1403. res_abort_move(dev, slave, RES_MPT, id);
  1404. return err;
  1405. }
  1406. int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1407. struct mlx4_vhcr *vhcr,
  1408. struct mlx4_cmd_mailbox *inbox,
  1409. struct mlx4_cmd_mailbox *outbox,
  1410. struct mlx4_cmd_info *cmd)
  1411. {
  1412. int err;
  1413. int index = vhcr->in_modifier;
  1414. struct res_mpt *mpt;
  1415. int id;
  1416. id = index & mpt_mask(dev);
  1417. err = mr_res_start_move_to(dev, slave, id, RES_MPT_MAPPED, &mpt);
  1418. if (err)
  1419. return err;
  1420. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1421. if (err)
  1422. goto ex_abort;
  1423. if (mpt->mtt)
  1424. atomic_dec(&mpt->mtt->ref_count);
  1425. res_end_move(dev, slave, RES_MPT, id);
  1426. return 0;
  1427. ex_abort:
  1428. res_abort_move(dev, slave, RES_MPT, id);
  1429. return err;
  1430. }
  1431. int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1432. struct mlx4_vhcr *vhcr,
  1433. struct mlx4_cmd_mailbox *inbox,
  1434. struct mlx4_cmd_mailbox *outbox,
  1435. struct mlx4_cmd_info *cmd)
  1436. {
  1437. int err;
  1438. int index = vhcr->in_modifier;
  1439. struct res_mpt *mpt;
  1440. int id;
  1441. id = index & mpt_mask(dev);
  1442. err = get_res(dev, slave, id, RES_MPT, &mpt);
  1443. if (err)
  1444. return err;
  1445. if (mpt->com.from_state != RES_MPT_HW) {
  1446. err = -EBUSY;
  1447. goto out;
  1448. }
  1449. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1450. out:
  1451. put_res(dev, slave, id, RES_MPT);
  1452. return err;
  1453. }
  1454. static int qp_get_rcqn(struct mlx4_qp_context *qpc)
  1455. {
  1456. return be32_to_cpu(qpc->cqn_recv) & 0xffffff;
  1457. }
  1458. static int qp_get_scqn(struct mlx4_qp_context *qpc)
  1459. {
  1460. return be32_to_cpu(qpc->cqn_send) & 0xffffff;
  1461. }
  1462. static u32 qp_get_srqn(struct mlx4_qp_context *qpc)
  1463. {
  1464. return be32_to_cpu(qpc->srqn) & 0x1ffffff;
  1465. }
  1466. int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
  1467. struct mlx4_vhcr *vhcr,
  1468. struct mlx4_cmd_mailbox *inbox,
  1469. struct mlx4_cmd_mailbox *outbox,
  1470. struct mlx4_cmd_info *cmd)
  1471. {
  1472. int err;
  1473. int qpn = vhcr->in_modifier & 0x7fffff;
  1474. struct res_mtt *mtt;
  1475. struct res_qp *qp;
  1476. struct mlx4_qp_context *qpc = inbox->buf + 8;
  1477. int mtt_base = qp_get_mtt_addr(qpc) / dev->caps.mtt_entry_sz;
  1478. int mtt_size = qp_get_mtt_size(qpc);
  1479. struct res_cq *rcq;
  1480. struct res_cq *scq;
  1481. int rcqn = qp_get_rcqn(qpc);
  1482. int scqn = qp_get_scqn(qpc);
  1483. u32 srqn = qp_get_srqn(qpc) & 0xffffff;
  1484. int use_srq = (qp_get_srqn(qpc) >> 24) & 1;
  1485. struct res_srq *srq;
  1486. int local_qpn = be32_to_cpu(qpc->local_qpn) & 0xffffff;
  1487. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_HW, &qp, 0);
  1488. if (err)
  1489. return err;
  1490. qp->local_qpn = local_qpn;
  1491. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1492. if (err)
  1493. goto ex_abort;
  1494. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  1495. if (err)
  1496. goto ex_put_mtt;
  1497. if (pdn2slave(qp_get_pdn(qpc)) != slave) {
  1498. err = -EPERM;
  1499. goto ex_put_mtt;
  1500. }
  1501. err = get_res(dev, slave, rcqn, RES_CQ, &rcq);
  1502. if (err)
  1503. goto ex_put_mtt;
  1504. if (scqn != rcqn) {
  1505. err = get_res(dev, slave, scqn, RES_CQ, &scq);
  1506. if (err)
  1507. goto ex_put_rcq;
  1508. } else
  1509. scq = rcq;
  1510. if (use_srq) {
  1511. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  1512. if (err)
  1513. goto ex_put_scq;
  1514. }
  1515. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1516. if (err)
  1517. goto ex_put_srq;
  1518. atomic_inc(&mtt->ref_count);
  1519. qp->mtt = mtt;
  1520. atomic_inc(&rcq->ref_count);
  1521. qp->rcq = rcq;
  1522. atomic_inc(&scq->ref_count);
  1523. qp->scq = scq;
  1524. if (scqn != rcqn)
  1525. put_res(dev, slave, scqn, RES_CQ);
  1526. if (use_srq) {
  1527. atomic_inc(&srq->ref_count);
  1528. put_res(dev, slave, srqn, RES_SRQ);
  1529. qp->srq = srq;
  1530. }
  1531. put_res(dev, slave, rcqn, RES_CQ);
  1532. put_res(dev, slave, mtt_base, RES_MTT);
  1533. res_end_move(dev, slave, RES_QP, qpn);
  1534. return 0;
  1535. ex_put_srq:
  1536. if (use_srq)
  1537. put_res(dev, slave, srqn, RES_SRQ);
  1538. ex_put_scq:
  1539. if (scqn != rcqn)
  1540. put_res(dev, slave, scqn, RES_CQ);
  1541. ex_put_rcq:
  1542. put_res(dev, slave, rcqn, RES_CQ);
  1543. ex_put_mtt:
  1544. put_res(dev, slave, mtt_base, RES_MTT);
  1545. ex_abort:
  1546. res_abort_move(dev, slave, RES_QP, qpn);
  1547. return err;
  1548. }
  1549. static int eq_get_mtt_addr(struct mlx4_eq_context *eqc)
  1550. {
  1551. return be32_to_cpu(eqc->mtt_base_addr_l) & 0xfffffff8;
  1552. }
  1553. static int eq_get_mtt_size(struct mlx4_eq_context *eqc)
  1554. {
  1555. int log_eq_size = eqc->log_eq_size & 0x1f;
  1556. int page_shift = (eqc->log_page_size & 0x3f) + 12;
  1557. if (log_eq_size + 5 < page_shift)
  1558. return 1;
  1559. return 1 << (log_eq_size + 5 - page_shift);
  1560. }
  1561. static int cq_get_mtt_addr(struct mlx4_cq_context *cqc)
  1562. {
  1563. return be32_to_cpu(cqc->mtt_base_addr_l) & 0xfffffff8;
  1564. }
  1565. static int cq_get_mtt_size(struct mlx4_cq_context *cqc)
  1566. {
  1567. int log_cq_size = (be32_to_cpu(cqc->logsize_usrpage) >> 24) & 0x1f;
  1568. int page_shift = (cqc->log_page_size & 0x3f) + 12;
  1569. if (log_cq_size + 5 < page_shift)
  1570. return 1;
  1571. return 1 << (log_cq_size + 5 - page_shift);
  1572. }
  1573. int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1574. struct mlx4_vhcr *vhcr,
  1575. struct mlx4_cmd_mailbox *inbox,
  1576. struct mlx4_cmd_mailbox *outbox,
  1577. struct mlx4_cmd_info *cmd)
  1578. {
  1579. int err;
  1580. int eqn = vhcr->in_modifier;
  1581. int res_id = (slave << 8) | eqn;
  1582. struct mlx4_eq_context *eqc = inbox->buf;
  1583. int mtt_base = eq_get_mtt_addr(eqc) / dev->caps.mtt_entry_sz;
  1584. int mtt_size = eq_get_mtt_size(eqc);
  1585. struct res_eq *eq;
  1586. struct res_mtt *mtt;
  1587. err = add_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1588. if (err)
  1589. return err;
  1590. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_HW, &eq);
  1591. if (err)
  1592. goto out_add;
  1593. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1594. if (err)
  1595. goto out_move;
  1596. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  1597. if (err)
  1598. goto out_put;
  1599. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1600. if (err)
  1601. goto out_put;
  1602. atomic_inc(&mtt->ref_count);
  1603. eq->mtt = mtt;
  1604. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1605. res_end_move(dev, slave, RES_EQ, res_id);
  1606. return 0;
  1607. out_put:
  1608. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1609. out_move:
  1610. res_abort_move(dev, slave, RES_EQ, res_id);
  1611. out_add:
  1612. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1613. return err;
  1614. }
  1615. static int get_containing_mtt(struct mlx4_dev *dev, int slave, int start,
  1616. int len, struct res_mtt **res)
  1617. {
  1618. struct mlx4_priv *priv = mlx4_priv(dev);
  1619. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1620. struct res_mtt *mtt;
  1621. int err = -EINVAL;
  1622. spin_lock_irq(mlx4_tlock(dev));
  1623. list_for_each_entry(mtt, &tracker->slave_list[slave].res_list[RES_MTT],
  1624. com.list) {
  1625. if (!check_mtt_range(dev, slave, start, len, mtt)) {
  1626. *res = mtt;
  1627. mtt->com.from_state = mtt->com.state;
  1628. mtt->com.state = RES_MTT_BUSY;
  1629. err = 0;
  1630. break;
  1631. }
  1632. }
  1633. spin_unlock_irq(mlx4_tlock(dev));
  1634. return err;
  1635. }
  1636. int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
  1637. struct mlx4_vhcr *vhcr,
  1638. struct mlx4_cmd_mailbox *inbox,
  1639. struct mlx4_cmd_mailbox *outbox,
  1640. struct mlx4_cmd_info *cmd)
  1641. {
  1642. struct mlx4_mtt mtt;
  1643. __be64 *page_list = inbox->buf;
  1644. u64 *pg_list = (u64 *)page_list;
  1645. int i;
  1646. struct res_mtt *rmtt = NULL;
  1647. int start = be64_to_cpu(page_list[0]);
  1648. int npages = vhcr->in_modifier;
  1649. int err;
  1650. err = get_containing_mtt(dev, slave, start, npages, &rmtt);
  1651. if (err)
  1652. return err;
  1653. /* Call the SW implementation of write_mtt:
  1654. * - Prepare a dummy mtt struct
  1655. * - Translate inbox contents to simple addresses in host endianess */
  1656. mtt.offset = 0; /* TBD this is broken but I don't handle it since
  1657. we don't really use it */
  1658. mtt.order = 0;
  1659. mtt.page_shift = 0;
  1660. for (i = 0; i < npages; ++i)
  1661. pg_list[i + 2] = (be64_to_cpu(page_list[i + 2]) & ~1ULL);
  1662. err = __mlx4_write_mtt(dev, &mtt, be64_to_cpu(page_list[0]), npages,
  1663. ((u64 *)page_list + 2));
  1664. if (rmtt)
  1665. put_res(dev, slave, rmtt->com.res_id, RES_MTT);
  1666. return err;
  1667. }
  1668. int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1669. struct mlx4_vhcr *vhcr,
  1670. struct mlx4_cmd_mailbox *inbox,
  1671. struct mlx4_cmd_mailbox *outbox,
  1672. struct mlx4_cmd_info *cmd)
  1673. {
  1674. int eqn = vhcr->in_modifier;
  1675. int res_id = eqn | (slave << 8);
  1676. struct res_eq *eq;
  1677. int err;
  1678. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_RESERVED, &eq);
  1679. if (err)
  1680. return err;
  1681. err = get_res(dev, slave, eq->mtt->com.res_id, RES_MTT, NULL);
  1682. if (err)
  1683. goto ex_abort;
  1684. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1685. if (err)
  1686. goto ex_put;
  1687. atomic_dec(&eq->mtt->ref_count);
  1688. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  1689. res_end_move(dev, slave, RES_EQ, res_id);
  1690. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1691. return 0;
  1692. ex_put:
  1693. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  1694. ex_abort:
  1695. res_abort_move(dev, slave, RES_EQ, res_id);
  1696. return err;
  1697. }
  1698. int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe)
  1699. {
  1700. struct mlx4_priv *priv = mlx4_priv(dev);
  1701. struct mlx4_slave_event_eq_info *event_eq;
  1702. struct mlx4_cmd_mailbox *mailbox;
  1703. u32 in_modifier = 0;
  1704. int err;
  1705. int res_id;
  1706. struct res_eq *req;
  1707. if (!priv->mfunc.master.slave_state)
  1708. return -EINVAL;
  1709. event_eq = &priv->mfunc.master.slave_state[slave].event_eq;
  1710. /* Create the event only if the slave is registered */
  1711. if ((event_eq->event_type & (1 << eqe->type)) == 0)
  1712. return 0;
  1713. mutex_lock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  1714. res_id = (slave << 8) | event_eq->eqn;
  1715. err = get_res(dev, slave, res_id, RES_EQ, &req);
  1716. if (err)
  1717. goto unlock;
  1718. if (req->com.from_state != RES_EQ_HW) {
  1719. err = -EINVAL;
  1720. goto put;
  1721. }
  1722. mailbox = mlx4_alloc_cmd_mailbox(dev);
  1723. if (IS_ERR(mailbox)) {
  1724. err = PTR_ERR(mailbox);
  1725. goto put;
  1726. }
  1727. if (eqe->type == MLX4_EVENT_TYPE_CMD) {
  1728. ++event_eq->token;
  1729. eqe->event.cmd.token = cpu_to_be16(event_eq->token);
  1730. }
  1731. memcpy(mailbox->buf, (u8 *) eqe, 28);
  1732. in_modifier = (slave & 0xff) | ((event_eq->eqn & 0xff) << 16);
  1733. err = mlx4_cmd(dev, mailbox->dma, in_modifier, 0,
  1734. MLX4_CMD_GEN_EQE, MLX4_CMD_TIME_CLASS_B,
  1735. MLX4_CMD_NATIVE);
  1736. put_res(dev, slave, res_id, RES_EQ);
  1737. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  1738. mlx4_free_cmd_mailbox(dev, mailbox);
  1739. return err;
  1740. put:
  1741. put_res(dev, slave, res_id, RES_EQ);
  1742. unlock:
  1743. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  1744. return err;
  1745. }
  1746. int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1747. struct mlx4_vhcr *vhcr,
  1748. struct mlx4_cmd_mailbox *inbox,
  1749. struct mlx4_cmd_mailbox *outbox,
  1750. struct mlx4_cmd_info *cmd)
  1751. {
  1752. int eqn = vhcr->in_modifier;
  1753. int res_id = eqn | (slave << 8);
  1754. struct res_eq *eq;
  1755. int err;
  1756. err = get_res(dev, slave, res_id, RES_EQ, &eq);
  1757. if (err)
  1758. return err;
  1759. if (eq->com.from_state != RES_EQ_HW) {
  1760. err = -EINVAL;
  1761. goto ex_put;
  1762. }
  1763. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1764. ex_put:
  1765. put_res(dev, slave, res_id, RES_EQ);
  1766. return err;
  1767. }
  1768. int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1769. struct mlx4_vhcr *vhcr,
  1770. struct mlx4_cmd_mailbox *inbox,
  1771. struct mlx4_cmd_mailbox *outbox,
  1772. struct mlx4_cmd_info *cmd)
  1773. {
  1774. int err;
  1775. int cqn = vhcr->in_modifier;
  1776. struct mlx4_cq_context *cqc = inbox->buf;
  1777. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  1778. struct res_cq *cq;
  1779. struct res_mtt *mtt;
  1780. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_HW, &cq);
  1781. if (err)
  1782. return err;
  1783. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1784. if (err)
  1785. goto out_move;
  1786. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  1787. if (err)
  1788. goto out_put;
  1789. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1790. if (err)
  1791. goto out_put;
  1792. atomic_inc(&mtt->ref_count);
  1793. cq->mtt = mtt;
  1794. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1795. res_end_move(dev, slave, RES_CQ, cqn);
  1796. return 0;
  1797. out_put:
  1798. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1799. out_move:
  1800. res_abort_move(dev, slave, RES_CQ, cqn);
  1801. return err;
  1802. }
  1803. int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1804. struct mlx4_vhcr *vhcr,
  1805. struct mlx4_cmd_mailbox *inbox,
  1806. struct mlx4_cmd_mailbox *outbox,
  1807. struct mlx4_cmd_info *cmd)
  1808. {
  1809. int err;
  1810. int cqn = vhcr->in_modifier;
  1811. struct res_cq *cq;
  1812. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_ALLOCATED, &cq);
  1813. if (err)
  1814. return err;
  1815. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1816. if (err)
  1817. goto out_move;
  1818. atomic_dec(&cq->mtt->ref_count);
  1819. res_end_move(dev, slave, RES_CQ, cqn);
  1820. return 0;
  1821. out_move:
  1822. res_abort_move(dev, slave, RES_CQ, cqn);
  1823. return err;
  1824. }
  1825. int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1826. struct mlx4_vhcr *vhcr,
  1827. struct mlx4_cmd_mailbox *inbox,
  1828. struct mlx4_cmd_mailbox *outbox,
  1829. struct mlx4_cmd_info *cmd)
  1830. {
  1831. int cqn = vhcr->in_modifier;
  1832. struct res_cq *cq;
  1833. int err;
  1834. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  1835. if (err)
  1836. return err;
  1837. if (cq->com.from_state != RES_CQ_HW)
  1838. goto ex_put;
  1839. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1840. ex_put:
  1841. put_res(dev, slave, cqn, RES_CQ);
  1842. return err;
  1843. }
  1844. static int handle_resize(struct mlx4_dev *dev, int slave,
  1845. struct mlx4_vhcr *vhcr,
  1846. struct mlx4_cmd_mailbox *inbox,
  1847. struct mlx4_cmd_mailbox *outbox,
  1848. struct mlx4_cmd_info *cmd,
  1849. struct res_cq *cq)
  1850. {
  1851. int err;
  1852. struct res_mtt *orig_mtt;
  1853. struct res_mtt *mtt;
  1854. struct mlx4_cq_context *cqc = inbox->buf;
  1855. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  1856. err = get_res(dev, slave, cq->mtt->com.res_id, RES_MTT, &orig_mtt);
  1857. if (err)
  1858. return err;
  1859. if (orig_mtt != cq->mtt) {
  1860. err = -EINVAL;
  1861. goto ex_put;
  1862. }
  1863. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1864. if (err)
  1865. goto ex_put;
  1866. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  1867. if (err)
  1868. goto ex_put1;
  1869. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1870. if (err)
  1871. goto ex_put1;
  1872. atomic_dec(&orig_mtt->ref_count);
  1873. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  1874. atomic_inc(&mtt->ref_count);
  1875. cq->mtt = mtt;
  1876. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1877. return 0;
  1878. ex_put1:
  1879. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1880. ex_put:
  1881. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  1882. return err;
  1883. }
  1884. int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1885. struct mlx4_vhcr *vhcr,
  1886. struct mlx4_cmd_mailbox *inbox,
  1887. struct mlx4_cmd_mailbox *outbox,
  1888. struct mlx4_cmd_info *cmd)
  1889. {
  1890. int cqn = vhcr->in_modifier;
  1891. struct res_cq *cq;
  1892. int err;
  1893. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  1894. if (err)
  1895. return err;
  1896. if (cq->com.from_state != RES_CQ_HW)
  1897. goto ex_put;
  1898. if (vhcr->op_modifier == 0) {
  1899. err = handle_resize(dev, slave, vhcr, inbox, outbox, cmd, cq);
  1900. if (err)
  1901. goto ex_put;
  1902. }
  1903. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1904. ex_put:
  1905. put_res(dev, slave, cqn, RES_CQ);
  1906. return err;
  1907. }
  1908. static int srq_get_pdn(struct mlx4_srq_context *srqc)
  1909. {
  1910. return be32_to_cpu(srqc->pd) & 0xffffff;
  1911. }
  1912. static int srq_get_mtt_size(struct mlx4_srq_context *srqc)
  1913. {
  1914. int log_srq_size = (be32_to_cpu(srqc->state_logsize_srqn) >> 24) & 0xf;
  1915. int log_rq_stride = srqc->logstride & 7;
  1916. int page_shift = (srqc->log_page_size & 0x3f) + 12;
  1917. if (log_srq_size + log_rq_stride + 4 < page_shift)
  1918. return 1;
  1919. return 1 << (log_srq_size + log_rq_stride + 4 - page_shift);
  1920. }
  1921. int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  1922. struct mlx4_vhcr *vhcr,
  1923. struct mlx4_cmd_mailbox *inbox,
  1924. struct mlx4_cmd_mailbox *outbox,
  1925. struct mlx4_cmd_info *cmd)
  1926. {
  1927. int err;
  1928. int srqn = vhcr->in_modifier;
  1929. struct res_mtt *mtt;
  1930. struct res_srq *srq;
  1931. struct mlx4_srq_context *srqc = inbox->buf;
  1932. int mtt_base = srq_get_mtt_addr(srqc) / dev->caps.mtt_entry_sz;
  1933. if (srqn != (be32_to_cpu(srqc->state_logsize_srqn) & 0xffffff))
  1934. return -EINVAL;
  1935. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_HW, &srq);
  1936. if (err)
  1937. return err;
  1938. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1939. if (err)
  1940. goto ex_abort;
  1941. err = check_mtt_range(dev, slave, mtt_base, srq_get_mtt_size(srqc),
  1942. mtt);
  1943. if (err)
  1944. goto ex_put_mtt;
  1945. if (pdn2slave(srq_get_pdn(srqc)) != slave) {
  1946. err = -EPERM;
  1947. goto ex_put_mtt;
  1948. }
  1949. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1950. if (err)
  1951. goto ex_put_mtt;
  1952. atomic_inc(&mtt->ref_count);
  1953. srq->mtt = mtt;
  1954. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1955. res_end_move(dev, slave, RES_SRQ, srqn);
  1956. return 0;
  1957. ex_put_mtt:
  1958. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1959. ex_abort:
  1960. res_abort_move(dev, slave, RES_SRQ, srqn);
  1961. return err;
  1962. }
  1963. int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  1964. struct mlx4_vhcr *vhcr,
  1965. struct mlx4_cmd_mailbox *inbox,
  1966. struct mlx4_cmd_mailbox *outbox,
  1967. struct mlx4_cmd_info *cmd)
  1968. {
  1969. int err;
  1970. int srqn = vhcr->in_modifier;
  1971. struct res_srq *srq;
  1972. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_ALLOCATED, &srq);
  1973. if (err)
  1974. return err;
  1975. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1976. if (err)
  1977. goto ex_abort;
  1978. atomic_dec(&srq->mtt->ref_count);
  1979. if (srq->cq)
  1980. atomic_dec(&srq->cq->ref_count);
  1981. res_end_move(dev, slave, RES_SRQ, srqn);
  1982. return 0;
  1983. ex_abort:
  1984. res_abort_move(dev, slave, RES_SRQ, srqn);
  1985. return err;
  1986. }
  1987. int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  1988. struct mlx4_vhcr *vhcr,
  1989. struct mlx4_cmd_mailbox *inbox,
  1990. struct mlx4_cmd_mailbox *outbox,
  1991. struct mlx4_cmd_info *cmd)
  1992. {
  1993. int err;
  1994. int srqn = vhcr->in_modifier;
  1995. struct res_srq *srq;
  1996. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  1997. if (err)
  1998. return err;
  1999. if (srq->com.from_state != RES_SRQ_HW) {
  2000. err = -EBUSY;
  2001. goto out;
  2002. }
  2003. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2004. out:
  2005. put_res(dev, slave, srqn, RES_SRQ);
  2006. return err;
  2007. }
  2008. int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2009. struct mlx4_vhcr *vhcr,
  2010. struct mlx4_cmd_mailbox *inbox,
  2011. struct mlx4_cmd_mailbox *outbox,
  2012. struct mlx4_cmd_info *cmd)
  2013. {
  2014. int err;
  2015. int srqn = vhcr->in_modifier;
  2016. struct res_srq *srq;
  2017. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  2018. if (err)
  2019. return err;
  2020. if (srq->com.from_state != RES_SRQ_HW) {
  2021. err = -EBUSY;
  2022. goto out;
  2023. }
  2024. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2025. out:
  2026. put_res(dev, slave, srqn, RES_SRQ);
  2027. return err;
  2028. }
  2029. int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
  2030. struct mlx4_vhcr *vhcr,
  2031. struct mlx4_cmd_mailbox *inbox,
  2032. struct mlx4_cmd_mailbox *outbox,
  2033. struct mlx4_cmd_info *cmd)
  2034. {
  2035. int err;
  2036. int qpn = vhcr->in_modifier & 0x7fffff;
  2037. struct res_qp *qp;
  2038. err = get_res(dev, slave, qpn, RES_QP, &qp);
  2039. if (err)
  2040. return err;
  2041. if (qp->com.from_state != RES_QP_HW) {
  2042. err = -EBUSY;
  2043. goto out;
  2044. }
  2045. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2046. out:
  2047. put_res(dev, slave, qpn, RES_QP);
  2048. return err;
  2049. }
  2050. int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
  2051. struct mlx4_vhcr *vhcr,
  2052. struct mlx4_cmd_mailbox *inbox,
  2053. struct mlx4_cmd_mailbox *outbox,
  2054. struct mlx4_cmd_info *cmd)
  2055. {
  2056. struct mlx4_qp_context *qpc = inbox->buf + 8;
  2057. update_ud_gid(dev, qpc, (u8)slave);
  2058. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2059. }
  2060. int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
  2061. struct mlx4_vhcr *vhcr,
  2062. struct mlx4_cmd_mailbox *inbox,
  2063. struct mlx4_cmd_mailbox *outbox,
  2064. struct mlx4_cmd_info *cmd)
  2065. {
  2066. int err;
  2067. int qpn = vhcr->in_modifier & 0x7fffff;
  2068. struct res_qp *qp;
  2069. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED, &qp, 0);
  2070. if (err)
  2071. return err;
  2072. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2073. if (err)
  2074. goto ex_abort;
  2075. atomic_dec(&qp->mtt->ref_count);
  2076. atomic_dec(&qp->rcq->ref_count);
  2077. atomic_dec(&qp->scq->ref_count);
  2078. if (qp->srq)
  2079. atomic_dec(&qp->srq->ref_count);
  2080. res_end_move(dev, slave, RES_QP, qpn);
  2081. return 0;
  2082. ex_abort:
  2083. res_abort_move(dev, slave, RES_QP, qpn);
  2084. return err;
  2085. }
  2086. static struct res_gid *find_gid(struct mlx4_dev *dev, int slave,
  2087. struct res_qp *rqp, u8 *gid)
  2088. {
  2089. struct res_gid *res;
  2090. list_for_each_entry(res, &rqp->mcg_list, list) {
  2091. if (!memcmp(res->gid, gid, 16))
  2092. return res;
  2093. }
  2094. return NULL;
  2095. }
  2096. static int add_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  2097. u8 *gid, enum mlx4_protocol prot)
  2098. {
  2099. struct res_gid *res;
  2100. int err;
  2101. res = kzalloc(sizeof *res, GFP_KERNEL);
  2102. if (!res)
  2103. return -ENOMEM;
  2104. spin_lock_irq(&rqp->mcg_spl);
  2105. if (find_gid(dev, slave, rqp, gid)) {
  2106. kfree(res);
  2107. err = -EEXIST;
  2108. } else {
  2109. memcpy(res->gid, gid, 16);
  2110. res->prot = prot;
  2111. list_add_tail(&res->list, &rqp->mcg_list);
  2112. err = 0;
  2113. }
  2114. spin_unlock_irq(&rqp->mcg_spl);
  2115. return err;
  2116. }
  2117. static int rem_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  2118. u8 *gid, enum mlx4_protocol prot)
  2119. {
  2120. struct res_gid *res;
  2121. int err;
  2122. spin_lock_irq(&rqp->mcg_spl);
  2123. res = find_gid(dev, slave, rqp, gid);
  2124. if (!res || res->prot != prot)
  2125. err = -EINVAL;
  2126. else {
  2127. list_del(&res->list);
  2128. kfree(res);
  2129. err = 0;
  2130. }
  2131. spin_unlock_irq(&rqp->mcg_spl);
  2132. return err;
  2133. }
  2134. int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
  2135. struct mlx4_vhcr *vhcr,
  2136. struct mlx4_cmd_mailbox *inbox,
  2137. struct mlx4_cmd_mailbox *outbox,
  2138. struct mlx4_cmd_info *cmd)
  2139. {
  2140. struct mlx4_qp qp; /* dummy for calling attach/detach */
  2141. u8 *gid = inbox->buf;
  2142. enum mlx4_protocol prot = (vhcr->in_modifier >> 28) & 0x7;
  2143. int err, err1;
  2144. int qpn;
  2145. struct res_qp *rqp;
  2146. int attach = vhcr->op_modifier;
  2147. int block_loopback = vhcr->in_modifier >> 31;
  2148. u8 steer_type_mask = 2;
  2149. enum mlx4_steer_type type = gid[7] & steer_type_mask;
  2150. qpn = vhcr->in_modifier & 0xffffff;
  2151. err = get_res(dev, slave, qpn, RES_QP, &rqp);
  2152. if (err)
  2153. return err;
  2154. qp.qpn = qpn;
  2155. if (attach) {
  2156. err = add_mcg_res(dev, slave, rqp, gid, prot);
  2157. if (err)
  2158. goto ex_put;
  2159. err = mlx4_qp_attach_common(dev, &qp, gid,
  2160. block_loopback, prot, type);
  2161. if (err)
  2162. goto ex_rem;
  2163. } else {
  2164. err = rem_mcg_res(dev, slave, rqp, gid, prot);
  2165. if (err)
  2166. goto ex_put;
  2167. err = mlx4_qp_detach_common(dev, &qp, gid, prot, type);
  2168. }
  2169. put_res(dev, slave, qpn, RES_QP);
  2170. return 0;
  2171. ex_rem:
  2172. /* ignore error return below, already in error */
  2173. err1 = rem_mcg_res(dev, slave, rqp, gid, prot);
  2174. ex_put:
  2175. put_res(dev, slave, qpn, RES_QP);
  2176. return err;
  2177. }
  2178. enum {
  2179. BUSY_MAX_RETRIES = 10
  2180. };
  2181. int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
  2182. struct mlx4_vhcr *vhcr,
  2183. struct mlx4_cmd_mailbox *inbox,
  2184. struct mlx4_cmd_mailbox *outbox,
  2185. struct mlx4_cmd_info *cmd)
  2186. {
  2187. int err;
  2188. int index = vhcr->in_modifier & 0xffff;
  2189. err = get_res(dev, slave, index, RES_COUNTER, NULL);
  2190. if (err)
  2191. return err;
  2192. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2193. put_res(dev, slave, index, RES_COUNTER);
  2194. return err;
  2195. }
  2196. static void detach_qp(struct mlx4_dev *dev, int slave, struct res_qp *rqp)
  2197. {
  2198. struct res_gid *rgid;
  2199. struct res_gid *tmp;
  2200. int err;
  2201. struct mlx4_qp qp; /* dummy for calling attach/detach */
  2202. list_for_each_entry_safe(rgid, tmp, &rqp->mcg_list, list) {
  2203. qp.qpn = rqp->local_qpn;
  2204. err = mlx4_qp_detach_common(dev, &qp, rgid->gid, rgid->prot,
  2205. MLX4_MC_STEER);
  2206. list_del(&rgid->list);
  2207. kfree(rgid);
  2208. }
  2209. }
  2210. static int _move_all_busy(struct mlx4_dev *dev, int slave,
  2211. enum mlx4_resource type, int print)
  2212. {
  2213. struct mlx4_priv *priv = mlx4_priv(dev);
  2214. struct mlx4_resource_tracker *tracker =
  2215. &priv->mfunc.master.res_tracker;
  2216. struct list_head *rlist = &tracker->slave_list[slave].res_list[type];
  2217. struct res_common *r;
  2218. struct res_common *tmp;
  2219. int busy;
  2220. busy = 0;
  2221. spin_lock_irq(mlx4_tlock(dev));
  2222. list_for_each_entry_safe(r, tmp, rlist, list) {
  2223. if (r->owner == slave) {
  2224. if (!r->removing) {
  2225. if (r->state == RES_ANY_BUSY) {
  2226. if (print)
  2227. mlx4_dbg(dev,
  2228. "%s id 0x%x is busy\n",
  2229. ResourceType(type),
  2230. r->res_id);
  2231. ++busy;
  2232. } else {
  2233. r->from_state = r->state;
  2234. r->state = RES_ANY_BUSY;
  2235. r->removing = 1;
  2236. }
  2237. }
  2238. }
  2239. }
  2240. spin_unlock_irq(mlx4_tlock(dev));
  2241. return busy;
  2242. }
  2243. static int move_all_busy(struct mlx4_dev *dev, int slave,
  2244. enum mlx4_resource type)
  2245. {
  2246. unsigned long begin;
  2247. int busy;
  2248. begin = jiffies;
  2249. do {
  2250. busy = _move_all_busy(dev, slave, type, 0);
  2251. if (time_after(jiffies, begin + 5 * HZ))
  2252. break;
  2253. if (busy)
  2254. cond_resched();
  2255. } while (busy);
  2256. if (busy)
  2257. busy = _move_all_busy(dev, slave, type, 1);
  2258. return busy;
  2259. }
  2260. static void rem_slave_qps(struct mlx4_dev *dev, int slave)
  2261. {
  2262. struct mlx4_priv *priv = mlx4_priv(dev);
  2263. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2264. struct list_head *qp_list =
  2265. &tracker->slave_list[slave].res_list[RES_QP];
  2266. struct res_qp *qp;
  2267. struct res_qp *tmp;
  2268. int state;
  2269. u64 in_param;
  2270. int qpn;
  2271. int err;
  2272. err = move_all_busy(dev, slave, RES_QP);
  2273. if (err)
  2274. mlx4_warn(dev, "rem_slave_qps: Could not move all qps to busy"
  2275. "for slave %d\n", slave);
  2276. spin_lock_irq(mlx4_tlock(dev));
  2277. list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
  2278. spin_unlock_irq(mlx4_tlock(dev));
  2279. if (qp->com.owner == slave) {
  2280. qpn = qp->com.res_id;
  2281. detach_qp(dev, slave, qp);
  2282. state = qp->com.from_state;
  2283. while (state != 0) {
  2284. switch (state) {
  2285. case RES_QP_RESERVED:
  2286. spin_lock_irq(mlx4_tlock(dev));
  2287. radix_tree_delete(&tracker->res_tree[RES_QP],
  2288. qp->com.res_id);
  2289. list_del(&qp->com.list);
  2290. spin_unlock_irq(mlx4_tlock(dev));
  2291. kfree(qp);
  2292. state = 0;
  2293. break;
  2294. case RES_QP_MAPPED:
  2295. if (!valid_reserved(dev, slave, qpn))
  2296. __mlx4_qp_free_icm(dev, qpn);
  2297. state = RES_QP_RESERVED;
  2298. break;
  2299. case RES_QP_HW:
  2300. in_param = slave;
  2301. err = mlx4_cmd(dev, in_param,
  2302. qp->local_qpn, 2,
  2303. MLX4_CMD_2RST_QP,
  2304. MLX4_CMD_TIME_CLASS_A,
  2305. MLX4_CMD_NATIVE);
  2306. if (err)
  2307. mlx4_dbg(dev, "rem_slave_qps: failed"
  2308. " to move slave %d qpn %d to"
  2309. " reset\n", slave,
  2310. qp->local_qpn);
  2311. atomic_dec(&qp->rcq->ref_count);
  2312. atomic_dec(&qp->scq->ref_count);
  2313. atomic_dec(&qp->mtt->ref_count);
  2314. if (qp->srq)
  2315. atomic_dec(&qp->srq->ref_count);
  2316. state = RES_QP_MAPPED;
  2317. break;
  2318. default:
  2319. state = 0;
  2320. }
  2321. }
  2322. }
  2323. spin_lock_irq(mlx4_tlock(dev));
  2324. }
  2325. spin_unlock_irq(mlx4_tlock(dev));
  2326. }
  2327. static void rem_slave_srqs(struct mlx4_dev *dev, int slave)
  2328. {
  2329. struct mlx4_priv *priv = mlx4_priv(dev);
  2330. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2331. struct list_head *srq_list =
  2332. &tracker->slave_list[slave].res_list[RES_SRQ];
  2333. struct res_srq *srq;
  2334. struct res_srq *tmp;
  2335. int state;
  2336. u64 in_param;
  2337. LIST_HEAD(tlist);
  2338. int srqn;
  2339. int err;
  2340. err = move_all_busy(dev, slave, RES_SRQ);
  2341. if (err)
  2342. mlx4_warn(dev, "rem_slave_srqs: Could not move all srqs to "
  2343. "busy for slave %d\n", slave);
  2344. spin_lock_irq(mlx4_tlock(dev));
  2345. list_for_each_entry_safe(srq, tmp, srq_list, com.list) {
  2346. spin_unlock_irq(mlx4_tlock(dev));
  2347. if (srq->com.owner == slave) {
  2348. srqn = srq->com.res_id;
  2349. state = srq->com.from_state;
  2350. while (state != 0) {
  2351. switch (state) {
  2352. case RES_SRQ_ALLOCATED:
  2353. __mlx4_srq_free_icm(dev, srqn);
  2354. spin_lock_irq(mlx4_tlock(dev));
  2355. radix_tree_delete(&tracker->res_tree[RES_SRQ],
  2356. srqn);
  2357. list_del(&srq->com.list);
  2358. spin_unlock_irq(mlx4_tlock(dev));
  2359. kfree(srq);
  2360. state = 0;
  2361. break;
  2362. case RES_SRQ_HW:
  2363. in_param = slave;
  2364. err = mlx4_cmd(dev, in_param, srqn, 1,
  2365. MLX4_CMD_HW2SW_SRQ,
  2366. MLX4_CMD_TIME_CLASS_A,
  2367. MLX4_CMD_NATIVE);
  2368. if (err)
  2369. mlx4_dbg(dev, "rem_slave_srqs: failed"
  2370. " to move slave %d srq %d to"
  2371. " SW ownership\n",
  2372. slave, srqn);
  2373. atomic_dec(&srq->mtt->ref_count);
  2374. if (srq->cq)
  2375. atomic_dec(&srq->cq->ref_count);
  2376. state = RES_SRQ_ALLOCATED;
  2377. break;
  2378. default:
  2379. state = 0;
  2380. }
  2381. }
  2382. }
  2383. spin_lock_irq(mlx4_tlock(dev));
  2384. }
  2385. spin_unlock_irq(mlx4_tlock(dev));
  2386. }
  2387. static void rem_slave_cqs(struct mlx4_dev *dev, int slave)
  2388. {
  2389. struct mlx4_priv *priv = mlx4_priv(dev);
  2390. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2391. struct list_head *cq_list =
  2392. &tracker->slave_list[slave].res_list[RES_CQ];
  2393. struct res_cq *cq;
  2394. struct res_cq *tmp;
  2395. int state;
  2396. u64 in_param;
  2397. LIST_HEAD(tlist);
  2398. int cqn;
  2399. int err;
  2400. err = move_all_busy(dev, slave, RES_CQ);
  2401. if (err)
  2402. mlx4_warn(dev, "rem_slave_cqs: Could not move all cqs to "
  2403. "busy for slave %d\n", slave);
  2404. spin_lock_irq(mlx4_tlock(dev));
  2405. list_for_each_entry_safe(cq, tmp, cq_list, com.list) {
  2406. spin_unlock_irq(mlx4_tlock(dev));
  2407. if (cq->com.owner == slave && !atomic_read(&cq->ref_count)) {
  2408. cqn = cq->com.res_id;
  2409. state = cq->com.from_state;
  2410. while (state != 0) {
  2411. switch (state) {
  2412. case RES_CQ_ALLOCATED:
  2413. __mlx4_cq_free_icm(dev, cqn);
  2414. spin_lock_irq(mlx4_tlock(dev));
  2415. radix_tree_delete(&tracker->res_tree[RES_CQ],
  2416. cqn);
  2417. list_del(&cq->com.list);
  2418. spin_unlock_irq(mlx4_tlock(dev));
  2419. kfree(cq);
  2420. state = 0;
  2421. break;
  2422. case RES_CQ_HW:
  2423. in_param = slave;
  2424. err = mlx4_cmd(dev, in_param, cqn, 1,
  2425. MLX4_CMD_HW2SW_CQ,
  2426. MLX4_CMD_TIME_CLASS_A,
  2427. MLX4_CMD_NATIVE);
  2428. if (err)
  2429. mlx4_dbg(dev, "rem_slave_cqs: failed"
  2430. " to move slave %d cq %d to"
  2431. " SW ownership\n",
  2432. slave, cqn);
  2433. atomic_dec(&cq->mtt->ref_count);
  2434. state = RES_CQ_ALLOCATED;
  2435. break;
  2436. default:
  2437. state = 0;
  2438. }
  2439. }
  2440. }
  2441. spin_lock_irq(mlx4_tlock(dev));
  2442. }
  2443. spin_unlock_irq(mlx4_tlock(dev));
  2444. }
  2445. static void rem_slave_mrs(struct mlx4_dev *dev, int slave)
  2446. {
  2447. struct mlx4_priv *priv = mlx4_priv(dev);
  2448. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2449. struct list_head *mpt_list =
  2450. &tracker->slave_list[slave].res_list[RES_MPT];
  2451. struct res_mpt *mpt;
  2452. struct res_mpt *tmp;
  2453. int state;
  2454. u64 in_param;
  2455. LIST_HEAD(tlist);
  2456. int mptn;
  2457. int err;
  2458. err = move_all_busy(dev, slave, RES_MPT);
  2459. if (err)
  2460. mlx4_warn(dev, "rem_slave_mrs: Could not move all mpts to "
  2461. "busy for slave %d\n", slave);
  2462. spin_lock_irq(mlx4_tlock(dev));
  2463. list_for_each_entry_safe(mpt, tmp, mpt_list, com.list) {
  2464. spin_unlock_irq(mlx4_tlock(dev));
  2465. if (mpt->com.owner == slave) {
  2466. mptn = mpt->com.res_id;
  2467. state = mpt->com.from_state;
  2468. while (state != 0) {
  2469. switch (state) {
  2470. case RES_MPT_RESERVED:
  2471. __mlx4_mr_release(dev, mpt->key);
  2472. spin_lock_irq(mlx4_tlock(dev));
  2473. radix_tree_delete(&tracker->res_tree[RES_MPT],
  2474. mptn);
  2475. list_del(&mpt->com.list);
  2476. spin_unlock_irq(mlx4_tlock(dev));
  2477. kfree(mpt);
  2478. state = 0;
  2479. break;
  2480. case RES_MPT_MAPPED:
  2481. __mlx4_mr_free_icm(dev, mpt->key);
  2482. state = RES_MPT_RESERVED;
  2483. break;
  2484. case RES_MPT_HW:
  2485. in_param = slave;
  2486. err = mlx4_cmd(dev, in_param, mptn, 0,
  2487. MLX4_CMD_HW2SW_MPT,
  2488. MLX4_CMD_TIME_CLASS_A,
  2489. MLX4_CMD_NATIVE);
  2490. if (err)
  2491. mlx4_dbg(dev, "rem_slave_mrs: failed"
  2492. " to move slave %d mpt %d to"
  2493. " SW ownership\n",
  2494. slave, mptn);
  2495. if (mpt->mtt)
  2496. atomic_dec(&mpt->mtt->ref_count);
  2497. state = RES_MPT_MAPPED;
  2498. break;
  2499. default:
  2500. state = 0;
  2501. }
  2502. }
  2503. }
  2504. spin_lock_irq(mlx4_tlock(dev));
  2505. }
  2506. spin_unlock_irq(mlx4_tlock(dev));
  2507. }
  2508. static void rem_slave_mtts(struct mlx4_dev *dev, int slave)
  2509. {
  2510. struct mlx4_priv *priv = mlx4_priv(dev);
  2511. struct mlx4_resource_tracker *tracker =
  2512. &priv->mfunc.master.res_tracker;
  2513. struct list_head *mtt_list =
  2514. &tracker->slave_list[slave].res_list[RES_MTT];
  2515. struct res_mtt *mtt;
  2516. struct res_mtt *tmp;
  2517. int state;
  2518. LIST_HEAD(tlist);
  2519. int base;
  2520. int err;
  2521. err = move_all_busy(dev, slave, RES_MTT);
  2522. if (err)
  2523. mlx4_warn(dev, "rem_slave_mtts: Could not move all mtts to "
  2524. "busy for slave %d\n", slave);
  2525. spin_lock_irq(mlx4_tlock(dev));
  2526. list_for_each_entry_safe(mtt, tmp, mtt_list, com.list) {
  2527. spin_unlock_irq(mlx4_tlock(dev));
  2528. if (mtt->com.owner == slave) {
  2529. base = mtt->com.res_id;
  2530. state = mtt->com.from_state;
  2531. while (state != 0) {
  2532. switch (state) {
  2533. case RES_MTT_ALLOCATED:
  2534. __mlx4_free_mtt_range(dev, base,
  2535. mtt->order);
  2536. spin_lock_irq(mlx4_tlock(dev));
  2537. radix_tree_delete(&tracker->res_tree[RES_MTT],
  2538. base);
  2539. list_del(&mtt->com.list);
  2540. spin_unlock_irq(mlx4_tlock(dev));
  2541. kfree(mtt);
  2542. state = 0;
  2543. break;
  2544. default:
  2545. state = 0;
  2546. }
  2547. }
  2548. }
  2549. spin_lock_irq(mlx4_tlock(dev));
  2550. }
  2551. spin_unlock_irq(mlx4_tlock(dev));
  2552. }
  2553. static void rem_slave_eqs(struct mlx4_dev *dev, int slave)
  2554. {
  2555. struct mlx4_priv *priv = mlx4_priv(dev);
  2556. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2557. struct list_head *eq_list =
  2558. &tracker->slave_list[slave].res_list[RES_EQ];
  2559. struct res_eq *eq;
  2560. struct res_eq *tmp;
  2561. int err;
  2562. int state;
  2563. LIST_HEAD(tlist);
  2564. int eqn;
  2565. struct mlx4_cmd_mailbox *mailbox;
  2566. err = move_all_busy(dev, slave, RES_EQ);
  2567. if (err)
  2568. mlx4_warn(dev, "rem_slave_eqs: Could not move all eqs to "
  2569. "busy for slave %d\n", slave);
  2570. spin_lock_irq(mlx4_tlock(dev));
  2571. list_for_each_entry_safe(eq, tmp, eq_list, com.list) {
  2572. spin_unlock_irq(mlx4_tlock(dev));
  2573. if (eq->com.owner == slave) {
  2574. eqn = eq->com.res_id;
  2575. state = eq->com.from_state;
  2576. while (state != 0) {
  2577. switch (state) {
  2578. case RES_EQ_RESERVED:
  2579. spin_lock_irq(mlx4_tlock(dev));
  2580. radix_tree_delete(&tracker->res_tree[RES_EQ],
  2581. eqn);
  2582. list_del(&eq->com.list);
  2583. spin_unlock_irq(mlx4_tlock(dev));
  2584. kfree(eq);
  2585. state = 0;
  2586. break;
  2587. case RES_EQ_HW:
  2588. mailbox = mlx4_alloc_cmd_mailbox(dev);
  2589. if (IS_ERR(mailbox)) {
  2590. cond_resched();
  2591. continue;
  2592. }
  2593. err = mlx4_cmd_box(dev, slave, 0,
  2594. eqn & 0xff, 0,
  2595. MLX4_CMD_HW2SW_EQ,
  2596. MLX4_CMD_TIME_CLASS_A,
  2597. MLX4_CMD_NATIVE);
  2598. mlx4_dbg(dev, "rem_slave_eqs: failed"
  2599. " to move slave %d eqs %d to"
  2600. " SW ownership\n", slave, eqn);
  2601. mlx4_free_cmd_mailbox(dev, mailbox);
  2602. if (!err) {
  2603. atomic_dec(&eq->mtt->ref_count);
  2604. state = RES_EQ_RESERVED;
  2605. }
  2606. break;
  2607. default:
  2608. state = 0;
  2609. }
  2610. }
  2611. }
  2612. spin_lock_irq(mlx4_tlock(dev));
  2613. }
  2614. spin_unlock_irq(mlx4_tlock(dev));
  2615. }
  2616. void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave)
  2617. {
  2618. struct mlx4_priv *priv = mlx4_priv(dev);
  2619. mutex_lock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  2620. /*VLAN*/
  2621. rem_slave_macs(dev, slave);
  2622. rem_slave_qps(dev, slave);
  2623. rem_slave_srqs(dev, slave);
  2624. rem_slave_cqs(dev, slave);
  2625. rem_slave_mrs(dev, slave);
  2626. rem_slave_eqs(dev, slave);
  2627. rem_slave_mtts(dev, slave);
  2628. mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  2629. }