port.c 23 KB

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  1. /*
  2. * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/errno.h>
  33. #include <linux/if_ether.h>
  34. #include <linux/export.h>
  35. #include <linux/mlx4/cmd.h>
  36. #include "mlx4.h"
  37. #define MLX4_MAC_VALID (1ull << 63)
  38. #define MLX4_MAC_MASK 0xffffffffffffULL
  39. #define MLX4_VLAN_VALID (1u << 31)
  40. #define MLX4_VLAN_MASK 0xfff
  41. void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table)
  42. {
  43. int i;
  44. mutex_init(&table->mutex);
  45. for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
  46. table->entries[i] = 0;
  47. table->refs[i] = 0;
  48. }
  49. table->max = 1 << dev->caps.log_num_macs;
  50. table->total = 0;
  51. }
  52. void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table)
  53. {
  54. int i;
  55. mutex_init(&table->mutex);
  56. for (i = 0; i < MLX4_MAX_VLAN_NUM; i++) {
  57. table->entries[i] = 0;
  58. table->refs[i] = 0;
  59. }
  60. table->max = (1 << dev->caps.log_num_vlans) - MLX4_VLAN_REGULAR;
  61. table->total = 0;
  62. }
  63. static int mlx4_uc_steer_add(struct mlx4_dev *dev, u8 port, u64 mac, int *qpn)
  64. {
  65. struct mlx4_qp qp;
  66. u8 gid[16] = {0};
  67. int err;
  68. qp.qpn = *qpn;
  69. mac &= 0xffffffffffffULL;
  70. mac = cpu_to_be64(mac << 16);
  71. memcpy(&gid[10], &mac, ETH_ALEN);
  72. gid[5] = port;
  73. gid[7] = MLX4_UC_STEER << 1;
  74. err = mlx4_unicast_attach(dev, &qp, gid, 0, MLX4_PROT_ETH);
  75. if (err)
  76. mlx4_warn(dev, "Failed Attaching Unicast\n");
  77. return err;
  78. }
  79. static void mlx4_uc_steer_release(struct mlx4_dev *dev, u8 port,
  80. u64 mac, int qpn)
  81. {
  82. struct mlx4_qp qp;
  83. u8 gid[16] = {0};
  84. qp.qpn = qpn;
  85. mac &= 0xffffffffffffULL;
  86. mac = cpu_to_be64(mac << 16);
  87. memcpy(&gid[10], &mac, ETH_ALEN);
  88. gid[5] = port;
  89. gid[7] = MLX4_UC_STEER << 1;
  90. mlx4_unicast_detach(dev, &qp, gid, MLX4_PROT_ETH);
  91. }
  92. static int validate_index(struct mlx4_dev *dev,
  93. struct mlx4_mac_table *table, int index)
  94. {
  95. int err = 0;
  96. if (index < 0 || index >= table->max || !table->entries[index]) {
  97. mlx4_warn(dev, "No valid Mac entry for the given index\n");
  98. err = -EINVAL;
  99. }
  100. return err;
  101. }
  102. static int find_index(struct mlx4_dev *dev,
  103. struct mlx4_mac_table *table, u64 mac)
  104. {
  105. int i;
  106. for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
  107. if ((mac & MLX4_MAC_MASK) ==
  108. (MLX4_MAC_MASK & be64_to_cpu(table->entries[i])))
  109. return i;
  110. }
  111. /* Mac not found */
  112. return -EINVAL;
  113. }
  114. int mlx4_get_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int *qpn)
  115. {
  116. struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
  117. struct mlx4_mac_entry *entry;
  118. int index = 0;
  119. int err = 0;
  120. mlx4_dbg(dev, "Registering MAC: 0x%llx for adding\n",
  121. (unsigned long long) mac);
  122. index = mlx4_register_mac(dev, port, mac);
  123. if (index < 0) {
  124. err = index;
  125. mlx4_err(dev, "Failed adding MAC: 0x%llx\n",
  126. (unsigned long long) mac);
  127. return err;
  128. }
  129. if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER)) {
  130. *qpn = info->base_qpn + index;
  131. return 0;
  132. }
  133. err = mlx4_qp_reserve_range(dev, 1, 1, qpn);
  134. mlx4_dbg(dev, "Reserved qp %d\n", *qpn);
  135. if (err) {
  136. mlx4_err(dev, "Failed to reserve qp for mac registration\n");
  137. goto qp_err;
  138. }
  139. err = mlx4_uc_steer_add(dev, port, mac, qpn);
  140. if (err)
  141. goto steer_err;
  142. entry = kmalloc(sizeof *entry, GFP_KERNEL);
  143. if (!entry) {
  144. err = -ENOMEM;
  145. goto alloc_err;
  146. }
  147. entry->mac = mac;
  148. err = radix_tree_insert(&info->mac_tree, *qpn, entry);
  149. if (err)
  150. goto insert_err;
  151. return 0;
  152. insert_err:
  153. kfree(entry);
  154. alloc_err:
  155. mlx4_uc_steer_release(dev, port, mac, *qpn);
  156. steer_err:
  157. mlx4_qp_release_range(dev, *qpn, 1);
  158. qp_err:
  159. mlx4_unregister_mac(dev, port, mac);
  160. return err;
  161. }
  162. EXPORT_SYMBOL_GPL(mlx4_get_eth_qp);
  163. void mlx4_put_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int qpn)
  164. {
  165. struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
  166. struct mlx4_mac_entry *entry;
  167. mlx4_dbg(dev, "Registering MAC: 0x%llx for deleting\n",
  168. (unsigned long long) mac);
  169. mlx4_unregister_mac(dev, port, mac);
  170. if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER) {
  171. entry = radix_tree_lookup(&info->mac_tree, qpn);
  172. if (entry) {
  173. mlx4_dbg(dev, "Releasing qp: port %d, mac 0x%llx,"
  174. " qpn %d\n", port,
  175. (unsigned long long) mac, qpn);
  176. mlx4_uc_steer_release(dev, port, entry->mac, qpn);
  177. mlx4_qp_release_range(dev, qpn, 1);
  178. radix_tree_delete(&info->mac_tree, qpn);
  179. kfree(entry);
  180. }
  181. }
  182. }
  183. EXPORT_SYMBOL_GPL(mlx4_put_eth_qp);
  184. static int mlx4_set_port_mac_table(struct mlx4_dev *dev, u8 port,
  185. __be64 *entries)
  186. {
  187. struct mlx4_cmd_mailbox *mailbox;
  188. u32 in_mod;
  189. int err;
  190. mailbox = mlx4_alloc_cmd_mailbox(dev);
  191. if (IS_ERR(mailbox))
  192. return PTR_ERR(mailbox);
  193. memcpy(mailbox->buf, entries, MLX4_MAC_TABLE_SIZE);
  194. in_mod = MLX4_SET_PORT_MAC_TABLE << 8 | port;
  195. err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
  196. MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
  197. mlx4_free_cmd_mailbox(dev, mailbox);
  198. return err;
  199. }
  200. int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac)
  201. {
  202. struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
  203. struct mlx4_mac_table *table = &info->mac_table;
  204. int i, err = 0;
  205. int free = -1;
  206. mlx4_dbg(dev, "Registering MAC: 0x%llx for port %d\n",
  207. (unsigned long long) mac, port);
  208. mutex_lock(&table->mutex);
  209. for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
  210. if (free < 0 && !table->entries[i]) {
  211. free = i;
  212. continue;
  213. }
  214. if (mac == (MLX4_MAC_MASK & be64_to_cpu(table->entries[i]))) {
  215. /* MAC already registered, Must not have duplicates */
  216. err = -EEXIST;
  217. goto out;
  218. }
  219. }
  220. mlx4_dbg(dev, "Free MAC index is %d\n", free);
  221. if (table->total == table->max) {
  222. /* No free mac entries */
  223. err = -ENOSPC;
  224. goto out;
  225. }
  226. /* Register new MAC */
  227. table->entries[free] = cpu_to_be64(mac | MLX4_MAC_VALID);
  228. err = mlx4_set_port_mac_table(dev, port, table->entries);
  229. if (unlikely(err)) {
  230. mlx4_err(dev, "Failed adding MAC: 0x%llx\n",
  231. (unsigned long long) mac);
  232. table->entries[free] = 0;
  233. goto out;
  234. }
  235. err = free;
  236. ++table->total;
  237. out:
  238. mutex_unlock(&table->mutex);
  239. return err;
  240. }
  241. EXPORT_SYMBOL_GPL(__mlx4_register_mac);
  242. int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac)
  243. {
  244. u64 out_param;
  245. int err;
  246. if (mlx4_is_mfunc(dev)) {
  247. set_param_l(&out_param, port);
  248. err = mlx4_cmd_imm(dev, mac, &out_param, RES_MAC,
  249. RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
  250. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
  251. if (err)
  252. return err;
  253. return get_param_l(&out_param);
  254. }
  255. return __mlx4_register_mac(dev, port, mac);
  256. }
  257. EXPORT_SYMBOL_GPL(mlx4_register_mac);
  258. void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac)
  259. {
  260. struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
  261. struct mlx4_mac_table *table = &info->mac_table;
  262. int index;
  263. index = find_index(dev, table, mac);
  264. mutex_lock(&table->mutex);
  265. if (validate_index(dev, table, index))
  266. goto out;
  267. table->entries[index] = 0;
  268. mlx4_set_port_mac_table(dev, port, table->entries);
  269. --table->total;
  270. out:
  271. mutex_unlock(&table->mutex);
  272. }
  273. EXPORT_SYMBOL_GPL(__mlx4_unregister_mac);
  274. void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac)
  275. {
  276. u64 out_param;
  277. int err;
  278. if (mlx4_is_mfunc(dev)) {
  279. set_param_l(&out_param, port);
  280. err = mlx4_cmd_imm(dev, mac, &out_param, RES_MAC,
  281. RES_OP_RESERVE_AND_MAP, MLX4_CMD_FREE_RES,
  282. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
  283. return;
  284. }
  285. __mlx4_unregister_mac(dev, port, mac);
  286. return;
  287. }
  288. EXPORT_SYMBOL_GPL(mlx4_unregister_mac);
  289. int mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac)
  290. {
  291. struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
  292. struct mlx4_mac_table *table = &info->mac_table;
  293. struct mlx4_mac_entry *entry;
  294. int index = qpn - info->base_qpn;
  295. int err = 0;
  296. if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER) {
  297. entry = radix_tree_lookup(&info->mac_tree, qpn);
  298. if (!entry)
  299. return -EINVAL;
  300. mlx4_uc_steer_release(dev, port, entry->mac, qpn);
  301. mlx4_unregister_mac(dev, port, entry->mac);
  302. entry->mac = new_mac;
  303. mlx4_register_mac(dev, port, new_mac);
  304. err = mlx4_uc_steer_add(dev, port, entry->mac, &qpn);
  305. return err;
  306. }
  307. /* CX1 doesn't support multi-functions */
  308. mutex_lock(&table->mutex);
  309. err = validate_index(dev, table, index);
  310. if (err)
  311. goto out;
  312. table->entries[index] = cpu_to_be64(new_mac | MLX4_MAC_VALID);
  313. err = mlx4_set_port_mac_table(dev, port, table->entries);
  314. if (unlikely(err)) {
  315. mlx4_err(dev, "Failed adding MAC: 0x%llx\n",
  316. (unsigned long long) new_mac);
  317. table->entries[index] = 0;
  318. }
  319. out:
  320. mutex_unlock(&table->mutex);
  321. return err;
  322. }
  323. EXPORT_SYMBOL_GPL(mlx4_replace_mac);
  324. static int mlx4_set_port_vlan_table(struct mlx4_dev *dev, u8 port,
  325. __be32 *entries)
  326. {
  327. struct mlx4_cmd_mailbox *mailbox;
  328. u32 in_mod;
  329. int err;
  330. mailbox = mlx4_alloc_cmd_mailbox(dev);
  331. if (IS_ERR(mailbox))
  332. return PTR_ERR(mailbox);
  333. memcpy(mailbox->buf, entries, MLX4_VLAN_TABLE_SIZE);
  334. in_mod = MLX4_SET_PORT_VLAN_TABLE << 8 | port;
  335. err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
  336. MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
  337. mlx4_free_cmd_mailbox(dev, mailbox);
  338. return err;
  339. }
  340. int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx)
  341. {
  342. struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
  343. int i;
  344. for (i = 0; i < MLX4_MAX_VLAN_NUM; ++i) {
  345. if (table->refs[i] &&
  346. (vid == (MLX4_VLAN_MASK &
  347. be32_to_cpu(table->entries[i])))) {
  348. /* VLAN already registered, increase reference count */
  349. *idx = i;
  350. return 0;
  351. }
  352. }
  353. return -ENOENT;
  354. }
  355. EXPORT_SYMBOL_GPL(mlx4_find_cached_vlan);
  356. static int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan,
  357. int *index)
  358. {
  359. struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
  360. int i, err = 0;
  361. int free = -1;
  362. mutex_lock(&table->mutex);
  363. if (table->total == table->max) {
  364. /* No free vlan entries */
  365. err = -ENOSPC;
  366. goto out;
  367. }
  368. for (i = MLX4_VLAN_REGULAR; i < MLX4_MAX_VLAN_NUM; i++) {
  369. if (free < 0 && (table->refs[i] == 0)) {
  370. free = i;
  371. continue;
  372. }
  373. if (table->refs[i] &&
  374. (vlan == (MLX4_VLAN_MASK &
  375. be32_to_cpu(table->entries[i])))) {
  376. /* Vlan already registered, increase references count */
  377. *index = i;
  378. ++table->refs[i];
  379. goto out;
  380. }
  381. }
  382. if (free < 0) {
  383. err = -ENOMEM;
  384. goto out;
  385. }
  386. /* Register new VLAN */
  387. table->refs[free] = 1;
  388. table->entries[free] = cpu_to_be32(vlan | MLX4_VLAN_VALID);
  389. err = mlx4_set_port_vlan_table(dev, port, table->entries);
  390. if (unlikely(err)) {
  391. mlx4_warn(dev, "Failed adding vlan: %u\n", vlan);
  392. table->refs[free] = 0;
  393. table->entries[free] = 0;
  394. goto out;
  395. }
  396. *index = free;
  397. ++table->total;
  398. out:
  399. mutex_unlock(&table->mutex);
  400. return err;
  401. }
  402. int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index)
  403. {
  404. u64 out_param;
  405. int err;
  406. if (mlx4_is_mfunc(dev)) {
  407. set_param_l(&out_param, port);
  408. err = mlx4_cmd_imm(dev, vlan, &out_param, RES_VLAN,
  409. RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
  410. MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
  411. if (!err)
  412. *index = get_param_l(&out_param);
  413. return err;
  414. }
  415. return __mlx4_register_vlan(dev, port, vlan, index);
  416. }
  417. EXPORT_SYMBOL_GPL(mlx4_register_vlan);
  418. static void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index)
  419. {
  420. struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
  421. if (index < MLX4_VLAN_REGULAR) {
  422. mlx4_warn(dev, "Trying to free special vlan index %d\n", index);
  423. return;
  424. }
  425. mutex_lock(&table->mutex);
  426. if (!table->refs[index]) {
  427. mlx4_warn(dev, "No vlan entry for index %d\n", index);
  428. goto out;
  429. }
  430. if (--table->refs[index]) {
  431. mlx4_dbg(dev, "Have more references for index %d,"
  432. "no need to modify vlan table\n", index);
  433. goto out;
  434. }
  435. table->entries[index] = 0;
  436. mlx4_set_port_vlan_table(dev, port, table->entries);
  437. --table->total;
  438. out:
  439. mutex_unlock(&table->mutex);
  440. }
  441. void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index)
  442. {
  443. u64 in_param;
  444. int err;
  445. if (mlx4_is_mfunc(dev)) {
  446. set_param_l(&in_param, port);
  447. err = mlx4_cmd(dev, in_param, RES_VLAN, RES_OP_RESERVE_AND_MAP,
  448. MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
  449. MLX4_CMD_WRAPPED);
  450. if (!err)
  451. mlx4_warn(dev, "Failed freeing vlan at index:%d\n",
  452. index);
  453. return;
  454. }
  455. __mlx4_unregister_vlan(dev, port, index);
  456. }
  457. EXPORT_SYMBOL_GPL(mlx4_unregister_vlan);
  458. int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps)
  459. {
  460. struct mlx4_cmd_mailbox *inmailbox, *outmailbox;
  461. u8 *inbuf, *outbuf;
  462. int err;
  463. inmailbox = mlx4_alloc_cmd_mailbox(dev);
  464. if (IS_ERR(inmailbox))
  465. return PTR_ERR(inmailbox);
  466. outmailbox = mlx4_alloc_cmd_mailbox(dev);
  467. if (IS_ERR(outmailbox)) {
  468. mlx4_free_cmd_mailbox(dev, inmailbox);
  469. return PTR_ERR(outmailbox);
  470. }
  471. inbuf = inmailbox->buf;
  472. outbuf = outmailbox->buf;
  473. memset(inbuf, 0, 256);
  474. memset(outbuf, 0, 256);
  475. inbuf[0] = 1;
  476. inbuf[1] = 1;
  477. inbuf[2] = 1;
  478. inbuf[3] = 1;
  479. *(__be16 *) (&inbuf[16]) = cpu_to_be16(0x0015);
  480. *(__be32 *) (&inbuf[20]) = cpu_to_be32(port);
  481. err = mlx4_cmd_box(dev, inmailbox->dma, outmailbox->dma, port, 3,
  482. MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
  483. MLX4_CMD_NATIVE);
  484. if (!err)
  485. *caps = *(__be32 *) (outbuf + 84);
  486. mlx4_free_cmd_mailbox(dev, inmailbox);
  487. mlx4_free_cmd_mailbox(dev, outmailbox);
  488. return err;
  489. }
  490. int mlx4_check_ext_port_caps(struct mlx4_dev *dev, u8 port)
  491. {
  492. struct mlx4_cmd_mailbox *inmailbox, *outmailbox;
  493. u8 *inbuf, *outbuf;
  494. int err, packet_error;
  495. inmailbox = mlx4_alloc_cmd_mailbox(dev);
  496. if (IS_ERR(inmailbox))
  497. return PTR_ERR(inmailbox);
  498. outmailbox = mlx4_alloc_cmd_mailbox(dev);
  499. if (IS_ERR(outmailbox)) {
  500. mlx4_free_cmd_mailbox(dev, inmailbox);
  501. return PTR_ERR(outmailbox);
  502. }
  503. inbuf = inmailbox->buf;
  504. outbuf = outmailbox->buf;
  505. memset(inbuf, 0, 256);
  506. memset(outbuf, 0, 256);
  507. inbuf[0] = 1;
  508. inbuf[1] = 1;
  509. inbuf[2] = 1;
  510. inbuf[3] = 1;
  511. *(__be16 *) (&inbuf[16]) = MLX4_ATTR_EXTENDED_PORT_INFO;
  512. *(__be32 *) (&inbuf[20]) = cpu_to_be32(port);
  513. err = mlx4_cmd_box(dev, inmailbox->dma, outmailbox->dma, port, 3,
  514. MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
  515. MLX4_CMD_NATIVE);
  516. packet_error = be16_to_cpu(*(__be16 *) (outbuf + 4));
  517. dev->caps.ext_port_cap[port] = (!err && !packet_error) ?
  518. MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO
  519. : 0;
  520. mlx4_free_cmd_mailbox(dev, inmailbox);
  521. mlx4_free_cmd_mailbox(dev, outmailbox);
  522. return err;
  523. }
  524. static int mlx4_common_set_port(struct mlx4_dev *dev, int slave, u32 in_mod,
  525. u8 op_mod, struct mlx4_cmd_mailbox *inbox)
  526. {
  527. struct mlx4_priv *priv = mlx4_priv(dev);
  528. struct mlx4_port_info *port_info;
  529. struct mlx4_mfunc_master_ctx *master = &priv->mfunc.master;
  530. struct mlx4_slave_state *slave_st = &master->slave_state[slave];
  531. struct mlx4_set_port_rqp_calc_context *qpn_context;
  532. struct mlx4_set_port_general_context *gen_context;
  533. int reset_qkey_viols;
  534. int port;
  535. int is_eth;
  536. u32 in_modifier;
  537. u32 promisc;
  538. u16 mtu, prev_mtu;
  539. int err;
  540. int i;
  541. __be32 agg_cap_mask;
  542. __be32 slave_cap_mask;
  543. __be32 new_cap_mask;
  544. port = in_mod & 0xff;
  545. in_modifier = in_mod >> 8;
  546. is_eth = op_mod;
  547. port_info = &priv->port[port];
  548. /* Slaves cannot perform SET_PORT operations except changing MTU */
  549. if (is_eth) {
  550. if (slave != dev->caps.function &&
  551. in_modifier != MLX4_SET_PORT_GENERAL) {
  552. mlx4_warn(dev, "denying SET_PORT for slave:%d\n",
  553. slave);
  554. return -EINVAL;
  555. }
  556. switch (in_modifier) {
  557. case MLX4_SET_PORT_RQP_CALC:
  558. qpn_context = inbox->buf;
  559. qpn_context->base_qpn =
  560. cpu_to_be32(port_info->base_qpn);
  561. qpn_context->n_mac = 0x7;
  562. promisc = be32_to_cpu(qpn_context->promisc) >>
  563. SET_PORT_PROMISC_SHIFT;
  564. qpn_context->promisc = cpu_to_be32(
  565. promisc << SET_PORT_PROMISC_SHIFT |
  566. port_info->base_qpn);
  567. promisc = be32_to_cpu(qpn_context->mcast) >>
  568. SET_PORT_MC_PROMISC_SHIFT;
  569. qpn_context->mcast = cpu_to_be32(
  570. promisc << SET_PORT_MC_PROMISC_SHIFT |
  571. port_info->base_qpn);
  572. break;
  573. case MLX4_SET_PORT_GENERAL:
  574. gen_context = inbox->buf;
  575. /* Mtu is configured as the max MTU among all the
  576. * the functions on the port. */
  577. mtu = be16_to_cpu(gen_context->mtu);
  578. mtu = min_t(int, mtu, dev->caps.eth_mtu_cap[port]);
  579. prev_mtu = slave_st->mtu[port];
  580. slave_st->mtu[port] = mtu;
  581. if (mtu > master->max_mtu[port])
  582. master->max_mtu[port] = mtu;
  583. if (mtu < prev_mtu && prev_mtu ==
  584. master->max_mtu[port]) {
  585. slave_st->mtu[port] = mtu;
  586. master->max_mtu[port] = mtu;
  587. for (i = 0; i < dev->num_slaves; i++) {
  588. master->max_mtu[port] =
  589. max(master->max_mtu[port],
  590. master->slave_state[i].mtu[port]);
  591. }
  592. }
  593. gen_context->mtu = cpu_to_be16(master->max_mtu[port]);
  594. break;
  595. }
  596. return mlx4_cmd(dev, inbox->dma, in_mod, op_mod,
  597. MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
  598. MLX4_CMD_NATIVE);
  599. }
  600. /* For IB, we only consider:
  601. * - The capability mask, which is set to the aggregate of all
  602. * slave function capabilities
  603. * - The QKey violatin counter - reset according to each request.
  604. */
  605. if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
  606. reset_qkey_viols = (*(u8 *) inbox->buf) & 0x40;
  607. new_cap_mask = ((__be32 *) inbox->buf)[2];
  608. } else {
  609. reset_qkey_viols = ((u8 *) inbox->buf)[3] & 0x1;
  610. new_cap_mask = ((__be32 *) inbox->buf)[1];
  611. }
  612. agg_cap_mask = 0;
  613. slave_cap_mask =
  614. priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
  615. priv->mfunc.master.slave_state[slave].ib_cap_mask[port] = new_cap_mask;
  616. for (i = 0; i < dev->num_slaves; i++)
  617. agg_cap_mask |=
  618. priv->mfunc.master.slave_state[i].ib_cap_mask[port];
  619. /* only clear mailbox for guests. Master may be setting
  620. * MTU or PKEY table size
  621. */
  622. if (slave != dev->caps.function)
  623. memset(inbox->buf, 0, 256);
  624. if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
  625. *(u8 *) inbox->buf = !!reset_qkey_viols << 6;
  626. ((__be32 *) inbox->buf)[2] = agg_cap_mask;
  627. } else {
  628. ((u8 *) inbox->buf)[3] = !!reset_qkey_viols;
  629. ((__be32 *) inbox->buf)[1] = agg_cap_mask;
  630. }
  631. err = mlx4_cmd(dev, inbox->dma, port, is_eth, MLX4_CMD_SET_PORT,
  632. MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
  633. if (err)
  634. priv->mfunc.master.slave_state[slave].ib_cap_mask[port] =
  635. slave_cap_mask;
  636. return err;
  637. }
  638. int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
  639. struct mlx4_vhcr *vhcr,
  640. struct mlx4_cmd_mailbox *inbox,
  641. struct mlx4_cmd_mailbox *outbox,
  642. struct mlx4_cmd_info *cmd)
  643. {
  644. return mlx4_common_set_port(dev, slave, vhcr->in_modifier,
  645. vhcr->op_modifier, inbox);
  646. }
  647. int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port)
  648. {
  649. struct mlx4_cmd_mailbox *mailbox;
  650. int err;
  651. if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
  652. return 0;
  653. mailbox = mlx4_alloc_cmd_mailbox(dev);
  654. if (IS_ERR(mailbox))
  655. return PTR_ERR(mailbox);
  656. memset(mailbox->buf, 0, 256);
  657. ((__be32 *) mailbox->buf)[1] = dev->caps.ib_port_def_cap[port];
  658. err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_SET_PORT,
  659. MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
  660. mlx4_free_cmd_mailbox(dev, mailbox);
  661. return err;
  662. }
  663. int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
  664. u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx)
  665. {
  666. struct mlx4_cmd_mailbox *mailbox;
  667. struct mlx4_set_port_general_context *context;
  668. int err;
  669. u32 in_mod;
  670. mailbox = mlx4_alloc_cmd_mailbox(dev);
  671. if (IS_ERR(mailbox))
  672. return PTR_ERR(mailbox);
  673. context = mailbox->buf;
  674. memset(context, 0, sizeof *context);
  675. context->flags = SET_PORT_GEN_ALL_VALID;
  676. context->mtu = cpu_to_be16(mtu);
  677. context->pptx = (pptx * (!pfctx)) << 7;
  678. context->pfctx = pfctx;
  679. context->pprx = (pprx * (!pfcrx)) << 7;
  680. context->pfcrx = pfcrx;
  681. in_mod = MLX4_SET_PORT_GENERAL << 8 | port;
  682. err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
  683. MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
  684. mlx4_free_cmd_mailbox(dev, mailbox);
  685. return err;
  686. }
  687. EXPORT_SYMBOL(mlx4_SET_PORT_general);
  688. int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
  689. u8 promisc)
  690. {
  691. struct mlx4_cmd_mailbox *mailbox;
  692. struct mlx4_set_port_rqp_calc_context *context;
  693. int err;
  694. u32 in_mod;
  695. u32 m_promisc = (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) ?
  696. MCAST_DIRECT : MCAST_DEFAULT;
  697. if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER &&
  698. dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER)
  699. return 0;
  700. mailbox = mlx4_alloc_cmd_mailbox(dev);
  701. if (IS_ERR(mailbox))
  702. return PTR_ERR(mailbox);
  703. context = mailbox->buf;
  704. memset(context, 0, sizeof *context);
  705. context->base_qpn = cpu_to_be32(base_qpn);
  706. context->n_mac = dev->caps.log_num_macs;
  707. context->promisc = cpu_to_be32(promisc << SET_PORT_PROMISC_SHIFT |
  708. base_qpn);
  709. context->mcast = cpu_to_be32(m_promisc << SET_PORT_MC_PROMISC_SHIFT |
  710. base_qpn);
  711. context->intra_no_vlan = 0;
  712. context->no_vlan = MLX4_NO_VLAN_IDX;
  713. context->intra_vlan_miss = 0;
  714. context->vlan_miss = MLX4_VLAN_MISS_IDX;
  715. in_mod = MLX4_SET_PORT_RQP_CALC << 8 | port;
  716. err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
  717. MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
  718. mlx4_free_cmd_mailbox(dev, mailbox);
  719. return err;
  720. }
  721. EXPORT_SYMBOL(mlx4_SET_PORT_qpn_calc);
  722. int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
  723. struct mlx4_vhcr *vhcr,
  724. struct mlx4_cmd_mailbox *inbox,
  725. struct mlx4_cmd_mailbox *outbox,
  726. struct mlx4_cmd_info *cmd)
  727. {
  728. int err = 0;
  729. return err;
  730. }
  731. int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port,
  732. u64 mac, u64 clear, u8 mode)
  733. {
  734. return mlx4_cmd(dev, (mac | (clear << 63)), port, mode,
  735. MLX4_CMD_SET_MCAST_FLTR, MLX4_CMD_TIME_CLASS_B,
  736. MLX4_CMD_WRAPPED);
  737. }
  738. EXPORT_SYMBOL(mlx4_SET_MCAST_FLTR);
  739. int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
  740. struct mlx4_vhcr *vhcr,
  741. struct mlx4_cmd_mailbox *inbox,
  742. struct mlx4_cmd_mailbox *outbox,
  743. struct mlx4_cmd_info *cmd)
  744. {
  745. int err = 0;
  746. return err;
  747. }
  748. int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave,
  749. u32 in_mod, struct mlx4_cmd_mailbox *outbox)
  750. {
  751. return mlx4_cmd_box(dev, 0, outbox->dma, in_mod, 0,
  752. MLX4_CMD_DUMP_ETH_STATS, MLX4_CMD_TIME_CLASS_B,
  753. MLX4_CMD_NATIVE);
  754. }
  755. int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
  756. struct mlx4_vhcr *vhcr,
  757. struct mlx4_cmd_mailbox *inbox,
  758. struct mlx4_cmd_mailbox *outbox,
  759. struct mlx4_cmd_info *cmd)
  760. {
  761. return mlx4_common_dump_eth_stats(dev, slave,
  762. vhcr->in_modifier, outbox);
  763. }