bnx2x_cmn.h 38 KB

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  1. /* bnx2x_cmn.h: Broadcom Everest network driver.
  2. *
  3. * Copyright (c) 2007-2011 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10. * Written by: Eliezer Tamir
  11. * Based on code from Michael Chan's bnx2 driver
  12. * UDP CSUM errata workaround by Arik Gendelman
  13. * Slowpath and fastpath rework by Vladislav Zolotarov
  14. * Statistics and Link management by Yitchak Gertner
  15. *
  16. */
  17. #ifndef BNX2X_CMN_H
  18. #define BNX2X_CMN_H
  19. #include <linux/types.h>
  20. #include <linux/pci.h>
  21. #include <linux/netdevice.h>
  22. #include <linux/etherdevice.h>
  23. #include "bnx2x.h"
  24. /* This is used as a replacement for an MCP if it's not present */
  25. extern int load_count[2][3]; /* per-path: 0-common, 1-port0, 2-port1 */
  26. extern int num_queues;
  27. /************************ Macros ********************************/
  28. #define BNX2X_PCI_FREE(x, y, size) \
  29. do { \
  30. if (x) { \
  31. dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \
  32. x = NULL; \
  33. y = 0; \
  34. } \
  35. } while (0)
  36. #define BNX2X_FREE(x) \
  37. do { \
  38. if (x) { \
  39. kfree((void *)x); \
  40. x = NULL; \
  41. } \
  42. } while (0)
  43. #define BNX2X_PCI_ALLOC(x, y, size) \
  44. do { \
  45. x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
  46. if (x == NULL) \
  47. goto alloc_mem_err; \
  48. memset((void *)x, 0, size); \
  49. } while (0)
  50. #define BNX2X_ALLOC(x, size) \
  51. do { \
  52. x = kzalloc(size, GFP_KERNEL); \
  53. if (x == NULL) \
  54. goto alloc_mem_err; \
  55. } while (0)
  56. /*********************** Interfaces ****************************
  57. * Functions that need to be implemented by each driver version
  58. */
  59. /* Init */
  60. /**
  61. * bnx2x_send_unload_req - request unload mode from the MCP.
  62. *
  63. * @bp: driver handle
  64. * @unload_mode: requested function's unload mode
  65. *
  66. * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
  67. */
  68. u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode);
  69. /**
  70. * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
  71. *
  72. * @bp: driver handle
  73. */
  74. void bnx2x_send_unload_done(struct bnx2x *bp);
  75. /**
  76. * bnx2x_config_rss_pf - configure RSS parameters.
  77. *
  78. * @bp: driver handle
  79. * @ind_table: indirection table to configure
  80. * @config_hash: re-configure RSS hash keys configuration
  81. */
  82. int bnx2x_config_rss_pf(struct bnx2x *bp, u8 *ind_table, bool config_hash);
  83. /**
  84. * bnx2x__init_func_obj - init function object
  85. *
  86. * @bp: driver handle
  87. *
  88. * Initializes the Function Object with the appropriate
  89. * parameters which include a function slow path driver
  90. * interface.
  91. */
  92. void bnx2x__init_func_obj(struct bnx2x *bp);
  93. /**
  94. * bnx2x_setup_queue - setup eth queue.
  95. *
  96. * @bp: driver handle
  97. * @fp: pointer to the fastpath structure
  98. * @leading: boolean
  99. *
  100. */
  101. int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
  102. bool leading);
  103. /**
  104. * bnx2x_setup_leading - bring up a leading eth queue.
  105. *
  106. * @bp: driver handle
  107. */
  108. int bnx2x_setup_leading(struct bnx2x *bp);
  109. /**
  110. * bnx2x_fw_command - send the MCP a request
  111. *
  112. * @bp: driver handle
  113. * @command: request
  114. * @param: request's parameter
  115. *
  116. * block until there is a reply
  117. */
  118. u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param);
  119. /**
  120. * bnx2x_initial_phy_init - initialize link parameters structure variables.
  121. *
  122. * @bp: driver handle
  123. * @load_mode: current mode
  124. */
  125. u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode);
  126. /**
  127. * bnx2x_link_set - configure hw according to link parameters structure.
  128. *
  129. * @bp: driver handle
  130. */
  131. void bnx2x_link_set(struct bnx2x *bp);
  132. /**
  133. * bnx2x_link_test - query link status.
  134. *
  135. * @bp: driver handle
  136. * @is_serdes: bool
  137. *
  138. * Returns 0 if link is UP.
  139. */
  140. u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes);
  141. /**
  142. * bnx2x_drv_pulse - write driver pulse to shmem
  143. *
  144. * @bp: driver handle
  145. *
  146. * writes the value in bp->fw_drv_pulse_wr_seq to drv_pulse mbox
  147. * in the shmem.
  148. */
  149. void bnx2x_drv_pulse(struct bnx2x *bp);
  150. /**
  151. * bnx2x_igu_ack_sb - update IGU with current SB value
  152. *
  153. * @bp: driver handle
  154. * @igu_sb_id: SB id
  155. * @segment: SB segment
  156. * @index: SB index
  157. * @op: SB operation
  158. * @update: is HW update required
  159. */
  160. void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
  161. u16 index, u8 op, u8 update);
  162. /* Disable transactions from chip to host */
  163. void bnx2x_pf_disable(struct bnx2x *bp);
  164. /**
  165. * bnx2x__link_status_update - handles link status change.
  166. *
  167. * @bp: driver handle
  168. */
  169. void bnx2x__link_status_update(struct bnx2x *bp);
  170. /**
  171. * bnx2x_link_report - report link status to upper layer.
  172. *
  173. * @bp: driver handle
  174. */
  175. void bnx2x_link_report(struct bnx2x *bp);
  176. /* None-atomic version of bnx2x_link_report() */
  177. void __bnx2x_link_report(struct bnx2x *bp);
  178. /**
  179. * bnx2x_get_mf_speed - calculate MF speed.
  180. *
  181. * @bp: driver handle
  182. *
  183. * Takes into account current linespeed and MF configuration.
  184. */
  185. u16 bnx2x_get_mf_speed(struct bnx2x *bp);
  186. /**
  187. * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler
  188. *
  189. * @irq: irq number
  190. * @dev_instance: private instance
  191. */
  192. irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance);
  193. /**
  194. * bnx2x_interrupt - non MSI-X interrupt handler
  195. *
  196. * @irq: irq number
  197. * @dev_instance: private instance
  198. */
  199. irqreturn_t bnx2x_interrupt(int irq, void *dev_instance);
  200. #ifdef BCM_CNIC
  201. /**
  202. * bnx2x_cnic_notify - send command to cnic driver
  203. *
  204. * @bp: driver handle
  205. * @cmd: command
  206. */
  207. int bnx2x_cnic_notify(struct bnx2x *bp, int cmd);
  208. /**
  209. * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information
  210. *
  211. * @bp: driver handle
  212. */
  213. void bnx2x_setup_cnic_irq_info(struct bnx2x *bp);
  214. #endif
  215. /**
  216. * bnx2x_int_enable - enable HW interrupts.
  217. *
  218. * @bp: driver handle
  219. */
  220. void bnx2x_int_enable(struct bnx2x *bp);
  221. /**
  222. * bnx2x_int_disable_sync - disable interrupts.
  223. *
  224. * @bp: driver handle
  225. * @disable_hw: true, disable HW interrupts.
  226. *
  227. * This function ensures that there are no
  228. * ISRs or SP DPCs (sp_task) are running after it returns.
  229. */
  230. void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw);
  231. /**
  232. * bnx2x_nic_init - init driver internals.
  233. *
  234. * @bp: driver handle
  235. * @load_code: COMMON, PORT or FUNCTION
  236. *
  237. * Initializes:
  238. * - rings
  239. * - status blocks
  240. * - etc.
  241. */
  242. void bnx2x_nic_init(struct bnx2x *bp, u32 load_code);
  243. /**
  244. * bnx2x_alloc_mem - allocate driver's memory.
  245. *
  246. * @bp: driver handle
  247. */
  248. int bnx2x_alloc_mem(struct bnx2x *bp);
  249. /**
  250. * bnx2x_free_mem - release driver's memory.
  251. *
  252. * @bp: driver handle
  253. */
  254. void bnx2x_free_mem(struct bnx2x *bp);
  255. /**
  256. * bnx2x_set_num_queues - set number of queues according to mode.
  257. *
  258. * @bp: driver handle
  259. */
  260. void bnx2x_set_num_queues(struct bnx2x *bp);
  261. /**
  262. * bnx2x_chip_cleanup - cleanup chip internals.
  263. *
  264. * @bp: driver handle
  265. * @unload_mode: COMMON, PORT, FUNCTION
  266. *
  267. * - Cleanup MAC configuration.
  268. * - Closes clients.
  269. * - etc.
  270. */
  271. void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode);
  272. /**
  273. * bnx2x_acquire_hw_lock - acquire HW lock.
  274. *
  275. * @bp: driver handle
  276. * @resource: resource bit which was locked
  277. */
  278. int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource);
  279. /**
  280. * bnx2x_release_hw_lock - release HW lock.
  281. *
  282. * @bp: driver handle
  283. * @resource: resource bit which was locked
  284. */
  285. int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource);
  286. /**
  287. * bnx2x_release_leader_lock - release recovery leader lock
  288. *
  289. * @bp: driver handle
  290. */
  291. int bnx2x_release_leader_lock(struct bnx2x *bp);
  292. /**
  293. * bnx2x_set_eth_mac - configure eth MAC address in the HW
  294. *
  295. * @bp: driver handle
  296. * @set: set or clear
  297. *
  298. * Configures according to the value in netdev->dev_addr.
  299. */
  300. int bnx2x_set_eth_mac(struct bnx2x *bp, bool set);
  301. /**
  302. * bnx2x_set_rx_mode - set MAC filtering configurations.
  303. *
  304. * @dev: netdevice
  305. *
  306. * called with netif_tx_lock from dev_mcast.c
  307. * If bp->state is OPEN, should be called with
  308. * netif_addr_lock_bh()
  309. */
  310. void bnx2x_set_rx_mode(struct net_device *dev);
  311. /**
  312. * bnx2x_set_storm_rx_mode - configure MAC filtering rules in a FW.
  313. *
  314. * @bp: driver handle
  315. *
  316. * If bp->state is OPEN, should be called with
  317. * netif_addr_lock_bh().
  318. */
  319. void bnx2x_set_storm_rx_mode(struct bnx2x *bp);
  320. /**
  321. * bnx2x_set_q_rx_mode - configures rx_mode for a single queue.
  322. *
  323. * @bp: driver handle
  324. * @cl_id: client id
  325. * @rx_mode_flags: rx mode configuration
  326. * @rx_accept_flags: rx accept configuration
  327. * @tx_accept_flags: tx accept configuration (tx switch)
  328. * @ramrod_flags: ramrod configuration
  329. */
  330. void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
  331. unsigned long rx_mode_flags,
  332. unsigned long rx_accept_flags,
  333. unsigned long tx_accept_flags,
  334. unsigned long ramrod_flags);
  335. /* Parity errors related */
  336. void bnx2x_inc_load_cnt(struct bnx2x *bp);
  337. u32 bnx2x_dec_load_cnt(struct bnx2x *bp);
  338. bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print);
  339. bool bnx2x_reset_is_done(struct bnx2x *bp, int engine);
  340. void bnx2x_set_reset_in_progress(struct bnx2x *bp);
  341. void bnx2x_set_reset_global(struct bnx2x *bp);
  342. void bnx2x_disable_close_the_gate(struct bnx2x *bp);
  343. /**
  344. * bnx2x_sp_event - handle ramrods completion.
  345. *
  346. * @fp: fastpath handle for the event
  347. * @rr_cqe: eth_rx_cqe
  348. */
  349. void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe);
  350. /**
  351. * bnx2x_ilt_set_info - prepare ILT configurations.
  352. *
  353. * @bp: driver handle
  354. */
  355. void bnx2x_ilt_set_info(struct bnx2x *bp);
  356. /**
  357. * bnx2x_dcbx_init - initialize dcbx protocol.
  358. *
  359. * @bp: driver handle
  360. */
  361. void bnx2x_dcbx_init(struct bnx2x *bp);
  362. /**
  363. * bnx2x_set_power_state - set power state to the requested value.
  364. *
  365. * @bp: driver handle
  366. * @state: required state D0 or D3hot
  367. *
  368. * Currently only D0 and D3hot are supported.
  369. */
  370. int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state);
  371. /**
  372. * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW.
  373. *
  374. * @bp: driver handle
  375. * @value: new value
  376. */
  377. void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value);
  378. /* Error handling */
  379. void bnx2x_panic_dump(struct bnx2x *bp);
  380. void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl);
  381. /* dev_close main block */
  382. int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode);
  383. /* dev_open main block */
  384. int bnx2x_nic_load(struct bnx2x *bp, int load_mode);
  385. /* hard_xmit callback */
  386. netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev);
  387. /* setup_tc callback */
  388. int bnx2x_setup_tc(struct net_device *dev, u8 num_tc);
  389. /* select_queue callback */
  390. u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb);
  391. /* reload helper */
  392. int bnx2x_reload_if_running(struct net_device *dev);
  393. int bnx2x_change_mac_addr(struct net_device *dev, void *p);
  394. /* NAPI poll Rx part */
  395. int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget);
  396. void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
  397. u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod);
  398. /* NAPI poll Tx part */
  399. int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata);
  400. /* suspend/resume callbacks */
  401. int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state);
  402. int bnx2x_resume(struct pci_dev *pdev);
  403. /* Release IRQ vectors */
  404. void bnx2x_free_irq(struct bnx2x *bp);
  405. void bnx2x_free_fp_mem(struct bnx2x *bp);
  406. int bnx2x_alloc_fp_mem(struct bnx2x *bp);
  407. void bnx2x_init_rx_rings(struct bnx2x *bp);
  408. void bnx2x_free_skbs(struct bnx2x *bp);
  409. void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw);
  410. void bnx2x_netif_start(struct bnx2x *bp);
  411. /**
  412. * bnx2x_enable_msix - set msix configuration.
  413. *
  414. * @bp: driver handle
  415. *
  416. * fills msix_table, requests vectors, updates num_queues
  417. * according to number of available vectors.
  418. */
  419. int bnx2x_enable_msix(struct bnx2x *bp);
  420. /**
  421. * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly
  422. *
  423. * @bp: driver handle
  424. */
  425. int bnx2x_enable_msi(struct bnx2x *bp);
  426. /**
  427. * bnx2x_poll - NAPI callback
  428. *
  429. * @napi: napi structure
  430. * @budget:
  431. *
  432. */
  433. int bnx2x_poll(struct napi_struct *napi, int budget);
  434. /**
  435. * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure
  436. *
  437. * @bp: driver handle
  438. */
  439. int __devinit bnx2x_alloc_mem_bp(struct bnx2x *bp);
  440. /**
  441. * bnx2x_free_mem_bp - release memories outsize main driver structure
  442. *
  443. * @bp: driver handle
  444. */
  445. void bnx2x_free_mem_bp(struct bnx2x *bp);
  446. /**
  447. * bnx2x_change_mtu - change mtu netdev callback
  448. *
  449. * @dev: net device
  450. * @new_mtu: requested mtu
  451. *
  452. */
  453. int bnx2x_change_mtu(struct net_device *dev, int new_mtu);
  454. #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC)
  455. /**
  456. * bnx2x_fcoe_get_wwn - return the requested WWN value for this port
  457. *
  458. * @dev: net_device
  459. * @wwn: output buffer
  460. * @type: WWN type: NETDEV_FCOE_WWNN (node) or NETDEV_FCOE_WWPN (port)
  461. *
  462. */
  463. int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type);
  464. #endif
  465. netdev_features_t bnx2x_fix_features(struct net_device *dev,
  466. netdev_features_t features);
  467. int bnx2x_set_features(struct net_device *dev, netdev_features_t features);
  468. /**
  469. * bnx2x_tx_timeout - tx timeout netdev callback
  470. *
  471. * @dev: net device
  472. */
  473. void bnx2x_tx_timeout(struct net_device *dev);
  474. /*********************** Inlines **********************************/
  475. /*********************** Fast path ********************************/
  476. static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp)
  477. {
  478. barrier(); /* status block is written to by the chip */
  479. fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
  480. }
  481. static inline void bnx2x_update_rx_prod_gen(struct bnx2x *bp,
  482. struct bnx2x_fastpath *fp, u16 bd_prod,
  483. u16 rx_comp_prod, u16 rx_sge_prod, u32 start)
  484. {
  485. struct ustorm_eth_rx_producers rx_prods = {0};
  486. u32 i;
  487. /* Update producers */
  488. rx_prods.bd_prod = bd_prod;
  489. rx_prods.cqe_prod = rx_comp_prod;
  490. rx_prods.sge_prod = rx_sge_prod;
  491. /*
  492. * Make sure that the BD and SGE data is updated before updating the
  493. * producers since FW might read the BD/SGE right after the producer
  494. * is updated.
  495. * This is only applicable for weak-ordered memory model archs such
  496. * as IA-64. The following barrier is also mandatory since FW will
  497. * assumes BDs must have buffers.
  498. */
  499. wmb();
  500. for (i = 0; i < sizeof(rx_prods)/4; i++)
  501. REG_WR(bp, start + i*4, ((u32 *)&rx_prods)[i]);
  502. mmiowb(); /* keep prod updates ordered */
  503. DP(NETIF_MSG_RX_STATUS,
  504. "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n",
  505. fp->index, bd_prod, rx_comp_prod, rx_sge_prod);
  506. }
  507. static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id,
  508. u8 segment, u16 index, u8 op,
  509. u8 update, u32 igu_addr)
  510. {
  511. struct igu_regular cmd_data = {0};
  512. cmd_data.sb_id_and_flags =
  513. ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
  514. (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
  515. (update << IGU_REGULAR_BUPDATE_SHIFT) |
  516. (op << IGU_REGULAR_ENABLE_INT_SHIFT));
  517. DP(NETIF_MSG_HW, "write 0x%08x to IGU addr 0x%x\n",
  518. cmd_data.sb_id_and_flags, igu_addr);
  519. REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags);
  520. /* Make sure that ACK is written */
  521. mmiowb();
  522. barrier();
  523. }
  524. static inline void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func,
  525. u8 idu_sb_id, bool is_Pf)
  526. {
  527. u32 data, ctl, cnt = 100;
  528. u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
  529. u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
  530. u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
  531. u32 sb_bit = 1 << (idu_sb_id%32);
  532. u32 func_encode = func |
  533. ((is_Pf == true ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT);
  534. u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
  535. /* Not supported in BC mode */
  536. if (CHIP_INT_MODE_IS_BC(bp))
  537. return;
  538. data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
  539. << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
  540. IGU_REGULAR_CLEANUP_SET |
  541. IGU_REGULAR_BCLEANUP;
  542. ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
  543. func_encode << IGU_CTRL_REG_FID_SHIFT |
  544. IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
  545. DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
  546. data, igu_addr_data);
  547. REG_WR(bp, igu_addr_data, data);
  548. mmiowb();
  549. barrier();
  550. DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
  551. ctl, igu_addr_ctl);
  552. REG_WR(bp, igu_addr_ctl, ctl);
  553. mmiowb();
  554. barrier();
  555. /* wait for clean up to finish */
  556. while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
  557. msleep(20);
  558. if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
  559. DP(NETIF_MSG_HW, "Unable to finish IGU cleanup: "
  560. "idu_sb_id %d offset %d bit %d (cnt %d)\n",
  561. idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
  562. }
  563. }
  564. static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id,
  565. u8 storm, u16 index, u8 op, u8 update)
  566. {
  567. u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
  568. COMMAND_REG_INT_ACK);
  569. struct igu_ack_register igu_ack;
  570. igu_ack.status_block_index = index;
  571. igu_ack.sb_id_and_flags =
  572. ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  573. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  574. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  575. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  576. DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n",
  577. (*(u32 *)&igu_ack), hc_addr);
  578. REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
  579. /* Make sure that ACK is written */
  580. mmiowb();
  581. barrier();
  582. }
  583. static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm,
  584. u16 index, u8 op, u8 update)
  585. {
  586. if (bp->common.int_block == INT_BLOCK_HC)
  587. bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update);
  588. else {
  589. u8 segment;
  590. if (CHIP_INT_MODE_IS_BC(bp))
  591. segment = storm;
  592. else if (igu_sb_id != bp->igu_dsb_id)
  593. segment = IGU_SEG_ACCESS_DEF;
  594. else if (storm == ATTENTION_ID)
  595. segment = IGU_SEG_ACCESS_ATTN;
  596. else
  597. segment = IGU_SEG_ACCESS_DEF;
  598. bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update);
  599. }
  600. }
  601. static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp)
  602. {
  603. u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 +
  604. COMMAND_REG_SIMD_MASK);
  605. u32 result = REG_RD(bp, hc_addr);
  606. DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n",
  607. result, hc_addr);
  608. barrier();
  609. return result;
  610. }
  611. static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp)
  612. {
  613. u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8);
  614. u32 result = REG_RD(bp, igu_addr);
  615. DP(NETIF_MSG_HW, "read 0x%08x from IGU addr 0x%x\n",
  616. result, igu_addr);
  617. barrier();
  618. return result;
  619. }
  620. static inline u16 bnx2x_ack_int(struct bnx2x *bp)
  621. {
  622. barrier();
  623. if (bp->common.int_block == INT_BLOCK_HC)
  624. return bnx2x_hc_ack_int(bp);
  625. else
  626. return bnx2x_igu_ack_int(bp);
  627. }
  628. static inline int bnx2x_has_tx_work_unload(struct bnx2x_fp_txdata *txdata)
  629. {
  630. /* Tell compiler that consumer and producer can change */
  631. barrier();
  632. return txdata->tx_pkt_prod != txdata->tx_pkt_cons;
  633. }
  634. static inline u16 bnx2x_tx_avail(struct bnx2x *bp,
  635. struct bnx2x_fp_txdata *txdata)
  636. {
  637. s16 used;
  638. u16 prod;
  639. u16 cons;
  640. prod = txdata->tx_bd_prod;
  641. cons = txdata->tx_bd_cons;
  642. /* NUM_TX_RINGS = number of "next-page" entries
  643. It will be used as a threshold */
  644. used = SUB_S16(prod, cons) + (s16)NUM_TX_RINGS;
  645. #ifdef BNX2X_STOP_ON_ERROR
  646. WARN_ON(used < 0);
  647. WARN_ON(used > bp->tx_ring_size);
  648. WARN_ON((bp->tx_ring_size - used) > MAX_TX_AVAIL);
  649. #endif
  650. return (s16)(bp->tx_ring_size) - used;
  651. }
  652. static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata *txdata)
  653. {
  654. u16 hw_cons;
  655. /* Tell compiler that status block fields can change */
  656. barrier();
  657. hw_cons = le16_to_cpu(*txdata->tx_cons_sb);
  658. return hw_cons != txdata->tx_pkt_cons;
  659. }
  660. static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath *fp)
  661. {
  662. u8 cos;
  663. for_each_cos_in_tx_queue(fp, cos)
  664. if (bnx2x_tx_queue_has_work(&fp->txdata[cos]))
  665. return true;
  666. return false;
  667. }
  668. static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp)
  669. {
  670. u16 rx_cons_sb;
  671. /* Tell compiler that status block fields can change */
  672. barrier();
  673. rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb);
  674. if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
  675. rx_cons_sb++;
  676. return (fp->rx_comp_cons != rx_cons_sb);
  677. }
  678. /**
  679. * bnx2x_tx_disable - disables tx from stack point of view
  680. *
  681. * @bp: driver handle
  682. */
  683. static inline void bnx2x_tx_disable(struct bnx2x *bp)
  684. {
  685. netif_tx_disable(bp->dev);
  686. netif_carrier_off(bp->dev);
  687. }
  688. static inline void bnx2x_free_rx_sge(struct bnx2x *bp,
  689. struct bnx2x_fastpath *fp, u16 index)
  690. {
  691. struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
  692. struct page *page = sw_buf->page;
  693. struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
  694. /* Skip "next page" elements */
  695. if (!page)
  696. return;
  697. dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping),
  698. SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE);
  699. __free_pages(page, PAGES_PER_SGE_SHIFT);
  700. sw_buf->page = NULL;
  701. sge->addr_hi = 0;
  702. sge->addr_lo = 0;
  703. }
  704. static inline void bnx2x_add_all_napi(struct bnx2x *bp)
  705. {
  706. int i;
  707. /* Add NAPI objects */
  708. for_each_rx_queue(bp, i)
  709. netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
  710. bnx2x_poll, BNX2X_NAPI_WEIGHT);
  711. }
  712. static inline void bnx2x_del_all_napi(struct bnx2x *bp)
  713. {
  714. int i;
  715. for_each_rx_queue(bp, i)
  716. netif_napi_del(&bnx2x_fp(bp, i, napi));
  717. }
  718. static inline void bnx2x_disable_msi(struct bnx2x *bp)
  719. {
  720. if (bp->flags & USING_MSIX_FLAG) {
  721. pci_disable_msix(bp->pdev);
  722. bp->flags &= ~USING_MSIX_FLAG;
  723. } else if (bp->flags & USING_MSI_FLAG) {
  724. pci_disable_msi(bp->pdev);
  725. bp->flags &= ~USING_MSI_FLAG;
  726. }
  727. }
  728. static inline int bnx2x_calc_num_queues(struct bnx2x *bp)
  729. {
  730. return num_queues ?
  731. min_t(int, num_queues, BNX2X_MAX_QUEUES(bp)) :
  732. min_t(int, num_online_cpus(), BNX2X_MAX_QUEUES(bp));
  733. }
  734. static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp)
  735. {
  736. int i, j;
  737. for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
  738. int idx = RX_SGE_CNT * i - 1;
  739. for (j = 0; j < 2; j++) {
  740. BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx);
  741. idx--;
  742. }
  743. }
  744. }
  745. static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp)
  746. {
  747. /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */
  748. memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask));
  749. /* Clear the two last indices in the page to 1:
  750. these are the indices that correspond to the "next" element,
  751. hence will never be indicated and should be removed from
  752. the calculations. */
  753. bnx2x_clear_sge_mask_next_elems(fp);
  754. }
  755. static inline int bnx2x_alloc_rx_sge(struct bnx2x *bp,
  756. struct bnx2x_fastpath *fp, u16 index)
  757. {
  758. struct page *page = alloc_pages(GFP_ATOMIC, PAGES_PER_SGE_SHIFT);
  759. struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
  760. struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
  761. dma_addr_t mapping;
  762. if (unlikely(page == NULL))
  763. return -ENOMEM;
  764. mapping = dma_map_page(&bp->pdev->dev, page, 0,
  765. SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE);
  766. if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
  767. __free_pages(page, PAGES_PER_SGE_SHIFT);
  768. return -ENOMEM;
  769. }
  770. sw_buf->page = page;
  771. dma_unmap_addr_set(sw_buf, mapping, mapping);
  772. sge->addr_hi = cpu_to_le32(U64_HI(mapping));
  773. sge->addr_lo = cpu_to_le32(U64_LO(mapping));
  774. return 0;
  775. }
  776. static inline int bnx2x_alloc_rx_data(struct bnx2x *bp,
  777. struct bnx2x_fastpath *fp, u16 index)
  778. {
  779. u8 *data;
  780. struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
  781. struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
  782. dma_addr_t mapping;
  783. data = kmalloc(fp->rx_buf_size + NET_SKB_PAD, GFP_ATOMIC);
  784. if (unlikely(data == NULL))
  785. return -ENOMEM;
  786. mapping = dma_map_single(&bp->pdev->dev, data + NET_SKB_PAD,
  787. fp->rx_buf_size,
  788. DMA_FROM_DEVICE);
  789. if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
  790. kfree(data);
  791. return -ENOMEM;
  792. }
  793. rx_buf->data = data;
  794. dma_unmap_addr_set(rx_buf, mapping, mapping);
  795. rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
  796. rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
  797. return 0;
  798. }
  799. /* note that we are not allocating a new buffer,
  800. * we are just moving one from cons to prod
  801. * we are not creating a new mapping,
  802. * so there is no need to check for dma_mapping_error().
  803. */
  804. static inline void bnx2x_reuse_rx_data(struct bnx2x_fastpath *fp,
  805. u16 cons, u16 prod)
  806. {
  807. struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
  808. struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
  809. struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons];
  810. struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
  811. dma_unmap_addr_set(prod_rx_buf, mapping,
  812. dma_unmap_addr(cons_rx_buf, mapping));
  813. prod_rx_buf->data = cons_rx_buf->data;
  814. *prod_bd = *cons_bd;
  815. }
  816. /************************* Init ******************************************/
  817. /**
  818. * bnx2x_func_start - init function
  819. *
  820. * @bp: driver handle
  821. *
  822. * Must be called before sending CLIENT_SETUP for the first client.
  823. */
  824. static inline int bnx2x_func_start(struct bnx2x *bp)
  825. {
  826. struct bnx2x_func_state_params func_params = {0};
  827. struct bnx2x_func_start_params *start_params =
  828. &func_params.params.start;
  829. /* Prepare parameters for function state transitions */
  830. __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
  831. func_params.f_obj = &bp->func_obj;
  832. func_params.cmd = BNX2X_F_CMD_START;
  833. /* Function parameters */
  834. start_params->mf_mode = bp->mf_mode;
  835. start_params->sd_vlan_tag = bp->mf_ov;
  836. if (CHIP_IS_E1x(bp))
  837. start_params->network_cos_mode = OVERRIDE_COS;
  838. else
  839. start_params->network_cos_mode = STATIC_COS;
  840. return bnx2x_func_state_change(bp, &func_params);
  841. }
  842. /**
  843. * bnx2x_set_fw_mac_addr - fill in a MAC address in FW format
  844. *
  845. * @fw_hi: pointer to upper part
  846. * @fw_mid: pointer to middle part
  847. * @fw_lo: pointer to lower part
  848. * @mac: pointer to MAC address
  849. */
  850. static inline void bnx2x_set_fw_mac_addr(u16 *fw_hi, u16 *fw_mid, u16 *fw_lo,
  851. u8 *mac)
  852. {
  853. ((u8 *)fw_hi)[0] = mac[1];
  854. ((u8 *)fw_hi)[1] = mac[0];
  855. ((u8 *)fw_mid)[0] = mac[3];
  856. ((u8 *)fw_mid)[1] = mac[2];
  857. ((u8 *)fw_lo)[0] = mac[5];
  858. ((u8 *)fw_lo)[1] = mac[4];
  859. }
  860. static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp,
  861. struct bnx2x_fastpath *fp, int last)
  862. {
  863. int i;
  864. if (fp->disable_tpa)
  865. return;
  866. for (i = 0; i < last; i++)
  867. bnx2x_free_rx_sge(bp, fp, i);
  868. }
  869. static inline void bnx2x_free_tpa_pool(struct bnx2x *bp,
  870. struct bnx2x_fastpath *fp, int last)
  871. {
  872. int i;
  873. for (i = 0; i < last; i++) {
  874. struct bnx2x_agg_info *tpa_info = &fp->tpa_info[i];
  875. struct sw_rx_bd *first_buf = &tpa_info->first_buf;
  876. u8 *data = first_buf->data;
  877. if (data == NULL) {
  878. DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
  879. continue;
  880. }
  881. if (tpa_info->tpa_state == BNX2X_TPA_START)
  882. dma_unmap_single(&bp->pdev->dev,
  883. dma_unmap_addr(first_buf, mapping),
  884. fp->rx_buf_size, DMA_FROM_DEVICE);
  885. kfree(data);
  886. first_buf->data = NULL;
  887. }
  888. }
  889. static inline void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
  890. {
  891. int i;
  892. for (i = 1; i <= NUM_TX_RINGS; i++) {
  893. struct eth_tx_next_bd *tx_next_bd =
  894. &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
  895. tx_next_bd->addr_hi =
  896. cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
  897. BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
  898. tx_next_bd->addr_lo =
  899. cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
  900. BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
  901. }
  902. SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
  903. txdata->tx_db.data.zero_fill1 = 0;
  904. txdata->tx_db.data.prod = 0;
  905. txdata->tx_pkt_prod = 0;
  906. txdata->tx_pkt_cons = 0;
  907. txdata->tx_bd_prod = 0;
  908. txdata->tx_bd_cons = 0;
  909. txdata->tx_pkt = 0;
  910. }
  911. static inline void bnx2x_init_tx_rings(struct bnx2x *bp)
  912. {
  913. int i;
  914. u8 cos;
  915. for_each_tx_queue(bp, i)
  916. for_each_cos_in_tx_queue(&bp->fp[i], cos)
  917. bnx2x_init_tx_ring_one(&bp->fp[i].txdata[cos]);
  918. }
  919. static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp)
  920. {
  921. int i;
  922. for (i = 1; i <= NUM_RX_RINGS; i++) {
  923. struct eth_rx_bd *rx_bd;
  924. rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2];
  925. rx_bd->addr_hi =
  926. cpu_to_le32(U64_HI(fp->rx_desc_mapping +
  927. BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
  928. rx_bd->addr_lo =
  929. cpu_to_le32(U64_LO(fp->rx_desc_mapping +
  930. BCM_PAGE_SIZE*(i % NUM_RX_RINGS)));
  931. }
  932. }
  933. static inline void bnx2x_set_next_page_sgl(struct bnx2x_fastpath *fp)
  934. {
  935. int i;
  936. for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
  937. struct eth_rx_sge *sge;
  938. sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2];
  939. sge->addr_hi =
  940. cpu_to_le32(U64_HI(fp->rx_sge_mapping +
  941. BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
  942. sge->addr_lo =
  943. cpu_to_le32(U64_LO(fp->rx_sge_mapping +
  944. BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
  945. }
  946. }
  947. static inline void bnx2x_set_next_page_rx_cq(struct bnx2x_fastpath *fp)
  948. {
  949. int i;
  950. for (i = 1; i <= NUM_RCQ_RINGS; i++) {
  951. struct eth_rx_cqe_next_page *nextpg;
  952. nextpg = (struct eth_rx_cqe_next_page *)
  953. &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1];
  954. nextpg->addr_hi =
  955. cpu_to_le32(U64_HI(fp->rx_comp_mapping +
  956. BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
  957. nextpg->addr_lo =
  958. cpu_to_le32(U64_LO(fp->rx_comp_mapping +
  959. BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
  960. }
  961. }
  962. /* Returns the number of actually allocated BDs */
  963. static inline int bnx2x_alloc_rx_bds(struct bnx2x_fastpath *fp,
  964. int rx_ring_size)
  965. {
  966. struct bnx2x *bp = fp->bp;
  967. u16 ring_prod, cqe_ring_prod;
  968. int i;
  969. fp->rx_comp_cons = 0;
  970. cqe_ring_prod = ring_prod = 0;
  971. /* This routine is called only during fo init so
  972. * fp->eth_q_stats.rx_skb_alloc_failed = 0
  973. */
  974. for (i = 0; i < rx_ring_size; i++) {
  975. if (bnx2x_alloc_rx_data(bp, fp, ring_prod) < 0) {
  976. fp->eth_q_stats.rx_skb_alloc_failed++;
  977. continue;
  978. }
  979. ring_prod = NEXT_RX_IDX(ring_prod);
  980. cqe_ring_prod = NEXT_RCQ_IDX(cqe_ring_prod);
  981. WARN_ON(ring_prod <= (i - fp->eth_q_stats.rx_skb_alloc_failed));
  982. }
  983. if (fp->eth_q_stats.rx_skb_alloc_failed)
  984. BNX2X_ERR("was only able to allocate "
  985. "%d rx skbs on queue[%d]\n",
  986. (i - fp->eth_q_stats.rx_skb_alloc_failed), fp->index);
  987. fp->rx_bd_prod = ring_prod;
  988. /* Limit the CQE producer by the CQE ring size */
  989. fp->rx_comp_prod = min_t(u16, NUM_RCQ_RINGS*RCQ_DESC_CNT,
  990. cqe_ring_prod);
  991. fp->rx_pkt = fp->rx_calls = 0;
  992. return i - fp->eth_q_stats.rx_skb_alloc_failed;
  993. }
  994. /* Statistics ID are global per chip/path, while Client IDs for E1x are per
  995. * port.
  996. */
  997. static inline u8 bnx2x_stats_id(struct bnx2x_fastpath *fp)
  998. {
  999. if (!CHIP_IS_E1x(fp->bp))
  1000. return fp->cl_id;
  1001. else
  1002. return fp->cl_id + BP_PORT(fp->bp) * FP_SB_MAX_E1x;
  1003. }
  1004. static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath *fp,
  1005. bnx2x_obj_type obj_type)
  1006. {
  1007. struct bnx2x *bp = fp->bp;
  1008. /* Configure classification DBs */
  1009. bnx2x_init_mac_obj(bp, &fp->mac_obj, fp->cl_id, fp->cid,
  1010. BP_FUNC(bp), bnx2x_sp(bp, mac_rdata),
  1011. bnx2x_sp_mapping(bp, mac_rdata),
  1012. BNX2X_FILTER_MAC_PENDING,
  1013. &bp->sp_state, obj_type,
  1014. &bp->macs_pool);
  1015. }
  1016. /**
  1017. * bnx2x_get_path_func_num - get number of active functions
  1018. *
  1019. * @bp: driver handle
  1020. *
  1021. * Calculates the number of active (not hidden) functions on the
  1022. * current path.
  1023. */
  1024. static inline u8 bnx2x_get_path_func_num(struct bnx2x *bp)
  1025. {
  1026. u8 func_num = 0, i;
  1027. /* 57710 has only one function per-port */
  1028. if (CHIP_IS_E1(bp))
  1029. return 1;
  1030. /* Calculate a number of functions enabled on the current
  1031. * PATH/PORT.
  1032. */
  1033. if (CHIP_REV_IS_SLOW(bp)) {
  1034. if (IS_MF(bp))
  1035. func_num = 4;
  1036. else
  1037. func_num = 2;
  1038. } else {
  1039. for (i = 0; i < E1H_FUNC_MAX / 2; i++) {
  1040. u32 func_config =
  1041. MF_CFG_RD(bp,
  1042. func_mf_config[BP_PORT(bp) + 2 * i].
  1043. config);
  1044. func_num +=
  1045. ((func_config & FUNC_MF_CFG_FUNC_HIDE) ? 0 : 1);
  1046. }
  1047. }
  1048. WARN_ON(!func_num);
  1049. return func_num;
  1050. }
  1051. static inline void bnx2x_init_bp_objs(struct bnx2x *bp)
  1052. {
  1053. /* RX_MODE controlling object */
  1054. bnx2x_init_rx_mode_obj(bp, &bp->rx_mode_obj);
  1055. /* multicast configuration controlling object */
  1056. bnx2x_init_mcast_obj(bp, &bp->mcast_obj, bp->fp->cl_id, bp->fp->cid,
  1057. BP_FUNC(bp), BP_FUNC(bp),
  1058. bnx2x_sp(bp, mcast_rdata),
  1059. bnx2x_sp_mapping(bp, mcast_rdata),
  1060. BNX2X_FILTER_MCAST_PENDING, &bp->sp_state,
  1061. BNX2X_OBJ_TYPE_RX);
  1062. /* Setup CAM credit pools */
  1063. bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp),
  1064. bnx2x_get_path_func_num(bp));
  1065. /* RSS configuration object */
  1066. bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id,
  1067. bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp),
  1068. bnx2x_sp(bp, rss_rdata),
  1069. bnx2x_sp_mapping(bp, rss_rdata),
  1070. BNX2X_FILTER_RSS_CONF_PENDING, &bp->sp_state,
  1071. BNX2X_OBJ_TYPE_RX);
  1072. }
  1073. static inline u8 bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp)
  1074. {
  1075. if (CHIP_IS_E1x(fp->bp))
  1076. return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H;
  1077. else
  1078. return fp->cl_id;
  1079. }
  1080. static inline u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
  1081. {
  1082. struct bnx2x *bp = fp->bp;
  1083. if (!CHIP_IS_E1x(bp))
  1084. return USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
  1085. else
  1086. return USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
  1087. }
  1088. static inline void bnx2x_init_txdata(struct bnx2x *bp,
  1089. struct bnx2x_fp_txdata *txdata, u32 cid, int txq_index,
  1090. __le16 *tx_cons_sb)
  1091. {
  1092. txdata->cid = cid;
  1093. txdata->txq_index = txq_index;
  1094. txdata->tx_cons_sb = tx_cons_sb;
  1095. DP(BNX2X_MSG_SP, "created tx data cid %d, txq %d\n",
  1096. txdata->cid, txdata->txq_index);
  1097. }
  1098. #ifdef BCM_CNIC
  1099. static inline u8 bnx2x_cnic_eth_cl_id(struct bnx2x *bp, u8 cl_idx)
  1100. {
  1101. return bp->cnic_base_cl_id + cl_idx +
  1102. (bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX;
  1103. }
  1104. static inline u8 bnx2x_cnic_fw_sb_id(struct bnx2x *bp)
  1105. {
  1106. /* the 'first' id is allocated for the cnic */
  1107. return bp->base_fw_ndsb;
  1108. }
  1109. static inline u8 bnx2x_cnic_igu_sb_id(struct bnx2x *bp)
  1110. {
  1111. return bp->igu_base_sb;
  1112. }
  1113. static inline void bnx2x_init_fcoe_fp(struct bnx2x *bp)
  1114. {
  1115. struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
  1116. unsigned long q_type = 0;
  1117. bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
  1118. bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
  1119. BNX2X_FCOE_ETH_CL_ID_IDX);
  1120. /** Current BNX2X_FCOE_ETH_CID deffinition implies not more than
  1121. * 16 ETH clients per function when CNIC is enabled!
  1122. *
  1123. * Fix it ASAP!!!
  1124. */
  1125. bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID;
  1126. bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
  1127. bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
  1128. bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
  1129. bnx2x_init_txdata(bp, &bnx2x_fcoe(bp, txdata[0]),
  1130. fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX);
  1131. DP(BNX2X_MSG_SP, "created fcoe tx data (fp index %d)\n", fp->index);
  1132. /* qZone id equals to FW (per path) client id */
  1133. bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
  1134. /* init shortcut */
  1135. bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
  1136. bnx2x_rx_ustorm_prods_offset(fp);
  1137. /* Configure Queue State object */
  1138. __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
  1139. __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
  1140. /* No multi-CoS for FCoE L2 client */
  1141. BUG_ON(fp->max_cos != 1);
  1142. bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, &fp->cid, 1,
  1143. BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
  1144. bnx2x_sp_mapping(bp, q_rdata), q_type);
  1145. DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d "
  1146. "igu_sb %d\n",
  1147. fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
  1148. fp->igu_sb_id);
  1149. }
  1150. #endif
  1151. static inline int bnx2x_clean_tx_queue(struct bnx2x *bp,
  1152. struct bnx2x_fp_txdata *txdata)
  1153. {
  1154. int cnt = 1000;
  1155. while (bnx2x_has_tx_work_unload(txdata)) {
  1156. if (!cnt) {
  1157. BNX2X_ERR("timeout waiting for queue[%d]: "
  1158. "txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n",
  1159. txdata->txq_index, txdata->tx_pkt_prod,
  1160. txdata->tx_pkt_cons);
  1161. #ifdef BNX2X_STOP_ON_ERROR
  1162. bnx2x_panic();
  1163. return -EBUSY;
  1164. #else
  1165. break;
  1166. #endif
  1167. }
  1168. cnt--;
  1169. usleep_range(1000, 1000);
  1170. }
  1171. return 0;
  1172. }
  1173. int bnx2x_get_link_cfg_idx(struct bnx2x *bp);
  1174. static inline void __storm_memset_struct(struct bnx2x *bp,
  1175. u32 addr, size_t size, u32 *data)
  1176. {
  1177. int i;
  1178. for (i = 0; i < size/4; i++)
  1179. REG_WR(bp, addr + (i * 4), data[i]);
  1180. }
  1181. static inline void storm_memset_func_cfg(struct bnx2x *bp,
  1182. struct tstorm_eth_function_common_config *tcfg,
  1183. u16 abs_fid)
  1184. {
  1185. size_t size = sizeof(struct tstorm_eth_function_common_config);
  1186. u32 addr = BAR_TSTRORM_INTMEM +
  1187. TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
  1188. __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
  1189. }
  1190. static inline void storm_memset_cmng(struct bnx2x *bp,
  1191. struct cmng_struct_per_port *cmng,
  1192. u8 port)
  1193. {
  1194. size_t size = sizeof(struct cmng_struct_per_port);
  1195. u32 addr = BAR_XSTRORM_INTMEM +
  1196. XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
  1197. __storm_memset_struct(bp, addr, size, (u32 *)cmng);
  1198. }
  1199. /**
  1200. * bnx2x_wait_sp_comp - wait for the outstanding SP commands.
  1201. *
  1202. * @bp: driver handle
  1203. * @mask: bits that need to be cleared
  1204. */
  1205. static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask)
  1206. {
  1207. int tout = 5000; /* Wait for 5 secs tops */
  1208. while (tout--) {
  1209. smp_mb();
  1210. netif_addr_lock_bh(bp->dev);
  1211. if (!(bp->sp_state & mask)) {
  1212. netif_addr_unlock_bh(bp->dev);
  1213. return true;
  1214. }
  1215. netif_addr_unlock_bh(bp->dev);
  1216. usleep_range(1000, 1000);
  1217. }
  1218. smp_mb();
  1219. netif_addr_lock_bh(bp->dev);
  1220. if (bp->sp_state & mask) {
  1221. BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, "
  1222. "mask 0x%lx\n", bp->sp_state, mask);
  1223. netif_addr_unlock_bh(bp->dev);
  1224. return false;
  1225. }
  1226. netif_addr_unlock_bh(bp->dev);
  1227. return true;
  1228. }
  1229. /**
  1230. * bnx2x_set_ctx_validation - set CDU context validation values
  1231. *
  1232. * @bp: driver handle
  1233. * @cxt: context of the connection on the host memory
  1234. * @cid: SW CID of the connection to be configured
  1235. */
  1236. void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt,
  1237. u32 cid);
  1238. void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id,
  1239. u8 sb_index, u8 disable, u16 usec);
  1240. void bnx2x_acquire_phy_lock(struct bnx2x *bp);
  1241. void bnx2x_release_phy_lock(struct bnx2x *bp);
  1242. /**
  1243. * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration.
  1244. *
  1245. * @bp: driver handle
  1246. * @mf_cfg: MF configuration
  1247. *
  1248. */
  1249. static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg)
  1250. {
  1251. u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
  1252. FUNC_MF_CFG_MAX_BW_SHIFT;
  1253. if (!max_cfg) {
  1254. DP(NETIF_MSG_LINK,
  1255. "Max BW configured to 0 - using 100 instead\n");
  1256. max_cfg = 100;
  1257. }
  1258. return max_cfg;
  1259. }
  1260. /**
  1261. * bnx2x_get_iscsi_info - update iSCSI params according to licensing info.
  1262. *
  1263. * @bp: driver handle
  1264. *
  1265. */
  1266. void bnx2x_get_iscsi_info(struct bnx2x *bp);
  1267. /* returns func by VN for current port */
  1268. static inline int func_by_vn(struct bnx2x *bp, int vn)
  1269. {
  1270. return 2 * vn + BP_PORT(bp);
  1271. }
  1272. /**
  1273. * bnx2x_link_sync_notify - send notification to other functions.
  1274. *
  1275. * @bp: driver handle
  1276. *
  1277. */
  1278. static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
  1279. {
  1280. int func;
  1281. int vn;
  1282. /* Set the attention towards other drivers on the same port */
  1283. for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
  1284. if (vn == BP_VN(bp))
  1285. continue;
  1286. func = func_by_vn(bp, vn);
  1287. REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
  1288. (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
  1289. }
  1290. }
  1291. /**
  1292. * bnx2x_update_drv_flags - update flags in shmem
  1293. *
  1294. * @bp: driver handle
  1295. * @flags: flags to update
  1296. * @set: set or clear
  1297. *
  1298. */
  1299. static inline void bnx2x_update_drv_flags(struct bnx2x *bp, u32 flags, u32 set)
  1300. {
  1301. if (SHMEM2_HAS(bp, drv_flags)) {
  1302. u32 drv_flags;
  1303. bnx2x_acquire_hw_lock(bp, HW_LOCK_DRV_FLAGS);
  1304. drv_flags = SHMEM2_RD(bp, drv_flags);
  1305. if (set)
  1306. SET_FLAGS(drv_flags, flags);
  1307. else
  1308. RESET_FLAGS(drv_flags, flags);
  1309. SHMEM2_WR(bp, drv_flags, drv_flags);
  1310. DP(NETIF_MSG_HW, "drv_flags 0x%08x\n", drv_flags);
  1311. bnx2x_release_hw_lock(bp, HW_LOCK_DRV_FLAGS);
  1312. }
  1313. }
  1314. static inline bool bnx2x_is_valid_ether_addr(struct bnx2x *bp, u8 *addr)
  1315. {
  1316. if (is_valid_ether_addr(addr))
  1317. return true;
  1318. #ifdef BCM_CNIC
  1319. if (is_zero_ether_addr(addr) && IS_MF_ISCSI_SD(bp))
  1320. return true;
  1321. #endif
  1322. return false;
  1323. }
  1324. #endif /* BNX2X_CMN_H */