i8042.c 28 KB

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  1. /*
  2. * i8042 keyboard and mouse controller driver for Linux
  3. *
  4. * Copyright (c) 1999-2004 Vojtech Pavlik
  5. */
  6. /*
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. */
  11. #include <linux/delay.h>
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/ioport.h>
  16. #include <linux/init.h>
  17. #include <linux/serio.h>
  18. #include <linux/err.h>
  19. #include <linux/rcupdate.h>
  20. #include <linux/platform_device.h>
  21. #include <asm/io.h>
  22. MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>");
  23. MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver");
  24. MODULE_LICENSE("GPL");
  25. static unsigned int i8042_nokbd;
  26. module_param_named(nokbd, i8042_nokbd, bool, 0);
  27. MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port.");
  28. static unsigned int i8042_noaux;
  29. module_param_named(noaux, i8042_noaux, bool, 0);
  30. MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port.");
  31. static unsigned int i8042_nomux;
  32. module_param_named(nomux, i8042_nomux, bool, 0);
  33. MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing conrtoller is present.");
  34. static unsigned int i8042_unlock;
  35. module_param_named(unlock, i8042_unlock, bool, 0);
  36. MODULE_PARM_DESC(unlock, "Ignore keyboard lock.");
  37. static unsigned int i8042_reset;
  38. module_param_named(reset, i8042_reset, bool, 0);
  39. MODULE_PARM_DESC(reset, "Reset controller during init and cleanup.");
  40. static unsigned int i8042_direct;
  41. module_param_named(direct, i8042_direct, bool, 0);
  42. MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode.");
  43. static unsigned int i8042_dumbkbd;
  44. module_param_named(dumbkbd, i8042_dumbkbd, bool, 0);
  45. MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard");
  46. static unsigned int i8042_noloop;
  47. module_param_named(noloop, i8042_noloop, bool, 0);
  48. MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port");
  49. static unsigned int i8042_blink_frequency = 500;
  50. module_param_named(panicblink, i8042_blink_frequency, uint, 0600);
  51. MODULE_PARM_DESC(panicblink, "Frequency with which keyboard LEDs should blink when kernel panics");
  52. #ifdef CONFIG_PNP
  53. static int i8042_nopnp;
  54. module_param_named(nopnp, i8042_nopnp, bool, 0);
  55. MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings");
  56. #endif
  57. #define DEBUG
  58. #ifdef DEBUG
  59. static int i8042_debug;
  60. module_param_named(debug, i8042_debug, bool, 0600);
  61. MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off");
  62. #endif
  63. #include "i8042.h"
  64. static DEFINE_SPINLOCK(i8042_lock);
  65. struct i8042_port {
  66. struct serio *serio;
  67. int irq;
  68. unsigned char exists;
  69. signed char mux;
  70. };
  71. #define I8042_KBD_PORT_NO 0
  72. #define I8042_AUX_PORT_NO 1
  73. #define I8042_MUX_PORT_NO 2
  74. #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2)
  75. static struct i8042_port i8042_ports[I8042_NUM_PORTS];
  76. static unsigned char i8042_initial_ctr;
  77. static unsigned char i8042_ctr;
  78. static unsigned char i8042_mux_present;
  79. static unsigned char i8042_kbd_irq_registered;
  80. static unsigned char i8042_aux_irq_registered;
  81. static unsigned char i8042_suppress_kbd_ack;
  82. static struct platform_device *i8042_platform_device;
  83. static irqreturn_t i8042_interrupt(int irq, void *dev_id);
  84. /*
  85. * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to
  86. * be ready for reading values from it / writing values to it.
  87. * Called always with i8042_lock held.
  88. */
  89. static int i8042_wait_read(void)
  90. {
  91. int i = 0;
  92. while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) {
  93. udelay(50);
  94. i++;
  95. }
  96. return -(i == I8042_CTL_TIMEOUT);
  97. }
  98. static int i8042_wait_write(void)
  99. {
  100. int i = 0;
  101. while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) {
  102. udelay(50);
  103. i++;
  104. }
  105. return -(i == I8042_CTL_TIMEOUT);
  106. }
  107. /*
  108. * i8042_flush() flushes all data that may be in the keyboard and mouse buffers
  109. * of the i8042 down the toilet.
  110. */
  111. static int i8042_flush(void)
  112. {
  113. unsigned long flags;
  114. unsigned char data, str;
  115. int i = 0;
  116. spin_lock_irqsave(&i8042_lock, flags);
  117. while (((str = i8042_read_status()) & I8042_STR_OBF) && (i < I8042_BUFFER_SIZE)) {
  118. udelay(50);
  119. data = i8042_read_data();
  120. i++;
  121. dbg("%02x <- i8042 (flush, %s)", data,
  122. str & I8042_STR_AUXDATA ? "aux" : "kbd");
  123. }
  124. spin_unlock_irqrestore(&i8042_lock, flags);
  125. return i;
  126. }
  127. /*
  128. * i8042_command() executes a command on the i8042. It also sends the input
  129. * parameter(s) of the commands to it, and receives the output value(s). The
  130. * parameters are to be stored in the param array, and the output is placed
  131. * into the same array. The number of the parameters and output values is
  132. * encoded in bits 8-11 of the command number.
  133. */
  134. static int __i8042_command(unsigned char *param, int command)
  135. {
  136. int i, error;
  137. if (i8042_noloop && command == I8042_CMD_AUX_LOOP)
  138. return -1;
  139. error = i8042_wait_write();
  140. if (error)
  141. return error;
  142. dbg("%02x -> i8042 (command)", command & 0xff);
  143. i8042_write_command(command & 0xff);
  144. for (i = 0; i < ((command >> 12) & 0xf); i++) {
  145. error = i8042_wait_write();
  146. if (error)
  147. return error;
  148. dbg("%02x -> i8042 (parameter)", param[i]);
  149. i8042_write_data(param[i]);
  150. }
  151. for (i = 0; i < ((command >> 8) & 0xf); i++) {
  152. error = i8042_wait_read();
  153. if (error) {
  154. dbg(" -- i8042 (timeout)");
  155. return error;
  156. }
  157. if (command == I8042_CMD_AUX_LOOP &&
  158. !(i8042_read_status() & I8042_STR_AUXDATA)) {
  159. dbg(" -- i8042 (auxerr)");
  160. return -1;
  161. }
  162. param[i] = i8042_read_data();
  163. dbg("%02x <- i8042 (return)", param[i]);
  164. }
  165. return 0;
  166. }
  167. static int i8042_command(unsigned char *param, int command)
  168. {
  169. unsigned long flags;
  170. int retval;
  171. spin_lock_irqsave(&i8042_lock, flags);
  172. retval = __i8042_command(param, command);
  173. spin_unlock_irqrestore(&i8042_lock, flags);
  174. return retval;
  175. }
  176. /*
  177. * i8042_kbd_write() sends a byte out through the keyboard interface.
  178. */
  179. static int i8042_kbd_write(struct serio *port, unsigned char c)
  180. {
  181. unsigned long flags;
  182. int retval = 0;
  183. spin_lock_irqsave(&i8042_lock, flags);
  184. if (!(retval = i8042_wait_write())) {
  185. dbg("%02x -> i8042 (kbd-data)", c);
  186. i8042_write_data(c);
  187. }
  188. spin_unlock_irqrestore(&i8042_lock, flags);
  189. return retval;
  190. }
  191. /*
  192. * i8042_aux_write() sends a byte out through the aux interface.
  193. */
  194. static int i8042_aux_write(struct serio *serio, unsigned char c)
  195. {
  196. struct i8042_port *port = serio->port_data;
  197. return i8042_command(&c, port->mux == -1 ?
  198. I8042_CMD_AUX_SEND :
  199. I8042_CMD_MUX_SEND + port->mux);
  200. }
  201. /*
  202. * i8042_start() is called by serio core when port is about to finish
  203. * registering. It will mark port as existing so i8042_interrupt can
  204. * start sending data through it.
  205. */
  206. static int i8042_start(struct serio *serio)
  207. {
  208. struct i8042_port *port = serio->port_data;
  209. port->exists = 1;
  210. mb();
  211. return 0;
  212. }
  213. /*
  214. * i8042_stop() marks serio port as non-existing so i8042_interrupt
  215. * will not try to send data to the port that is about to go away.
  216. * The function is called by serio core as part of unregister procedure.
  217. */
  218. static void i8042_stop(struct serio *serio)
  219. {
  220. struct i8042_port *port = serio->port_data;
  221. port->exists = 0;
  222. synchronize_sched();
  223. port->serio = NULL;
  224. }
  225. /*
  226. * i8042_interrupt() is the most important function in this driver -
  227. * it handles the interrupts from the i8042, and sends incoming bytes
  228. * to the upper layers.
  229. */
  230. static irqreturn_t i8042_interrupt(int irq, void *dev_id)
  231. {
  232. struct i8042_port *port;
  233. unsigned long flags;
  234. unsigned char str, data;
  235. unsigned int dfl;
  236. unsigned int port_no;
  237. int ret = 1;
  238. spin_lock_irqsave(&i8042_lock, flags);
  239. str = i8042_read_status();
  240. if (unlikely(~str & I8042_STR_OBF)) {
  241. spin_unlock_irqrestore(&i8042_lock, flags);
  242. if (irq) dbg("Interrupt %d, without any data", irq);
  243. ret = 0;
  244. goto out;
  245. }
  246. data = i8042_read_data();
  247. spin_unlock_irqrestore(&i8042_lock, flags);
  248. if (i8042_mux_present && (str & I8042_STR_AUXDATA)) {
  249. static unsigned long last_transmit;
  250. static unsigned char last_str;
  251. dfl = 0;
  252. if (str & I8042_STR_MUXERR) {
  253. dbg("MUX error, status is %02x, data is %02x", str, data);
  254. /*
  255. * When MUXERR condition is signalled the data register can only contain
  256. * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately
  257. * it is not always the case. Some KBCs also report 0xfc when there is
  258. * nothing connected to the port while others sometimes get confused which
  259. * port the data came from and signal error leaving the data intact. They
  260. * _do not_ revert to legacy mode (actually I've never seen KBC reverting
  261. * to legacy mode yet, when we see one we'll add proper handling).
  262. * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the
  263. * rest assume that the data came from the same serio last byte
  264. * was transmitted (if transmission happened not too long ago).
  265. */
  266. switch (data) {
  267. default:
  268. if (time_before(jiffies, last_transmit + HZ/10)) {
  269. str = last_str;
  270. break;
  271. }
  272. /* fall through - report timeout */
  273. case 0xfc:
  274. case 0xfd:
  275. case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break;
  276. case 0xff: dfl = SERIO_PARITY; data = 0xfe; break;
  277. }
  278. }
  279. port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3);
  280. last_str = str;
  281. last_transmit = jiffies;
  282. } else {
  283. dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) |
  284. ((str & I8042_STR_TIMEOUT) ? SERIO_TIMEOUT : 0);
  285. port_no = (str & I8042_STR_AUXDATA) ?
  286. I8042_AUX_PORT_NO : I8042_KBD_PORT_NO;
  287. }
  288. port = &i8042_ports[port_no];
  289. dbg("%02x <- i8042 (interrupt, %d, %d%s%s)",
  290. data, port_no, irq,
  291. dfl & SERIO_PARITY ? ", bad parity" : "",
  292. dfl & SERIO_TIMEOUT ? ", timeout" : "");
  293. if (unlikely(i8042_suppress_kbd_ack))
  294. if (port_no == I8042_KBD_PORT_NO &&
  295. (data == 0xfa || data == 0xfe)) {
  296. i8042_suppress_kbd_ack--;
  297. goto out;
  298. }
  299. if (likely(port->exists))
  300. serio_interrupt(port->serio, data, dfl);
  301. out:
  302. return IRQ_RETVAL(ret);
  303. }
  304. /*
  305. * i8042_enable_kbd_port enables keybaord port on chip
  306. */
  307. static int i8042_enable_kbd_port(void)
  308. {
  309. i8042_ctr &= ~I8042_CTR_KBDDIS;
  310. i8042_ctr |= I8042_CTR_KBDINT;
  311. if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
  312. i8042_ctr &= ~I8042_CTR_KBDINT;
  313. i8042_ctr |= I8042_CTR_KBDDIS;
  314. printk(KERN_ERR "i8042.c: Failed to enable KBD port.\n");
  315. return -EIO;
  316. }
  317. return 0;
  318. }
  319. /*
  320. * i8042_enable_aux_port enables AUX (mouse) port on chip
  321. */
  322. static int i8042_enable_aux_port(void)
  323. {
  324. i8042_ctr &= ~I8042_CTR_AUXDIS;
  325. i8042_ctr |= I8042_CTR_AUXINT;
  326. if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
  327. i8042_ctr &= ~I8042_CTR_AUXINT;
  328. i8042_ctr |= I8042_CTR_AUXDIS;
  329. printk(KERN_ERR "i8042.c: Failed to enable AUX port.\n");
  330. return -EIO;
  331. }
  332. return 0;
  333. }
  334. /*
  335. * i8042_enable_mux_ports enables 4 individual AUX ports after
  336. * the controller has been switched into Multiplexed mode
  337. */
  338. static int i8042_enable_mux_ports(void)
  339. {
  340. unsigned char param;
  341. int i;
  342. for (i = 0; i < I8042_NUM_MUX_PORTS; i++) {
  343. i8042_command(&param, I8042_CMD_MUX_PFX + i);
  344. i8042_command(&param, I8042_CMD_AUX_ENABLE);
  345. }
  346. return i8042_enable_aux_port();
  347. }
  348. /*
  349. * i8042_set_mux_mode checks whether the controller has an active
  350. * multiplexor and puts the chip into Multiplexed (1) or Legacy (0) mode.
  351. */
  352. static int i8042_set_mux_mode(unsigned int mode, unsigned char *mux_version)
  353. {
  354. unsigned char param;
  355. /*
  356. * Get rid of bytes in the queue.
  357. */
  358. i8042_flush();
  359. /*
  360. * Internal loopback test - send three bytes, they should come back from the
  361. * mouse interface, the last should be version.
  362. */
  363. param = 0xf0;
  364. if (i8042_command(&param, I8042_CMD_AUX_LOOP) || param != 0xf0)
  365. return -1;
  366. param = mode ? 0x56 : 0xf6;
  367. if (i8042_command(&param, I8042_CMD_AUX_LOOP) || param != (mode ? 0x56 : 0xf6))
  368. return -1;
  369. param = mode ? 0xa4 : 0xa5;
  370. if (i8042_command(&param, I8042_CMD_AUX_LOOP) || param == (mode ? 0xa4 : 0xa5))
  371. return -1;
  372. if (mux_version)
  373. *mux_version = param;
  374. return 0;
  375. }
  376. /*
  377. * i8042_check_mux() checks whether the controller supports the PS/2 Active
  378. * Multiplexing specification by Synaptics, Phoenix, Insyde and
  379. * LCS/Telegraphics.
  380. */
  381. static int __devinit i8042_check_mux(void)
  382. {
  383. unsigned char mux_version;
  384. if (i8042_set_mux_mode(1, &mux_version))
  385. return -1;
  386. /*
  387. * Workaround for interference with USB Legacy emulation
  388. * that causes a v10.12 MUX to be found.
  389. */
  390. if (mux_version == 0xAC)
  391. return -1;
  392. printk(KERN_INFO "i8042.c: Detected active multiplexing controller, rev %d.%d.\n",
  393. (mux_version >> 4) & 0xf, mux_version & 0xf);
  394. /*
  395. * Disable all muxed ports by disabling AUX.
  396. */
  397. i8042_ctr |= I8042_CTR_AUXDIS;
  398. i8042_ctr &= ~I8042_CTR_AUXINT;
  399. if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
  400. printk(KERN_ERR "i8042.c: Failed to disable AUX port, can't use MUX.\n");
  401. return -EIO;
  402. }
  403. i8042_mux_present = 1;
  404. return 0;
  405. }
  406. /*
  407. * The following is used to test AUX IRQ delivery.
  408. */
  409. static struct completion i8042_aux_irq_delivered __devinitdata;
  410. static int i8042_irq_being_tested __devinitdata;
  411. static irqreturn_t __devinit i8042_aux_test_irq(int irq, void *dev_id)
  412. {
  413. unsigned long flags;
  414. unsigned char str, data;
  415. spin_lock_irqsave(&i8042_lock, flags);
  416. str = i8042_read_status();
  417. if (str & I8042_STR_OBF) {
  418. data = i8042_read_data();
  419. if (i8042_irq_being_tested &&
  420. data == 0xa5 && (str & I8042_STR_AUXDATA))
  421. complete(&i8042_aux_irq_delivered);
  422. }
  423. spin_unlock_irqrestore(&i8042_lock, flags);
  424. return IRQ_HANDLED;
  425. }
  426. /*
  427. * i8042_toggle_aux - enables or disables AUX port on i8042 via command and
  428. * verifies success by readinng CTR. Used when testing for presence of AUX
  429. * port.
  430. */
  431. static int __devinit i8042_toggle_aux(int on)
  432. {
  433. unsigned char param;
  434. int i;
  435. if (i8042_command(&param,
  436. on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE))
  437. return -1;
  438. /* some chips need some time to set the I8042_CTR_AUXDIS bit */
  439. for (i = 0; i < 100; i++) {
  440. udelay(50);
  441. if (i8042_command(&param, I8042_CMD_CTL_RCTR))
  442. return -1;
  443. if (!(param & I8042_CTR_AUXDIS) == on)
  444. return 0;
  445. }
  446. return -1;
  447. }
  448. /*
  449. * i8042_check_aux() applies as much paranoia as it can at detecting
  450. * the presence of an AUX interface.
  451. */
  452. static int __devinit i8042_check_aux(void)
  453. {
  454. int retval = -1;
  455. int irq_registered = 0;
  456. int aux_loop_broken = 0;
  457. unsigned long flags;
  458. unsigned char param;
  459. /*
  460. * Get rid of bytes in the queue.
  461. */
  462. i8042_flush();
  463. /*
  464. * Internal loopback test - filters out AT-type i8042's. Unfortunately
  465. * SiS screwed up and their 5597 doesn't support the LOOP command even
  466. * though it has an AUX port.
  467. */
  468. param = 0x5a;
  469. retval = i8042_command(&param, I8042_CMD_AUX_LOOP);
  470. if (retval || param != 0x5a) {
  471. /*
  472. * External connection test - filters out AT-soldered PS/2 i8042's
  473. * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error
  474. * 0xfa - no error on some notebooks which ignore the spec
  475. * Because it's common for chipsets to return error on perfectly functioning
  476. * AUX ports, we test for this only when the LOOP command failed.
  477. */
  478. if (i8042_command(&param, I8042_CMD_AUX_TEST) ||
  479. (param && param != 0xfa && param != 0xff))
  480. return -1;
  481. /*
  482. * If AUX_LOOP completed without error but returned unexpected data
  483. * mark it as broken
  484. */
  485. if (!retval)
  486. aux_loop_broken = 1;
  487. }
  488. /*
  489. * Bit assignment test - filters out PS/2 i8042's in AT mode
  490. */
  491. if (i8042_toggle_aux(0)) {
  492. printk(KERN_WARNING "Failed to disable AUX port, but continuing anyway... Is this a SiS?\n");
  493. printk(KERN_WARNING "If AUX port is really absent please use the 'i8042.noaux' option.\n");
  494. }
  495. if (i8042_toggle_aux(1))
  496. return -1;
  497. /*
  498. * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and
  499. * used it for a PCI card or somethig else.
  500. */
  501. if (i8042_noloop || aux_loop_broken) {
  502. /*
  503. * Without LOOP command we can't test AUX IRQ delivery. Assume the port
  504. * is working and hope we are right.
  505. */
  506. retval = 0;
  507. goto out;
  508. }
  509. if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED,
  510. "i8042", i8042_platform_device))
  511. goto out;
  512. irq_registered = 1;
  513. if (i8042_enable_aux_port())
  514. goto out;
  515. spin_lock_irqsave(&i8042_lock, flags);
  516. init_completion(&i8042_aux_irq_delivered);
  517. i8042_irq_being_tested = 1;
  518. param = 0xa5;
  519. retval = __i8042_command(&param, I8042_CMD_AUX_LOOP & 0xf0ff);
  520. spin_unlock_irqrestore(&i8042_lock, flags);
  521. if (retval)
  522. goto out;
  523. if (wait_for_completion_timeout(&i8042_aux_irq_delivered,
  524. msecs_to_jiffies(250)) == 0) {
  525. /*
  526. * AUX IRQ was never delivered so we need to flush the controller to
  527. * get rid of the byte we put there; otherwise keyboard may not work.
  528. */
  529. i8042_flush();
  530. retval = -1;
  531. }
  532. out:
  533. /*
  534. * Disable the interface.
  535. */
  536. i8042_ctr |= I8042_CTR_AUXDIS;
  537. i8042_ctr &= ~I8042_CTR_AUXINT;
  538. if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
  539. retval = -1;
  540. if (irq_registered)
  541. free_irq(I8042_AUX_IRQ, i8042_platform_device);
  542. return retval;
  543. }
  544. static int i8042_controller_check(void)
  545. {
  546. if (i8042_flush() == I8042_BUFFER_SIZE) {
  547. printk(KERN_ERR "i8042.c: No controller found.\n");
  548. return -ENODEV;
  549. }
  550. return 0;
  551. }
  552. static int i8042_controller_selftest(void)
  553. {
  554. unsigned char param;
  555. if (!i8042_reset)
  556. return 0;
  557. if (i8042_command(&param, I8042_CMD_CTL_TEST)) {
  558. printk(KERN_ERR "i8042.c: i8042 controller self test timeout.\n");
  559. return -ENODEV;
  560. }
  561. if (param != I8042_RET_CTL_TEST) {
  562. printk(KERN_ERR "i8042.c: i8042 controller selftest failed. (%#x != %#x)\n",
  563. param, I8042_RET_CTL_TEST);
  564. return -EIO;
  565. }
  566. return 0;
  567. }
  568. /*
  569. * i8042_controller init initializes the i8042 controller, and,
  570. * most importantly, sets it into non-xlated mode if that's
  571. * desired.
  572. */
  573. static int i8042_controller_init(void)
  574. {
  575. unsigned long flags;
  576. /*
  577. * Save the CTR for restoral on unload / reboot.
  578. */
  579. if (i8042_command(&i8042_ctr, I8042_CMD_CTL_RCTR)) {
  580. printk(KERN_ERR "i8042.c: Can't read CTR while initializing i8042.\n");
  581. return -EIO;
  582. }
  583. i8042_initial_ctr = i8042_ctr;
  584. /*
  585. * Disable the keyboard interface and interrupt.
  586. */
  587. i8042_ctr |= I8042_CTR_KBDDIS;
  588. i8042_ctr &= ~I8042_CTR_KBDINT;
  589. /*
  590. * Handle keylock.
  591. */
  592. spin_lock_irqsave(&i8042_lock, flags);
  593. if (~i8042_read_status() & I8042_STR_KEYLOCK) {
  594. if (i8042_unlock)
  595. i8042_ctr |= I8042_CTR_IGNKEYLOCK;
  596. else
  597. printk(KERN_WARNING "i8042.c: Warning: Keylock active.\n");
  598. }
  599. spin_unlock_irqrestore(&i8042_lock, flags);
  600. /*
  601. * If the chip is configured into nontranslated mode by the BIOS, don't
  602. * bother enabling translating and be happy.
  603. */
  604. if (~i8042_ctr & I8042_CTR_XLATE)
  605. i8042_direct = 1;
  606. /*
  607. * Set nontranslated mode for the kbd interface if requested by an option.
  608. * After this the kbd interface becomes a simple serial in/out, like the aux
  609. * interface is. We don't do this by default, since it can confuse notebook
  610. * BIOSes.
  611. */
  612. if (i8042_direct)
  613. i8042_ctr &= ~I8042_CTR_XLATE;
  614. /*
  615. * Write CTR back.
  616. */
  617. if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
  618. printk(KERN_ERR "i8042.c: Can't write CTR while initializing i8042.\n");
  619. return -EIO;
  620. }
  621. return 0;
  622. }
  623. /*
  624. * Reset the controller and reset CRT to the original value set by BIOS.
  625. */
  626. static void i8042_controller_reset(void)
  627. {
  628. i8042_flush();
  629. /*
  630. * Disable both KBD and AUX interfaces so they don't get in the way
  631. */
  632. i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS;
  633. i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT);
  634. /*
  635. * Disable MUX mode if present.
  636. */
  637. if (i8042_mux_present)
  638. i8042_set_mux_mode(0, NULL);
  639. /*
  640. * Reset the controller if requested.
  641. */
  642. i8042_controller_selftest();
  643. /*
  644. * Restore the original control register setting.
  645. */
  646. if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR))
  647. printk(KERN_WARNING "i8042.c: Can't restore CTR.\n");
  648. }
  649. /*
  650. * i8042_panic_blink() will flash the keyboard LEDs and is called when
  651. * kernel panics. Flashing LEDs is useful for users running X who may
  652. * not see the console and will help distingushing panics from "real"
  653. * lockups.
  654. *
  655. * Note that DELAY has a limit of 10ms so we will not get stuck here
  656. * waiting for KBC to free up even if KBD interrupt is off
  657. */
  658. #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0)
  659. static long i8042_panic_blink(long count)
  660. {
  661. long delay = 0;
  662. static long last_blink;
  663. static char led;
  664. /*
  665. * We expect frequency to be about 1/2s. KDB uses about 1s.
  666. * Make sure they are different.
  667. */
  668. if (!i8042_blink_frequency)
  669. return 0;
  670. if (count - last_blink < i8042_blink_frequency)
  671. return 0;
  672. led ^= 0x01 | 0x04;
  673. while (i8042_read_status() & I8042_STR_IBF)
  674. DELAY;
  675. dbg("%02x -> i8042 (panic blink)", 0xed);
  676. i8042_suppress_kbd_ack = 2;
  677. i8042_write_data(0xed); /* set leds */
  678. DELAY;
  679. while (i8042_read_status() & I8042_STR_IBF)
  680. DELAY;
  681. DELAY;
  682. dbg("%02x -> i8042 (panic blink)", led);
  683. i8042_write_data(led);
  684. DELAY;
  685. last_blink = count;
  686. return delay;
  687. }
  688. #undef DELAY
  689. #ifdef CONFIG_PM
  690. /*
  691. * Here we try to restore the original BIOS settings. We only want to
  692. * do that once, when we really suspend, not when we taking memory
  693. * snapshot for swsusp (in this case we'll perform required cleanup
  694. * as part of shutdown process).
  695. */
  696. static int i8042_suspend(struct platform_device *dev, pm_message_t state)
  697. {
  698. if (dev->dev.power.power_state.event != state.event) {
  699. if (state.event == PM_EVENT_SUSPEND)
  700. i8042_controller_reset();
  701. dev->dev.power.power_state = state;
  702. }
  703. return 0;
  704. }
  705. /*
  706. * Here we try to reset everything back to a state in which suspended
  707. */
  708. static int i8042_resume(struct platform_device *dev)
  709. {
  710. int error;
  711. /*
  712. * Do not bother with restoring state if we haven't suspened yet
  713. */
  714. if (dev->dev.power.power_state.event == PM_EVENT_ON)
  715. return 0;
  716. error = i8042_controller_check();
  717. if (error)
  718. return error;
  719. error = i8042_controller_selftest();
  720. if (error)
  721. return error;
  722. /*
  723. * Restore original CTR value and disable all ports
  724. */
  725. i8042_ctr = i8042_initial_ctr;
  726. if (i8042_direct)
  727. i8042_ctr &= ~I8042_CTR_XLATE;
  728. i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS;
  729. i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT);
  730. if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
  731. printk(KERN_ERR "i8042: Can't write CTR to resume\n");
  732. return -EIO;
  733. }
  734. if (i8042_mux_present) {
  735. if (i8042_set_mux_mode(1, NULL) || i8042_enable_mux_ports())
  736. printk(KERN_WARNING
  737. "i8042: failed to resume active multiplexor, "
  738. "mouse won't work.\n");
  739. } else if (i8042_ports[I8042_AUX_PORT_NO].serio)
  740. i8042_enable_aux_port();
  741. if (i8042_ports[I8042_KBD_PORT_NO].serio)
  742. i8042_enable_kbd_port();
  743. i8042_interrupt(0, NULL);
  744. dev->dev.power.power_state = PMSG_ON;
  745. return 0;
  746. }
  747. #endif /* CONFIG_PM */
  748. /*
  749. * We need to reset the 8042 back to original mode on system shutdown,
  750. * because otherwise BIOSes will be confused.
  751. */
  752. static void i8042_shutdown(struct platform_device *dev)
  753. {
  754. i8042_controller_reset();
  755. }
  756. static int __devinit i8042_create_kbd_port(void)
  757. {
  758. struct serio *serio;
  759. struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO];
  760. serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
  761. if (!serio)
  762. return -ENOMEM;
  763. serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL;
  764. serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write;
  765. serio->start = i8042_start;
  766. serio->stop = i8042_stop;
  767. serio->port_data = port;
  768. serio->dev.parent = &i8042_platform_device->dev;
  769. strlcpy(serio->name, "i8042 KBD port", sizeof(serio->name));
  770. strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys));
  771. port->serio = serio;
  772. port->irq = I8042_KBD_IRQ;
  773. return 0;
  774. }
  775. static int __devinit i8042_create_aux_port(int idx)
  776. {
  777. struct serio *serio;
  778. int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx;
  779. struct i8042_port *port = &i8042_ports[port_no];
  780. serio = kzalloc(sizeof(struct serio), GFP_KERNEL);
  781. if (!serio)
  782. return -ENOMEM;
  783. serio->id.type = SERIO_8042;
  784. serio->write = i8042_aux_write;
  785. serio->start = i8042_start;
  786. serio->stop = i8042_stop;
  787. serio->port_data = port;
  788. serio->dev.parent = &i8042_platform_device->dev;
  789. if (idx < 0) {
  790. strlcpy(serio->name, "i8042 AUX port", sizeof(serio->name));
  791. strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys));
  792. } else {
  793. snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx);
  794. snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1);
  795. }
  796. port->serio = serio;
  797. port->mux = idx;
  798. port->irq = I8042_AUX_IRQ;
  799. return 0;
  800. }
  801. static void __devinit i8042_free_kbd_port(void)
  802. {
  803. kfree(i8042_ports[I8042_KBD_PORT_NO].serio);
  804. i8042_ports[I8042_KBD_PORT_NO].serio = NULL;
  805. }
  806. static void __devinit i8042_free_aux_ports(void)
  807. {
  808. int i;
  809. for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) {
  810. kfree(i8042_ports[i].serio);
  811. i8042_ports[i].serio = NULL;
  812. }
  813. }
  814. static void __devinit i8042_register_ports(void)
  815. {
  816. int i;
  817. for (i = 0; i < I8042_NUM_PORTS; i++) {
  818. if (i8042_ports[i].serio) {
  819. printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n",
  820. i8042_ports[i].serio->name,
  821. (unsigned long) I8042_DATA_REG,
  822. (unsigned long) I8042_COMMAND_REG,
  823. i8042_ports[i].irq);
  824. serio_register_port(i8042_ports[i].serio);
  825. }
  826. }
  827. }
  828. static void __devinit i8042_unregister_ports(void)
  829. {
  830. int i;
  831. for (i = 0; i < I8042_NUM_PORTS; i++) {
  832. if (i8042_ports[i].serio) {
  833. serio_unregister_port(i8042_ports[i].serio);
  834. i8042_ports[i].serio = NULL;
  835. }
  836. }
  837. }
  838. static void i8042_free_irqs(void)
  839. {
  840. if (i8042_aux_irq_registered)
  841. free_irq(I8042_AUX_IRQ, i8042_platform_device);
  842. if (i8042_kbd_irq_registered)
  843. free_irq(I8042_KBD_IRQ, i8042_platform_device);
  844. i8042_aux_irq_registered = i8042_kbd_irq_registered = 0;
  845. }
  846. static int __devinit i8042_setup_aux(void)
  847. {
  848. int (*aux_enable)(void);
  849. int error;
  850. int i;
  851. if (i8042_check_aux())
  852. return -ENODEV;
  853. if (i8042_nomux || i8042_check_mux()) {
  854. error = i8042_create_aux_port(-1);
  855. if (error)
  856. goto err_free_ports;
  857. aux_enable = i8042_enable_aux_port;
  858. } else {
  859. for (i = 0; i < I8042_NUM_MUX_PORTS; i++) {
  860. error = i8042_create_aux_port(i);
  861. if (error)
  862. goto err_free_ports;
  863. }
  864. aux_enable = i8042_enable_mux_ports;
  865. }
  866. error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED,
  867. "i8042", i8042_platform_device);
  868. if (error)
  869. goto err_free_ports;
  870. if (aux_enable())
  871. goto err_free_irq;
  872. i8042_aux_irq_registered = 1;
  873. return 0;
  874. err_free_irq:
  875. free_irq(I8042_AUX_IRQ, i8042_platform_device);
  876. err_free_ports:
  877. i8042_free_aux_ports();
  878. return error;
  879. }
  880. static int __devinit i8042_setup_kbd(void)
  881. {
  882. int error;
  883. error = i8042_create_kbd_port();
  884. if (error)
  885. return error;
  886. error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED,
  887. "i8042", i8042_platform_device);
  888. if (error)
  889. goto err_free_port;
  890. error = i8042_enable_kbd_port();
  891. if (error)
  892. goto err_free_irq;
  893. i8042_kbd_irq_registered = 1;
  894. return 0;
  895. err_free_irq:
  896. free_irq(I8042_KBD_IRQ, i8042_platform_device);
  897. err_free_port:
  898. i8042_free_kbd_port();
  899. return error;
  900. }
  901. static int __devinit i8042_probe(struct platform_device *dev)
  902. {
  903. int error;
  904. error = i8042_controller_selftest();
  905. if (error)
  906. return error;
  907. error = i8042_controller_init();
  908. if (error)
  909. return error;
  910. if (!i8042_noaux) {
  911. error = i8042_setup_aux();
  912. if (error && error != -ENODEV && error != -EBUSY)
  913. goto out_fail;
  914. }
  915. if (!i8042_nokbd) {
  916. error = i8042_setup_kbd();
  917. if (error)
  918. goto out_fail;
  919. }
  920. /*
  921. * Ok, everything is ready, let's register all serio ports
  922. */
  923. i8042_register_ports();
  924. return 0;
  925. out_fail:
  926. i8042_free_aux_ports(); /* in case KBD failed but AUX not */
  927. i8042_free_irqs();
  928. i8042_controller_reset();
  929. return error;
  930. }
  931. static int __devexit i8042_remove(struct platform_device *dev)
  932. {
  933. i8042_unregister_ports();
  934. i8042_free_irqs();
  935. i8042_controller_reset();
  936. return 0;
  937. }
  938. static struct platform_driver i8042_driver = {
  939. .driver = {
  940. .name = "i8042",
  941. .owner = THIS_MODULE,
  942. },
  943. .probe = i8042_probe,
  944. .remove = __devexit_p(i8042_remove),
  945. .shutdown = i8042_shutdown,
  946. #ifdef CONFIG_PM
  947. .suspend = i8042_suspend,
  948. .resume = i8042_resume,
  949. #endif
  950. };
  951. static int __init i8042_init(void)
  952. {
  953. int err;
  954. dbg_init();
  955. err = i8042_platform_init();
  956. if (err)
  957. return err;
  958. err = i8042_controller_check();
  959. if (err)
  960. goto err_platform_exit;
  961. err = platform_driver_register(&i8042_driver);
  962. if (err)
  963. goto err_platform_exit;
  964. i8042_platform_device = platform_device_alloc("i8042", -1);
  965. if (!i8042_platform_device) {
  966. err = -ENOMEM;
  967. goto err_unregister_driver;
  968. }
  969. err = platform_device_add(i8042_platform_device);
  970. if (err)
  971. goto err_free_device;
  972. panic_blink = i8042_panic_blink;
  973. return 0;
  974. err_free_device:
  975. platform_device_put(i8042_platform_device);
  976. err_unregister_driver:
  977. platform_driver_unregister(&i8042_driver);
  978. err_platform_exit:
  979. i8042_platform_exit();
  980. return err;
  981. }
  982. static void __exit i8042_exit(void)
  983. {
  984. platform_device_unregister(i8042_platform_device);
  985. platform_driver_unregister(&i8042_driver);
  986. i8042_platform_exit();
  987. panic_blink = NULL;
  988. }
  989. module_init(i8042_init);
  990. module_exit(i8042_exit);