stv090x.c 109 KB

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  1. /*
  2. STV0900/0903 Multistandard Broadcast Frontend driver
  3. Copyright (C) Manu Abraham <abraham.manu@gmail.com>
  4. Copyright (C) ST Microelectronics
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 2 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  16. */
  17. #include <linux/init.h>
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/string.h>
  21. #include <linux/mutex.h>
  22. #include <linux/dvb/frontend.h>
  23. #include "dvb_frontend.h"
  24. #include "stv6110x.h" /* for demodulator internal modes */
  25. #include "stv090x_reg.h"
  26. #include "stv090x.h"
  27. #include "stv090x_priv.h"
  28. static unsigned int verbose;
  29. module_param(verbose, int, 0644);
  30. struct mutex demod_lock;
  31. /* DVBS1 and DSS C/N Lookup table */
  32. static const struct stv090x_tab stv090x_s1cn_tab[] = {
  33. { 0, 8917 }, /* 0.0dB */
  34. { 5, 8801 }, /* 0.5dB */
  35. { 10, 8667 }, /* 1.0dB */
  36. { 15, 8522 }, /* 1.5dB */
  37. { 20, 8355 }, /* 2.0dB */
  38. { 25, 8175 }, /* 2.5dB */
  39. { 30, 7979 }, /* 3.0dB */
  40. { 35, 7763 }, /* 3.5dB */
  41. { 40, 7530 }, /* 4.0dB */
  42. { 45, 7282 }, /* 4.5dB */
  43. { 50, 7026 }, /* 5.0dB */
  44. { 55, 6781 }, /* 5.5dB */
  45. { 60, 6514 }, /* 6.0dB */
  46. { 65, 6241 }, /* 6.5dB */
  47. { 70, 5965 }, /* 7.0dB */
  48. { 75, 5690 }, /* 7.5dB */
  49. { 80, 5424 }, /* 8.0dB */
  50. { 85, 5161 }, /* 8.5dB */
  51. { 90, 4902 }, /* 9.0dB */
  52. { 95, 4654 }, /* 9.5dB */
  53. { 100, 4417 }, /* 10.0dB */
  54. { 105, 4186 }, /* 10.5dB */
  55. { 110, 3968 }, /* 11.0dB */
  56. { 115, 3757 }, /* 11.5dB */
  57. { 120, 3558 }, /* 12.0dB */
  58. { 125, 3366 }, /* 12.5dB */
  59. { 130, 3185 }, /* 13.0dB */
  60. { 135, 3012 }, /* 13.5dB */
  61. { 140, 2850 }, /* 14.0dB */
  62. { 145, 2698 }, /* 14.5dB */
  63. { 150, 2550 }, /* 15.0dB */
  64. { 160, 2283 }, /* 16.0dB */
  65. { 170, 2042 }, /* 17.0dB */
  66. { 180, 1827 }, /* 18.0dB */
  67. { 190, 1636 }, /* 19.0dB */
  68. { 200, 1466 }, /* 20.0dB */
  69. { 210, 1315 }, /* 21.0dB */
  70. { 220, 1181 }, /* 22.0dB */
  71. { 230, 1064 }, /* 23.0dB */
  72. { 240, 960 }, /* 24.0dB */
  73. { 250, 869 }, /* 25.0dB */
  74. { 260, 792 }, /* 26.0dB */
  75. { 270, 724 }, /* 27.0dB */
  76. { 280, 665 }, /* 28.0dB */
  77. { 290, 616 }, /* 29.0dB */
  78. { 300, 573 }, /* 30.0dB */
  79. { 310, 537 }, /* 31.0dB */
  80. { 320, 507 }, /* 32.0dB */
  81. { 330, 483 }, /* 33.0dB */
  82. { 400, 398 }, /* 40.0dB */
  83. { 450, 381 }, /* 45.0dB */
  84. { 500, 377 } /* 50.0dB */
  85. };
  86. /* DVBS2 C/N Lookup table */
  87. static const struct stv090x_tab stv090x_s2cn_tab[] = {
  88. { -30, 13348 }, /* -3.0dB */
  89. { -20, 12640 }, /* -2d.0B */
  90. { -10, 11883 }, /* -1.0dB */
  91. { 0, 11101 }, /* -0.0dB */
  92. { 5, 10718 }, /* 0.5dB */
  93. { 10, 10339 }, /* 1.0dB */
  94. { 15, 9947 }, /* 1.5dB */
  95. { 20, 9552 }, /* 2.0dB */
  96. { 25, 9183 }, /* 2.5dB */
  97. { 30, 8799 }, /* 3.0dB */
  98. { 35, 8422 }, /* 3.5dB */
  99. { 40, 8062 }, /* 4.0dB */
  100. { 45, 7707 }, /* 4.5dB */
  101. { 50, 7353 }, /* 5.0dB */
  102. { 55, 7025 }, /* 5.5dB */
  103. { 60, 6684 }, /* 6.0dB */
  104. { 65, 6331 }, /* 6.5dB */
  105. { 70, 6036 }, /* 7.0dB */
  106. { 75, 5727 }, /* 7.5dB */
  107. { 80, 5437 }, /* 8.0dB */
  108. { 85, 5164 }, /* 8.5dB */
  109. { 90, 4902 }, /* 9.0dB */
  110. { 95, 4653 }, /* 9.5dB */
  111. { 100, 4408 }, /* 10.0dB */
  112. { 105, 4187 }, /* 10.5dB */
  113. { 110, 3961 }, /* 11.0dB */
  114. { 115, 3751 }, /* 11.5dB */
  115. { 120, 3558 }, /* 12.0dB */
  116. { 125, 3368 }, /* 12.5dB */
  117. { 130, 3191 }, /* 13.0dB */
  118. { 135, 3017 }, /* 13.5dB */
  119. { 140, 2862 }, /* 14.0dB */
  120. { 145, 2710 }, /* 14.5dB */
  121. { 150, 2565 }, /* 15.0dB */
  122. { 160, 2300 }, /* 16.0dB */
  123. { 170, 2058 }, /* 17.0dB */
  124. { 180, 1849 }, /* 18.0dB */
  125. { 190, 1663 }, /* 19.0dB */
  126. { 200, 1495 }, /* 20.0dB */
  127. { 210, 1349 }, /* 21.0dB */
  128. { 220, 1222 }, /* 22.0dB */
  129. { 230, 1110 }, /* 23.0dB */
  130. { 240, 1011 }, /* 24.0dB */
  131. { 250, 925 }, /* 25.0dB */
  132. { 260, 853 }, /* 26.0dB */
  133. { 270, 789 }, /* 27.0dB */
  134. { 280, 734 }, /* 28.0dB */
  135. { 290, 690 }, /* 29.0dB */
  136. { 300, 650 }, /* 30.0dB */
  137. { 310, 619 }, /* 31.0dB */
  138. { 320, 593 }, /* 32.0dB */
  139. { 330, 571 }, /* 33.0dB */
  140. { 400, 498 }, /* 40.0dB */
  141. { 450, 484 }, /* 45.0dB */
  142. { 500, 481 } /* 50.0dB */
  143. };
  144. /* RF level C/N lookup table */
  145. static const struct stv090x_tab stv090x_rf_tab[] = {
  146. { -5, 0xcaa1 }, /* -5dBm */
  147. { -10, 0xc229 }, /* -10dBm */
  148. { -15, 0xbb08 }, /* -15dBm */
  149. { -20, 0xb4bc }, /* -20dBm */
  150. { -25, 0xad5a }, /* -25dBm */
  151. { -30, 0xa298 }, /* -30dBm */
  152. { -35, 0x98a8 }, /* -35dBm */
  153. { -40, 0x8389 }, /* -40dBm */
  154. { -45, 0x59be }, /* -45dBm */
  155. { -50, 0x3a14 }, /* -50dBm */
  156. { -55, 0x2d11 }, /* -55dBm */
  157. { -60, 0x210d }, /* -60dBm */
  158. { -65, 0xa14f }, /* -65dBm */
  159. { -70, 0x07aa } /* -70dBm */
  160. };
  161. static struct stv090x_reg stv0900_initval[] = {
  162. { STV090x_OUTCFG, 0x00 },
  163. { STV090x_AGCRF1CFG, 0x11 },
  164. { STV090x_AGCRF2CFG, 0x13 },
  165. { STV090x_TSTTNR2, 0x21 },
  166. { STV090x_TSTTNR4, 0x21 },
  167. { STV090x_P2_DISTXCTL, 0x22 },
  168. { STV090x_P2_F22TX, 0xc0 },
  169. { STV090x_P2_F22RX, 0xc0 },
  170. { STV090x_P2_DISRXCTL, 0x00 },
  171. { STV090x_P2_DMDCFGMD, 0xF9 },
  172. { STV090x_P2_DEMOD, 0x08 },
  173. { STV090x_P2_DMDCFG3, 0xc4 },
  174. { STV090x_P2_CARFREQ, 0xed },
  175. { STV090x_P2_LDT, 0xd0 },
  176. { STV090x_P2_LDT2, 0xb8 },
  177. { STV090x_P2_TMGCFG, 0xd2 },
  178. { STV090x_P2_TMGTHRISE, 0x20 },
  179. { STV090x_P1_TMGCFG, 0xd2 },
  180. { STV090x_P2_TMGTHFALL, 0x00 },
  181. { STV090x_P2_FECSPY, 0x88 },
  182. { STV090x_P2_FSPYDATA, 0x3a },
  183. { STV090x_P2_FBERCPT4, 0x00 },
  184. { STV090x_P2_FSPYBER, 0x10 },
  185. { STV090x_P2_ERRCTRL1, 0x35 },
  186. { STV090x_P2_ERRCTRL2, 0xc1 },
  187. { STV090x_P2_CFRICFG, 0xf8 },
  188. { STV090x_P2_NOSCFG, 0x1c },
  189. { STV090x_P2_CORRELMANT, 0x70 },
  190. { STV090x_P2_CORRELABS, 0x88 },
  191. { STV090x_P2_AGC2REF, 0x38 },
  192. { STV090x_P2_CARCFG, 0xe4 },
  193. { STV090x_P2_ACLC, 0x1A },
  194. { STV090x_P2_BCLC, 0x09 },
  195. { STV090x_P2_CARHDR, 0x08 },
  196. { STV090x_P2_KREFTMG, 0xc1 },
  197. { STV090x_P2_SFRUPRATIO, 0xf0 },
  198. { STV090x_P2_SFRLOWRATIO, 0x70 },
  199. { STV090x_P2_SFRSTEP, 0x58 },
  200. { STV090x_P2_TMGCFG2, 0x01 },
  201. { STV090x_P2_CAR2CFG, 0x26 },
  202. { STV090x_P2_BCLC2S2Q, 0x86 },
  203. { STV090x_P2_BCLC2S28, 0x86 },
  204. { STV090x_P2_SMAPCOEF7, 0x77 },
  205. { STV090x_P2_SMAPCOEF6, 0x85 },
  206. { STV090x_P2_SMAPCOEF5, 0x77 },
  207. { STV090x_P2_TSCFGL, 0x20 },
  208. { STV090x_P2_DMDCFG2, 0x3b },
  209. { STV090x_P2_MODCODLST0, 0xff },
  210. { STV090x_P2_MODCODLST1, 0xff },
  211. { STV090x_P2_MODCODLST2, 0xff },
  212. { STV090x_P2_MODCODLST3, 0xff },
  213. { STV090x_P2_MODCODLST4, 0xff },
  214. { STV090x_P2_MODCODLST5, 0xff },
  215. { STV090x_P2_MODCODLST6, 0xff },
  216. { STV090x_P2_MODCODLST7, 0xcc },
  217. { STV090x_P2_MODCODLST8, 0xcc },
  218. { STV090x_P2_MODCODLST9, 0xcc },
  219. { STV090x_P2_MODCODLSTA, 0xcc },
  220. { STV090x_P2_MODCODLSTB, 0xcc },
  221. { STV090x_P2_MODCODLSTC, 0xcc },
  222. { STV090x_P2_MODCODLSTD, 0xcc },
  223. { STV090x_P2_MODCODLSTE, 0xcc },
  224. { STV090x_P2_MODCODLSTF, 0xcf },
  225. { STV090x_P1_DISTXCTL, 0x22 },
  226. { STV090x_P1_F22TX, 0xc0 },
  227. { STV090x_P1_F22RX, 0xc0 },
  228. { STV090x_P1_DISRXCTL, 0x00 },
  229. { STV090x_P1_DMDCFGMD, 0xf9 },
  230. { STV090x_P1_DEMOD, 0x08 },
  231. { STV090x_P1_DMDCFG3, 0xc4 },
  232. { STV090x_P1_CARFREQ, 0xed },
  233. { STV090x_P1_LDT, 0xd0 },
  234. { STV090x_P1_LDT2, 0xb8 },
  235. { STV090x_P1_TMGCFG, 0xd2 },
  236. { STV090x_P1_TMGTHRISE, 0x20 },
  237. { STV090x_P1_TMGTHFALL, 0x00 },
  238. { STV090x_P1_SFRUPRATIO, 0xf0 },
  239. { STV090x_P1_SFRLOWRATIO, 0x70 },
  240. { STV090x_P1_TSCFGL, 0x20 },
  241. { STV090x_P1_FECSPY, 0x88 },
  242. { STV090x_P1_FSPYDATA, 0x3a },
  243. { STV090x_P1_FBERCPT4, 0x00 },
  244. { STV090x_P1_FSPYBER, 0x10 },
  245. { STV090x_P1_ERRCTRL1, 0x35 },
  246. { STV090x_P1_ERRCTRL2, 0xc1 },
  247. { STV090x_P1_CFRICFG, 0xf8 },
  248. { STV090x_P1_NOSCFG, 0x1c },
  249. { STV090x_P1_CORRELMANT, 0x70 },
  250. { STV090x_P1_CORRELABS, 0x88 },
  251. { STV090x_P1_AGC2REF, 0x38 },
  252. { STV090x_P1_CARCFG, 0xe4 },
  253. { STV090x_P1_ACLC, 0x1A },
  254. { STV090x_P1_BCLC, 0x09 },
  255. { STV090x_P1_CARHDR, 0x08 },
  256. { STV090x_P1_KREFTMG, 0xc1 },
  257. { STV090x_P1_SFRSTEP, 0x58 },
  258. { STV090x_P1_TMGCFG2, 0x01 },
  259. { STV090x_P1_CAR2CFG, 0x26 },
  260. { STV090x_P1_BCLC2S2Q, 0x86 },
  261. { STV090x_P1_BCLC2S28, 0x86 },
  262. { STV090x_P1_SMAPCOEF7, 0x77 },
  263. { STV090x_P1_SMAPCOEF6, 0x85 },
  264. { STV090x_P1_SMAPCOEF5, 0x77 },
  265. { STV090x_P1_DMDCFG2, 0x3b },
  266. { STV090x_P1_MODCODLST0, 0xff },
  267. { STV090x_P1_MODCODLST1, 0xff },
  268. { STV090x_P1_MODCODLST2, 0xff },
  269. { STV090x_P1_MODCODLST3, 0xff },
  270. { STV090x_P1_MODCODLST4, 0xff },
  271. { STV090x_P1_MODCODLST5, 0xff },
  272. { STV090x_P1_MODCODLST6, 0xff },
  273. { STV090x_P1_MODCODLST7, 0xcc },
  274. { STV090x_P1_MODCODLST8, 0xcc },
  275. { STV090x_P1_MODCODLST9, 0xcc },
  276. { STV090x_P1_MODCODLSTA, 0xcc },
  277. { STV090x_P1_MODCODLSTB, 0xcc },
  278. { STV090x_P1_MODCODLSTC, 0xcc },
  279. { STV090x_P1_MODCODLSTD, 0xcc },
  280. { STV090x_P1_MODCODLSTE, 0xcc },
  281. { STV090x_P1_MODCODLSTF, 0xcf },
  282. { STV090x_GENCFG, 0x1d },
  283. { STV090x_NBITER_NF4, 0x37 },
  284. { STV090x_NBITER_NF5, 0x29 },
  285. { STV090x_NBITER_NF6, 0x37 },
  286. { STV090x_NBITER_NF7, 0x33 },
  287. { STV090x_NBITER_NF8, 0x31 },
  288. { STV090x_NBITER_NF9, 0x2f },
  289. { STV090x_NBITER_NF10, 0x39 },
  290. { STV090x_NBITER_NF11, 0x3a },
  291. { STV090x_NBITER_NF12, 0x29 },
  292. { STV090x_NBITER_NF13, 0x37 },
  293. { STV090x_NBITER_NF14, 0x33 },
  294. { STV090x_NBITER_NF15, 0x2f },
  295. { STV090x_NBITER_NF16, 0x39 },
  296. { STV090x_NBITER_NF17, 0x3a },
  297. { STV090x_NBITERNOERR, 0x04 },
  298. { STV090x_GAINLLR_NF4, 0x0C },
  299. { STV090x_GAINLLR_NF5, 0x0F },
  300. { STV090x_GAINLLR_NF6, 0x11 },
  301. { STV090x_GAINLLR_NF7, 0x14 },
  302. { STV090x_GAINLLR_NF8, 0x17 },
  303. { STV090x_GAINLLR_NF9, 0x19 },
  304. { STV090x_GAINLLR_NF10, 0x20 },
  305. { STV090x_GAINLLR_NF11, 0x21 },
  306. { STV090x_GAINLLR_NF12, 0x0D },
  307. { STV090x_GAINLLR_NF13, 0x0F },
  308. { STV090x_GAINLLR_NF14, 0x13 },
  309. { STV090x_GAINLLR_NF15, 0x1A },
  310. { STV090x_GAINLLR_NF16, 0x1F },
  311. { STV090x_GAINLLR_NF17, 0x21 },
  312. { STV090x_P1_FECM, 0x01 }, /* disable DSS modes */
  313. { STV090x_P2_FECM, 0x01 }, /* disable DSS modes */
  314. { STV090x_P1_PRVIT, 0x2F }, /* disable PR 6/7 */
  315. { STV090x_P2_PRVIT, 0x2F }, /* disable PR 6/7 */
  316. };
  317. static struct stv090x_reg stv0903_initval[] = {
  318. { STV090x_OUTCFG, 0x00 },
  319. { STV090x_AGCRF1CFG, 0x11 },
  320. { STV090x_STOPCLK1, 0x48 },
  321. { STV090x_STOPCLK2, 0x14 },
  322. { STV090x_TSTTNR1, 0x27 },
  323. { STV090x_TSTTNR2, 0x21 },
  324. { STV090x_P1_DISTXCTL, 0x22 },
  325. { STV090x_P1_F22TX, 0xc0 },
  326. { STV090x_P1_F22RX, 0xc0 },
  327. { STV090x_P1_DISRXCTL, 0x00 },
  328. { STV090x_P1_DMDCFGMD, 0xF9 },
  329. { STV090x_P1_DEMOD, 0x08 },
  330. { STV090x_P1_DMDCFG3, 0xc4 },
  331. { STV090x_P1_CARFREQ, 0xed },
  332. { STV090x_P1_TNRCFG2, 0x82 },
  333. { STV090x_P1_LDT, 0xd0 },
  334. { STV090x_P1_LDT2, 0xb8 },
  335. { STV090x_P1_TMGCFG, 0xd2 },
  336. { STV090x_P1_TMGTHRISE, 0x20 },
  337. { STV090x_P1_TMGTHFALL, 0x00 },
  338. { STV090x_P1_SFRUPRATIO, 0xf0 },
  339. { STV090x_P1_SFRLOWRATIO, 0x70 },
  340. { STV090x_P1_TSCFGL, 0x20 },
  341. { STV090x_P1_FECSPY, 0x88 },
  342. { STV090x_P1_FSPYDATA, 0x3a },
  343. { STV090x_P1_FBERCPT4, 0x00 },
  344. { STV090x_P1_FSPYBER, 0x10 },
  345. { STV090x_P1_ERRCTRL1, 0x35 },
  346. { STV090x_P1_ERRCTRL2, 0xc1 },
  347. { STV090x_P1_CFRICFG, 0xf8 },
  348. { STV090x_P1_NOSCFG, 0x1c },
  349. { STV090x_P1_CORRELMANT, 0x70 },
  350. { STV090x_P1_CORRELABS, 0x88 },
  351. { STV090x_P1_AGC2REF, 0x38 } ,
  352. { STV090x_P1_CARCFG, 0xe4 },
  353. { STV090x_P1_ACLC, 0x1A },
  354. { STV090x_P1_BCLC, 0x09 } ,
  355. { STV090x_P1_CARHDR, 0x08 },
  356. { STV090x_P1_KREFTMG, 0xc1 },
  357. { STV090x_P1_SFRSTEP, 0x58 },
  358. { STV090x_P1_TMGCFG2, 0x01 },
  359. { STV090x_P1_CAR2CFG, 0x26 },
  360. { STV090x_P1_BCLC2S2Q, 0x86 },
  361. { STV090x_P1_BCLC2S28, 0x86 },
  362. { STV090x_P1_SMAPCOEF7, 0x77 },
  363. { STV090x_P1_SMAPCOEF6, 0x85 },
  364. { STV090x_P1_SMAPCOEF5, 0x77 },
  365. { STV090x_P1_DMDCFG2, 0x3b },
  366. { STV090x_P1_MODCODLST0, 0xff },
  367. { STV090x_P1_MODCODLST1, 0xff },
  368. { STV090x_P1_MODCODLST2, 0xff },
  369. { STV090x_P1_MODCODLST3, 0xff },
  370. { STV090x_P1_MODCODLST4, 0xff },
  371. { STV090x_P1_MODCODLST5, 0xff },
  372. { STV090x_P1_MODCODLST6, 0xff },
  373. { STV090x_P1_MODCODLST7, 0xcc },
  374. { STV090x_P1_MODCODLST8, 0xcc },
  375. { STV090x_P1_MODCODLST9, 0xcc },
  376. { STV090x_P1_MODCODLSTA, 0xcc },
  377. { STV090x_P1_MODCODLSTB, 0xcc },
  378. { STV090x_P1_MODCODLSTC, 0xcc },
  379. { STV090x_P1_MODCODLSTD, 0xcc },
  380. { STV090x_P1_MODCODLSTE, 0xcc },
  381. { STV090x_P1_MODCODLSTF, 0xcf },
  382. { STV090x_GENCFG, 0x1c },
  383. { STV090x_NBITER_NF4, 0x37 },
  384. { STV090x_NBITER_NF5, 0x29 },
  385. { STV090x_NBITER_NF6, 0x37 },
  386. { STV090x_NBITER_NF7, 0x33 },
  387. { STV090x_NBITER_NF8, 0x31 },
  388. { STV090x_NBITER_NF9, 0x2f },
  389. { STV090x_NBITER_NF10, 0x39 },
  390. { STV090x_NBITER_NF11, 0x3a },
  391. { STV090x_NBITER_NF12, 0x29 },
  392. { STV090x_NBITER_NF13, 0x37 },
  393. { STV090x_NBITER_NF14, 0x33 },
  394. { STV090x_NBITER_NF15, 0x2f },
  395. { STV090x_NBITER_NF16, 0x39 },
  396. { STV090x_NBITER_NF17, 0x3a },
  397. { STV090x_NBITERNOERR, 0x04 },
  398. { STV090x_GAINLLR_NF4, 0x0C },
  399. { STV090x_GAINLLR_NF5, 0x0F },
  400. { STV090x_GAINLLR_NF6, 0x11 },
  401. { STV090x_GAINLLR_NF7, 0x14 },
  402. { STV090x_GAINLLR_NF8, 0x17 },
  403. { STV090x_GAINLLR_NF9, 0x19 },
  404. { STV090x_GAINLLR_NF10, 0x20 },
  405. { STV090x_GAINLLR_NF11, 0x21 },
  406. { STV090x_GAINLLR_NF12, 0x0D },
  407. { STV090x_GAINLLR_NF13, 0x0F },
  408. { STV090x_GAINLLR_NF14, 0x13 },
  409. { STV090x_GAINLLR_NF15, 0x1A },
  410. { STV090x_GAINLLR_NF16, 0x1F },
  411. { STV090x_GAINLLR_NF17, 0x21 },
  412. { STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */
  413. { STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/
  414. };
  415. static struct stv090x_reg stv0900_cut20_val[] = {
  416. { STV090x_P2_DMDCFG3, 0xe8 },
  417. { STV090x_P2_CARFREQ, 0x38 },
  418. { STV090x_P2_CARHDR, 0x20 },
  419. { STV090x_P2_KREFTMG, 0x5a },
  420. { STV090x_P2_SMAPCOEF7, 0x06 },
  421. { STV090x_P2_SMAPCOEF6, 0x00 },
  422. { STV090x_P2_SMAPCOEF5, 0x04 },
  423. { STV090x_P2_NOSCFG, 0x0c },
  424. { STV090x_P1_DMDCFG3, 0xe8 },
  425. { STV090x_P1_CARFREQ, 0x38 },
  426. { STV090x_P1_CARHDR, 0x20 },
  427. { STV090x_P1_KREFTMG, 0x5a },
  428. { STV090x_P1_SMAPCOEF7, 0x06 },
  429. { STV090x_P1_SMAPCOEF6, 0x00 },
  430. { STV090x_P1_SMAPCOEF5, 0x04 },
  431. { STV090x_P1_NOSCFG, 0x0c },
  432. { STV090x_GAINLLR_NF4, 0x21 },
  433. { STV090x_GAINLLR_NF5, 0x21 },
  434. { STV090x_GAINLLR_NF6, 0x20 },
  435. { STV090x_GAINLLR_NF7, 0x1F },
  436. { STV090x_GAINLLR_NF8, 0x1E },
  437. { STV090x_GAINLLR_NF9, 0x1E },
  438. { STV090x_GAINLLR_NF10, 0x1D },
  439. { STV090x_GAINLLR_NF11, 0x1B },
  440. { STV090x_GAINLLR_NF12, 0x20 },
  441. { STV090x_GAINLLR_NF13, 0x20 },
  442. { STV090x_GAINLLR_NF14, 0x20 },
  443. { STV090x_GAINLLR_NF15, 0x20 },
  444. { STV090x_GAINLLR_NF16, 0x20 },
  445. { STV090x_GAINLLR_NF17, 0x21 },
  446. };
  447. static struct stv090x_reg stv0903_cut20_val[] = {
  448. { STV090x_P1_DMDCFG3, 0xe8 },
  449. { STV090x_P1_CARFREQ, 0x38 },
  450. { STV090x_P1_CARHDR, 0x20 },
  451. { STV090x_P1_KREFTMG, 0x5a },
  452. { STV090x_P1_SMAPCOEF7, 0x06 },
  453. { STV090x_P1_SMAPCOEF6, 0x00 },
  454. { STV090x_P1_SMAPCOEF5, 0x04 },
  455. { STV090x_P1_NOSCFG, 0x0c },
  456. { STV090x_GAINLLR_NF4, 0x21 },
  457. { STV090x_GAINLLR_NF5, 0x21 },
  458. { STV090x_GAINLLR_NF6, 0x20 },
  459. { STV090x_GAINLLR_NF7, 0x1F },
  460. { STV090x_GAINLLR_NF8, 0x1E },
  461. { STV090x_GAINLLR_NF9, 0x1E },
  462. { STV090x_GAINLLR_NF10, 0x1D },
  463. { STV090x_GAINLLR_NF11, 0x1B },
  464. { STV090x_GAINLLR_NF12, 0x20 },
  465. { STV090x_GAINLLR_NF13, 0x20 },
  466. { STV090x_GAINLLR_NF14, 0x20 },
  467. { STV090x_GAINLLR_NF15, 0x20 },
  468. { STV090x_GAINLLR_NF16, 0x20 },
  469. { STV090x_GAINLLR_NF17, 0x21 }
  470. };
  471. /* Cut 1.x Long Frame Tracking CR loop */
  472. static struct stv090x_long_frame_crloop stv090x_s2_crl[] = {
  473. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  474. { STV090x_QPSK_12, 0x1c, 0x0d, 0x1b, 0x2c, 0x3a, 0x1c, 0x2a, 0x3b, 0x2a, 0x1b },
  475. { STV090x_QPSK_35, 0x2c, 0x0d, 0x2b, 0x2c, 0x3a, 0x0c, 0x3a, 0x2b, 0x2a, 0x0b },
  476. { STV090x_QPSK_23, 0x2c, 0x0d, 0x2b, 0x2c, 0x0b, 0x0c, 0x3a, 0x1b, 0x2a, 0x3a },
  477. { STV090x_QPSK_34, 0x3c, 0x0d, 0x3b, 0x1c, 0x0b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
  478. { STV090x_QPSK_45, 0x3c, 0x0d, 0x3b, 0x1c, 0x0b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
  479. { STV090x_QPSK_56, 0x0d, 0x0d, 0x3b, 0x1c, 0x0b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
  480. { STV090x_QPSK_89, 0x0d, 0x0d, 0x3b, 0x1c, 0x1b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
  481. { STV090x_QPSK_910, 0x1d, 0x0d, 0x3b, 0x1c, 0x1b, 0x3b, 0x3a, 0x0b, 0x2a, 0x3a },
  482. { STV090x_8PSK_35, 0x29, 0x3b, 0x09, 0x2b, 0x38, 0x0b, 0x18, 0x1a, 0x08, 0x0a },
  483. { STV090x_8PSK_23, 0x0a, 0x3b, 0x29, 0x2b, 0x19, 0x0b, 0x38, 0x1a, 0x18, 0x0a },
  484. { STV090x_8PSK_34, 0x3a, 0x3b, 0x2a, 0x2b, 0x39, 0x0b, 0x19, 0x1a, 0x38, 0x0a },
  485. { STV090x_8PSK_56, 0x1b, 0x3b, 0x0b, 0x2b, 0x1a, 0x0b, 0x39, 0x1a, 0x19, 0x0a },
  486. { STV090x_8PSK_89, 0x3b, 0x3b, 0x0b, 0x2b, 0x2a, 0x0b, 0x39, 0x1a, 0x29, 0x39 },
  487. { STV090x_8PSK_910, 0x3b, 0x3b, 0x0b, 0x2b, 0x2a, 0x0b, 0x39, 0x1a, 0x29, 0x39 }
  488. };
  489. /* Cut 2.0 Long Frame Tracking CR loop */
  490. static struct stv090x_long_frame_crloop stv090x_s2_crl_cut20[] = {
  491. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  492. { STV090x_QPSK_12, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x1e },
  493. { STV090x_QPSK_35, 0x2f, 0x3f, 0x2e, 0x2f, 0x3d, 0x0f, 0x0e, 0x2e, 0x3d, 0x0e },
  494. { STV090x_QPSK_23, 0x2f, 0x3f, 0x2e, 0x2f, 0x0e, 0x0f, 0x0e, 0x1e, 0x3d, 0x3d },
  495. { STV090x_QPSK_34, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  496. { STV090x_QPSK_45, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  497. { STV090x_QPSK_56, 0x3f, 0x3f, 0x3e, 0x1f, 0x0e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  498. { STV090x_QPSK_89, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  499. { STV090x_QPSK_910, 0x3f, 0x3f, 0x3e, 0x1f, 0x1e, 0x3e, 0x0e, 0x1e, 0x3d, 0x3d },
  500. { STV090x_8PSK_35, 0x3c, 0x3e, 0x1c, 0x2e, 0x0c, 0x1e, 0x2b, 0x2d, 0x1b, 0x1d },
  501. { STV090x_8PSK_23, 0x1d, 0x3e, 0x3c, 0x2e, 0x2c, 0x1e, 0x0c, 0x2d, 0x2b, 0x1d },
  502. { STV090x_8PSK_34, 0x0e, 0x3e, 0x3d, 0x2e, 0x0d, 0x1e, 0x2c, 0x2d, 0x0c, 0x1d },
  503. { STV090x_8PSK_56, 0x2e, 0x3e, 0x1e, 0x2e, 0x2d, 0x1e, 0x3c, 0x2d, 0x2c, 0x1d },
  504. { STV090x_8PSK_89, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x0d, 0x2d, 0x3c, 0x1d },
  505. { STV090x_8PSK_910, 0x3e, 0x3e, 0x1e, 0x2e, 0x3d, 0x1e, 0x1d, 0x2d, 0x0d, 0x1d }
  506. };
  507. /* Cut 2.0 Long Frame Tracking CR Loop */
  508. static struct stv090x_long_frame_crloop stv090x_s2_apsk_crl_cut20[] = {
  509. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  510. { STV090x_16APSK_23, 0x0c, 0x0c, 0x0c, 0x0c, 0x1d, 0x0c, 0x3c, 0x0c, 0x2c, 0x0c },
  511. { STV090x_16APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0e, 0x0c, 0x2d, 0x0c, 0x1d, 0x0c },
  512. { STV090x_16APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
  513. { STV090x_16APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x1e, 0x0c, 0x3d, 0x0c, 0x2d, 0x0c },
  514. { STV090x_16APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
  515. { STV090x_16APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x2e, 0x0c, 0x0e, 0x0c, 0x3d, 0x0c },
  516. { STV090x_32APSK_34, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
  517. { STV090x_32APSK_45, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
  518. { STV090x_32APSK_56, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
  519. { STV090x_32APSK_89, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c },
  520. { STV090x_32APSK_910, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c }
  521. };
  522. static struct stv090x_long_frame_crloop stv090x_s2_lowqpsk_crl_cut20[] = {
  523. /* MODCOD 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon 20MPoff 30MPon 30MPoff */
  524. { STV090x_QPSK_14, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x2d, 0x1f, 0x3d, 0x3e },
  525. { STV090x_QPSK_13, 0x0f, 0x3f, 0x0e, 0x3f, 0x2d, 0x2f, 0x3d, 0x0f, 0x3d, 0x2e },
  526. { STV090x_QPSK_25, 0x1f, 0x3f, 0x1e, 0x3f, 0x3d, 0x1f, 0x3d, 0x3e, 0x3d, 0x2e }
  527. };
  528. /* Cut 1.2 & 2.0 Short Frame Tracking CR Loop */
  529. static struct stv090x_short_frame_crloop stv090x_s2_short_crl[] = {
  530. /* MODCOD 2M_cut1.2 2M_cut2.0 5M_cut1.2 5M_cut2.0 10M_cut1.2 10M_cut2.0 20M_cut1.2 20M_cut2.0 30M_cut1.2 30M_cut2.0 */
  531. { STV090x_QPSK, 0x3c, 0x2f, 0x2b, 0x2e, 0x0b, 0x0e, 0x3a, 0x0e, 0x2a, 0x3d },
  532. { STV090x_8PSK, 0x0b, 0x3e, 0x2a, 0x0e, 0x0a, 0x2d, 0x19, 0x0d, 0x09, 0x3c },
  533. { STV090x_16APSK, 0x1b, 0x1e, 0x1b, 0x1e, 0x1b, 0x1e, 0x3a, 0x3d, 0x2a, 0x2d },
  534. { STV090x_32APSK, 0x1b, 0x1e, 0x1b, 0x1e, 0x1b, 0x1e, 0x3a, 0x3d, 0x2a, 0x2d }
  535. };
  536. static inline s32 comp2(s32 __x, s32 __width)
  537. {
  538. if (__width == 32)
  539. return __x;
  540. else
  541. return (__x >= (1 << (__width - 1))) ? (__x - (1 << __width)) : __x;
  542. }
  543. static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg)
  544. {
  545. const struct stv090x_config *config = state->config;
  546. int ret;
  547. u8 b0[] = { reg >> 8, reg & 0xff };
  548. u8 buf;
  549. struct i2c_msg msg[] = {
  550. { .addr = config->address, .flags = 0, .buf = b0, .len = 2 },
  551. { .addr = config->address, .flags = I2C_M_RD, .buf = &buf, .len = 1 }
  552. };
  553. ret = i2c_transfer(state->i2c, msg, 2);
  554. if (ret != 2) {
  555. if (ret != -ERESTARTSYS)
  556. dprintk(FE_ERROR, 1,
  557. "Read error, Reg=[0x%02x], Status=%d",
  558. reg, ret);
  559. return ret < 0 ? ret : -EREMOTEIO;
  560. }
  561. if (unlikely(*state->verbose >= FE_DEBUGREG))
  562. dprintk(FE_ERROR, 1, "Reg=[0x%02x], data=%02x",
  563. reg, buf);
  564. return (unsigned int) buf;
  565. }
  566. static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count)
  567. {
  568. const struct stv090x_config *config = state->config;
  569. int ret;
  570. u8 buf[2 + count];
  571. struct i2c_msg i2c_msg = { .addr = config->address, .flags = 0, .buf = buf, .len = 2 + count };
  572. buf[0] = reg >> 8;
  573. buf[1] = reg & 0xff;
  574. memcpy(&buf[2], data, count);
  575. if (unlikely(*state->verbose >= FE_DEBUGREG)) {
  576. int i;
  577. printk(KERN_DEBUG "%s [0x%04x]:", __func__, reg);
  578. for (i = 0; i < count; i++)
  579. printk(" %02x", data[i]);
  580. printk("\n");
  581. }
  582. ret = i2c_transfer(state->i2c, &i2c_msg, 1);
  583. if (ret != 1) {
  584. if (ret != -ERESTARTSYS)
  585. dprintk(FE_ERROR, 1, "Reg=[0x%04x], Data=[0x%02x ...], Count=%u, Status=%d",
  586. reg, data[0], count, ret);
  587. return ret < 0 ? ret : -EREMOTEIO;
  588. }
  589. return 0;
  590. }
  591. static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data)
  592. {
  593. return stv090x_write_regs(state, reg, &data, 1);
  594. }
  595. static int stv090x_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
  596. {
  597. struct stv090x_state *state = fe->demodulator_priv;
  598. const struct stv090x_config *config = state->config;
  599. u32 reg;
  600. reg = STV090x_READ_DEMOD(state, I2CRPT);
  601. // STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level);
  602. if (enable) {
  603. dprintk(FE_DEBUG, 1, "Enable Gate");
  604. STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1);
  605. if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0)
  606. goto err;
  607. } else {
  608. dprintk(FE_DEBUG, 1, "Disable Gate");
  609. STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0);
  610. if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0)
  611. goto err;
  612. }
  613. return 0;
  614. err:
  615. dprintk(FE_ERROR, 1, "I/O error");
  616. return -1;
  617. }
  618. static void stv090x_get_lock_tmg(struct stv090x_state *state)
  619. {
  620. switch (state->algo) {
  621. case STV090x_BLIND_SEARCH:
  622. dprintk(FE_DEBUG, 1, "Blind Search");
  623. if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/
  624. state->DemodTimeout = 1500;
  625. state->FecTimeout = 400;
  626. } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/
  627. state->DemodTimeout = 1000;
  628. state->FecTimeout = 300;
  629. } else { /*SR >20Msps*/
  630. state->DemodTimeout = 700;
  631. state->FecTimeout = 100;
  632. }
  633. break;
  634. case STV090x_COLD_SEARCH:
  635. case STV090x_WARM_SEARCH:
  636. default:
  637. dprintk(FE_DEBUG, 1, "Normal Search");
  638. if (state->srate <= 1000000) { /*SR <=1Msps*/
  639. state->DemodTimeout = 4500;
  640. state->FecTimeout = 1700;
  641. } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */
  642. state->DemodTimeout = 2500;
  643. state->FecTimeout = 1100;
  644. } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */
  645. state->DemodTimeout = 1000;
  646. state->FecTimeout = 550;
  647. } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */
  648. state->DemodTimeout = 700;
  649. state->FecTimeout = 250;
  650. } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */
  651. state->DemodTimeout = 400;
  652. state->FecTimeout = 130;
  653. } else { /*SR >20Msps*/
  654. state->DemodTimeout = 300;
  655. state->FecTimeout = 100;
  656. }
  657. break;
  658. }
  659. if (state->algo == STV090x_WARM_SEARCH)
  660. state->DemodTimeout /= 2;
  661. }
  662. static int stv090x_set_srate(struct stv090x_state *state, u32 srate)
  663. {
  664. u32 sym;
  665. if (srate > 6000000) {
  666. sym = (srate / 1000) * 65536;
  667. sym /= (state->mclk / 1000);
  668. } else {
  669. sym = (srate / 100) * 65536;
  670. sym /= (state->mclk / 100);
  671. }
  672. if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0) /* MSB */
  673. goto err;
  674. if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */
  675. goto err;
  676. return 0;
  677. err:
  678. dprintk(FE_ERROR, 1, "I/O error");
  679. return -1;
  680. }
  681. static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate)
  682. {
  683. u32 sym;
  684. srate = 105 * (srate / 100);
  685. if (srate > 6000000) {
  686. sym = (srate / 1000) * 65536;
  687. sym /= (clk / 1000);
  688. } else {
  689. sym = (srate / 100) * 65536;
  690. sym /= (clk / 100);
  691. }
  692. if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */
  693. goto err;
  694. if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */
  695. goto err;
  696. return 0;
  697. err:
  698. dprintk(FE_ERROR, 1, "I/O error");
  699. return -1;
  700. }
  701. static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate)
  702. {
  703. u32 sym;
  704. srate = 95 * (srate / 100);
  705. if (srate > 6000000) {
  706. sym = (srate / 1000) * 65536;
  707. sym /= (clk / 1000);
  708. } else {
  709. sym = (srate / 100) * 65536;
  710. sym /= (clk / 100);
  711. }
  712. if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0xff)) < 0) /* MSB */
  713. goto err;
  714. if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */
  715. goto err;
  716. return 0;
  717. err:
  718. dprintk(FE_ERROR, 1, "I/O error");
  719. return -1;
  720. }
  721. static u32 stv090x_car_width(u32 srate, u32 rolloff)
  722. {
  723. return srate + (srate * rolloff) / 100;
  724. }
  725. static int stv090x_set_vit_thacq(struct stv090x_state *state)
  726. {
  727. if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0)
  728. goto err;
  729. if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0)
  730. goto err;
  731. if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0)
  732. goto err;
  733. if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0)
  734. goto err;
  735. if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0)
  736. goto err;
  737. if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0)
  738. goto err;
  739. return 0;
  740. err:
  741. dprintk(FE_ERROR, 1, "I/O error");
  742. return -1;
  743. }
  744. static int stv090x_set_vit_thtracq(struct stv090x_state *state)
  745. {
  746. if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0)
  747. goto err;
  748. if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0)
  749. goto err;
  750. if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0)
  751. goto err;
  752. if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0)
  753. goto err;
  754. if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0)
  755. goto err;
  756. if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0)
  757. goto err;
  758. return 0;
  759. err:
  760. dprintk(FE_ERROR, 1, "I/O error");
  761. return -1;
  762. }
  763. static int stv090x_set_viterbi(struct stv090x_state *state)
  764. {
  765. switch (state->search_mode) {
  766. case STV090x_SEARCH_AUTO:
  767. if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */
  768. goto err;
  769. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */
  770. goto err;
  771. break;
  772. case STV090x_SEARCH_DVBS1:
  773. if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */
  774. goto err;
  775. switch (state->fec) {
  776. case STV090x_PR12:
  777. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
  778. goto err;
  779. break;
  780. case STV090x_PR23:
  781. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
  782. goto err;
  783. break;
  784. case STV090x_PR34:
  785. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0)
  786. goto err;
  787. break;
  788. case STV090x_PR56:
  789. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0)
  790. goto err;
  791. break;
  792. case STV090x_PR78:
  793. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0)
  794. goto err;
  795. break;
  796. default:
  797. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */
  798. goto err;
  799. break;
  800. }
  801. break;
  802. case STV090x_SEARCH_DSS:
  803. if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0)
  804. goto err;
  805. switch (state->fec) {
  806. case STV090x_PR12:
  807. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
  808. goto err;
  809. break;
  810. case STV090x_PR23:
  811. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
  812. goto err;
  813. break;
  814. case STV090x_PR67:
  815. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0)
  816. goto err;
  817. break;
  818. default:
  819. if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */
  820. goto err;
  821. break;
  822. }
  823. break;
  824. default:
  825. break;
  826. }
  827. return 0;
  828. err:
  829. dprintk(FE_ERROR, 1, "I/O error");
  830. return -1;
  831. }
  832. static int stv090x_stop_modcod(struct stv090x_state *state)
  833. {
  834. if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
  835. goto err;
  836. if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
  837. goto err;
  838. if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
  839. goto err;
  840. if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
  841. goto err;
  842. if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
  843. goto err;
  844. if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
  845. goto err;
  846. if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
  847. goto err;
  848. if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0)
  849. goto err;
  850. if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0)
  851. goto err;
  852. if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0)
  853. goto err;
  854. if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0)
  855. goto err;
  856. if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0)
  857. goto err;
  858. if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0)
  859. goto err;
  860. if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0)
  861. goto err;
  862. if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
  863. goto err;
  864. if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0)
  865. goto err;
  866. return 0;
  867. err:
  868. dprintk(FE_ERROR, 1, "I/O error");
  869. return -1;
  870. }
  871. static int stv090x_activate_modcod(struct stv090x_state *state)
  872. {
  873. u32 matype, modcod, f_mod, index;
  874. if (state->dev_ver <= 0x11) {
  875. msleep(5);
  876. modcod = STV090x_READ_DEMOD(state, PLHMODCOD);
  877. matype = modcod & 0x03;
  878. modcod = (modcod & 0x7f) >> 2;
  879. index = STV090x_ADDR_OFFST(state, MODCODLSTF) - (modcod / 2);
  880. switch (matype) {
  881. default:
  882. case 0:
  883. f_mod = 14;
  884. break;
  885. case 1:
  886. f_mod = 13;
  887. break;
  888. case 2:
  889. f_mod = 11;
  890. break;
  891. case 3:
  892. f_mod = 7;
  893. break;
  894. }
  895. if (matype <= 1) {
  896. if (modcod % 2) {
  897. if (stv090x_write_reg(state, index, 0xf0 | f_mod) < 0)
  898. goto err;
  899. } else {
  900. if (stv090x_write_reg(state, index, (f_mod << 4) | 0x0f) < 0)
  901. goto err;
  902. }
  903. }
  904. } else if (state->dev_ver >= 0x12) {
  905. if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
  906. goto err;
  907. if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0)
  908. goto err;
  909. if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0)
  910. goto err;
  911. if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0)
  912. goto err;
  913. if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0)
  914. goto err;
  915. if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0)
  916. goto err;
  917. if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0)
  918. goto err;
  919. if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
  920. goto err;
  921. if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
  922. goto err;
  923. if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
  924. goto err;
  925. if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
  926. goto err;
  927. if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
  928. goto err;
  929. if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
  930. goto err;
  931. if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
  932. goto err;
  933. if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0)
  934. goto err;
  935. if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
  936. goto err;
  937. }
  938. return 0;
  939. err:
  940. dprintk(FE_ERROR, 1, "I/O error");
  941. return -1;
  942. }
  943. static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable)
  944. {
  945. u32 reg;
  946. switch (state->demod) {
  947. case STV090x_DEMODULATOR_0:
  948. mutex_lock(&demod_lock);
  949. reg = stv090x_read_reg(state, STV090x_STOPCLK2);
  950. STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable);
  951. if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
  952. goto err;
  953. mutex_unlock(&demod_lock);
  954. break;
  955. case STV090x_DEMODULATOR_1:
  956. mutex_lock(&demod_lock);
  957. reg = stv090x_read_reg(state, STV090x_STOPCLK2);
  958. STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable);
  959. if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
  960. goto err;
  961. mutex_unlock(&demod_lock);
  962. break;
  963. default:
  964. dprintk(FE_ERROR, 1, "Wrong demodulator!");
  965. break;
  966. }
  967. return 0;
  968. err:
  969. mutex_unlock(&demod_lock);
  970. dprintk(FE_ERROR, 1, "I/O error");
  971. return -1;
  972. }
  973. static int stv090x_delivery_search(struct stv090x_state *state)
  974. {
  975. u32 reg;
  976. switch (state->search_mode) {
  977. case STV090x_SEARCH_DVBS1:
  978. case STV090x_SEARCH_DSS:
  979. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  980. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  981. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
  982. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  983. goto err;
  984. /* Activate Viterbi decoder in legacy search, do not use FRESVIT1, might impact VITERBI2 */
  985. if (stv090x_vitclk_ctl(state, 0) < 0)
  986. goto err;
  987. if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
  988. goto err;
  989. if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
  990. goto err;
  991. if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */
  992. goto err;
  993. stv090x_set_vit_thacq(state);
  994. stv090x_set_viterbi(state);
  995. break;
  996. case STV090x_SEARCH_DVBS2:
  997. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  998. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
  999. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
  1000. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1001. goto err;
  1002. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  1003. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
  1004. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1005. goto err;
  1006. if (stv090x_vitclk_ctl(state, 1) < 0)
  1007. goto err;
  1008. if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */
  1009. goto err;
  1010. if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
  1011. goto err;
  1012. if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
  1013. goto err;
  1014. if (state->demod_mode != STV090x_SINGLE) {
  1015. if (state->dev_ver <= 0x11) /* 900 in dual TS mode */
  1016. stv090x_stop_modcod(state);
  1017. else
  1018. stv090x_activate_modcod(state);
  1019. }
  1020. break;
  1021. case STV090x_SEARCH_AUTO:
  1022. default:
  1023. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1024. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
  1025. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
  1026. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1027. goto err;
  1028. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  1029. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
  1030. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1031. goto err;
  1032. if (stv090x_vitclk_ctl(state, 1) < 0)
  1033. goto err;
  1034. if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
  1035. goto err;
  1036. if (STV090x_WRITE_DEMOD(state, ACLC, 0x09) < 0)
  1037. goto err;
  1038. if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
  1039. goto err;
  1040. if (state->demod_mode != STV090x_SINGLE) {
  1041. if (state->dev_ver <= 0x11) /* 900 in dual TS mode */
  1042. stv090x_stop_modcod(state);
  1043. else
  1044. stv090x_activate_modcod(state);
  1045. }
  1046. stv090x_set_vit_thacq(state);
  1047. stv090x_set_viterbi(state);
  1048. break;
  1049. }
  1050. return 0;
  1051. err:
  1052. dprintk(FE_ERROR, 1, "I/O error");
  1053. return -1;
  1054. }
  1055. static int stv090x_start_search(struct stv090x_state *state)
  1056. {
  1057. u32 reg;
  1058. reg = STV090x_READ_DEMOD(state, DMDISTATE);
  1059. STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f);
  1060. if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
  1061. goto err;
  1062. if (state->dev_ver == 0x10) {
  1063. if (STV090x_WRITE_DEMOD(state, CORRELEXP, 0xaa) < 0)
  1064. goto err;
  1065. }
  1066. if (state->dev_ver < 0x20) {
  1067. if (STV090x_WRITE_DEMOD(state, CARHDR, 0x55) < 0)
  1068. goto err;
  1069. }
  1070. if (state->srate <= 5000000) {
  1071. if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0)
  1072. goto err;
  1073. if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0)
  1074. goto err;
  1075. if (STV090x_WRITE_DEMOD(state, CFRUP1, 0xff) < 0)
  1076. goto err;
  1077. if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0)
  1078. goto err;
  1079. if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0)
  1080. goto err;
  1081. /*enlarge the timing bandwith for Low SR*/
  1082. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0)
  1083. goto err;
  1084. } else {
  1085. /* If the symbol rate is >5 Msps
  1086. Set The carrier search up and low to auto mode */
  1087. if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
  1088. goto err;
  1089. /*reduce the timing bandwith for high SR*/
  1090. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
  1091. goto err;
  1092. }
  1093. if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0)
  1094. goto err;
  1095. if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0)
  1096. goto err;
  1097. if (state->dev_ver >= 0x20) {
  1098. if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
  1099. goto err;
  1100. if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
  1101. goto err;
  1102. if ((state->search_mode == STV090x_DVBS1) ||
  1103. (state->search_mode == STV090x_DSS) ||
  1104. (state->search_mode == STV090x_SEARCH_AUTO)) {
  1105. if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
  1106. goto err;
  1107. if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0)
  1108. goto err;
  1109. }
  1110. }
  1111. if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0)
  1112. goto err;
  1113. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0)
  1114. goto err;
  1115. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0)
  1116. goto err;
  1117. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1118. STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
  1119. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
  1120. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1121. goto err;
  1122. reg = STV090x_READ_DEMOD(state, DMDCFG2);
  1123. STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0);
  1124. if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0)
  1125. goto err;
  1126. if (state->dev_ver >= 0x20) { /*Frequency offset detector setting*/
  1127. if (state->srate < 10000000) {
  1128. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0)
  1129. goto err;
  1130. } else {
  1131. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0)
  1132. goto err;
  1133. }
  1134. } else {
  1135. if (state->srate < 10000000) {
  1136. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
  1137. goto err;
  1138. } else {
  1139. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
  1140. goto err;
  1141. }
  1142. }
  1143. switch (state->algo) {
  1144. case STV090x_WARM_SEARCH:/*The symbol rate and the exact carrier Frequency are known */
  1145. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  1146. goto err;
  1147. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
  1148. goto err;
  1149. break;
  1150. case STV090x_COLD_SEARCH:/*The symbol rate is known*/
  1151. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  1152. goto err;
  1153. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
  1154. goto err;
  1155. break;
  1156. default:
  1157. break;
  1158. }
  1159. return 0;
  1160. err:
  1161. dprintk(FE_ERROR, 1, "I/O error");
  1162. return -1;
  1163. }
  1164. static int stv090x_get_agc2_min_level(struct stv090x_state *state)
  1165. {
  1166. u32 agc2_min = 0, agc2 = 0, freq_init, freq_step, reg;
  1167. s32 i, j, steps, dir;
  1168. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
  1169. goto err;
  1170. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1171. STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
  1172. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 1);
  1173. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1174. goto err;
  1175. if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */
  1176. goto err;
  1177. if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
  1178. goto err;
  1179. if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */
  1180. goto err;
  1181. if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
  1182. goto err;
  1183. if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */
  1184. goto err;
  1185. stv090x_set_srate(state, 1000000);
  1186. steps = -1 + state->search_range / 1000000;
  1187. steps /= 2;
  1188. steps = (2 * steps) + 1;
  1189. if (steps < 0)
  1190. steps = 1;
  1191. dir = 1;
  1192. freq_step = (1000000 * 256) / (state->mclk / 256);
  1193. freq_init = 0;
  1194. for (i = 0; i < steps; i++) {
  1195. if (dir > 0)
  1196. freq_init = freq_init + (freq_step * i);
  1197. else
  1198. freq_init = freq_init - (freq_step * i);
  1199. dir = -1;
  1200. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */
  1201. goto err;
  1202. if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0)
  1203. goto err;
  1204. if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0)
  1205. goto err;
  1206. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */
  1207. goto err;
  1208. msleep(10);
  1209. for (j = 0; j < 10; j++) {
  1210. agc2 += STV090x_READ_DEMOD(state, AGC2I1) << 8;
  1211. agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
  1212. }
  1213. agc2 /= 10;
  1214. agc2_min = 0xffff;
  1215. if (agc2 < 0xffff)
  1216. agc2_min = agc2;
  1217. }
  1218. return agc2_min;
  1219. err:
  1220. dprintk(FE_ERROR, 1, "I/O error");
  1221. return -1;
  1222. }
  1223. static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk)
  1224. {
  1225. u8 r3, r2, r1, r0;
  1226. s32 srate, int_1, int_2, tmp_1, tmp_2;
  1227. u32 pow2;
  1228. r3 = STV090x_READ_DEMOD(state, SFR3);
  1229. r2 = STV090x_READ_DEMOD(state, SFR2);
  1230. r1 = STV090x_READ_DEMOD(state, SFR1);
  1231. r0 = STV090x_READ_DEMOD(state, SFR0);
  1232. srate = ((r3 << 24) | (r2 << 16) | (r1 << 8) | r0);
  1233. pow2 = 1 << 16;
  1234. int_1 = clk / pow2;
  1235. int_2 = srate / pow2;
  1236. tmp_1 = clk % pow2;
  1237. tmp_2 = srate % pow2;
  1238. srate = (int_1 * int_2) +
  1239. ((int_1 * tmp_2) / pow2) +
  1240. ((int_2 * tmp_1) / pow2);
  1241. return srate;
  1242. }
  1243. static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
  1244. {
  1245. struct dvb_frontend *fe = &state->frontend;
  1246. int tmg_lock = 0, i;
  1247. s32 tmg_cpt = 0, dir = 1, steps, cur_step = 0, freq;
  1248. u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg;
  1249. reg = STV090x_READ_DEMOD(state, DMDISTATE);
  1250. STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */
  1251. if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
  1252. goto err;
  1253. if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0)
  1254. goto err;
  1255. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0)
  1256. goto err;
  1257. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0)
  1258. goto err;
  1259. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1260. STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
  1261. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 1);
  1262. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1263. goto err;
  1264. if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0)
  1265. goto err;
  1266. if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
  1267. goto err;
  1268. if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0)
  1269. goto err;
  1270. if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
  1271. goto err;
  1272. if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0)
  1273. goto err;
  1274. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x60) < 0)
  1275. goto err;
  1276. if (state->dev_ver >= 0x20) {
  1277. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0)
  1278. goto err;
  1279. if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0)
  1280. goto err;
  1281. } else {
  1282. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
  1283. goto err;
  1284. if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x73) < 0)
  1285. goto err;
  1286. }
  1287. if (state->srate <= 2000000)
  1288. car_step = 1000;
  1289. else if (state->srate <= 5000000)
  1290. car_step = 2000;
  1291. else if (state->srate <= 12000000)
  1292. car_step = 3000;
  1293. else
  1294. car_step = 5000;
  1295. steps = -1 + ((state->search_range / 1000) / car_step);
  1296. steps /= 2;
  1297. steps = (2 * steps) + 1;
  1298. if (steps < 0)
  1299. steps = 1;
  1300. else if (steps > 10) {
  1301. steps = 11;
  1302. car_step = (state->search_range / 1000) / 10;
  1303. }
  1304. cur_step = 0;
  1305. dir = 1;
  1306. freq = state->frequency;
  1307. while ((!tmg_lock) && (cur_step < steps)) {
  1308. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */
  1309. goto err;
  1310. reg = STV090x_READ_DEMOD(state, DMDISTATE);
  1311. STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x00); /* trigger acquisition */
  1312. if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
  1313. goto err;
  1314. msleep(50);
  1315. for (i = 0; i < 10; i++) {
  1316. reg = STV090x_READ_DEMOD(state, DSTATUS);
  1317. if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
  1318. tmg_cpt++;
  1319. agc2 += STV090x_READ_DEMOD(state, AGC2I1) << 8;
  1320. agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
  1321. }
  1322. agc2 /= 10;
  1323. srate_coarse = stv090x_get_srate(state, state->mclk);
  1324. cur_step++;
  1325. dir *= -1;
  1326. if ((tmg_cpt >= 5) && (agc2 < 0x1f00) && (srate_coarse < 55000000) && (srate_coarse > 850000))
  1327. tmg_lock = 1;
  1328. else if (cur_step < steps) {
  1329. if (dir > 0)
  1330. freq += cur_step * car_step;
  1331. else
  1332. freq -= cur_step * car_step;
  1333. /* Setup tuner */
  1334. stv090x_i2c_gate_ctrl(fe, 1);
  1335. if (state->config->tuner_set_frequency)
  1336. state->config->tuner_set_frequency(fe, state->frequency);
  1337. if (state->config->tuner_set_bandwidth)
  1338. state->config->tuner_set_bandwidth(fe, state->tuner_bw);
  1339. stv090x_i2c_gate_ctrl(fe, 0);
  1340. msleep(50);
  1341. stv090x_i2c_gate_ctrl(fe, 1);
  1342. if (state->config->tuner_get_status)
  1343. state->config->tuner_get_status(fe, &reg);
  1344. if (reg)
  1345. dprintk(FE_DEBUG, 1, "Tuner phase locked");
  1346. else
  1347. dprintk(FE_DEBUG, 1, "Tuner unlocked");
  1348. stv090x_i2c_gate_ctrl(fe, 0);
  1349. }
  1350. }
  1351. if (!tmg_lock)
  1352. srate_coarse = 0;
  1353. else
  1354. srate_coarse = stv090x_get_srate(state, state->mclk);
  1355. return srate_coarse;
  1356. err:
  1357. dprintk(FE_ERROR, 1, "I/O error");
  1358. return -1;
  1359. }
  1360. static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
  1361. {
  1362. u32 srate_coarse, freq_coarse, sym, reg;
  1363. srate_coarse = stv090x_get_srate(state, state->mclk);
  1364. freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8;
  1365. freq_coarse |= STV090x_READ_DEMOD(state, CFR1);
  1366. sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
  1367. if (sym < state->srate)
  1368. srate_coarse = 0;
  1369. else {
  1370. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */
  1371. goto err;
  1372. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x01) < 0)
  1373. goto err;
  1374. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
  1375. goto err;
  1376. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
  1377. goto err;
  1378. if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
  1379. goto err;
  1380. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1381. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
  1382. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1383. goto err;
  1384. if (state->dev_ver >= 0x20) {
  1385. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
  1386. goto err;
  1387. } else {
  1388. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
  1389. goto err;
  1390. }
  1391. if (srate_coarse > 3000000) {
  1392. sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
  1393. sym = (sym / 1000) * 65536;
  1394. sym /= (state->mclk / 1000);
  1395. if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
  1396. goto err;
  1397. if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
  1398. goto err;
  1399. sym = 10 * (srate_coarse / 13); /* SFRLOW = SFR - 30% */
  1400. sym = (sym / 1000) * 65536;
  1401. sym /= (state->mclk / 1000);
  1402. if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
  1403. goto err;
  1404. if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
  1405. goto err;
  1406. sym = (srate_coarse / 1000) * 65536;
  1407. sym /= (state->mclk / 1000);
  1408. if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
  1409. goto err;
  1410. if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
  1411. goto err;
  1412. } else {
  1413. sym = 13 * (srate_coarse / 10); /* SFRUP = SFR + 30% */
  1414. sym = (sym / 100) * 65536;
  1415. sym /= (state->mclk / 100);
  1416. if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
  1417. goto err;
  1418. if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
  1419. goto err;
  1420. sym = 10 * (srate_coarse / 14); /* SFRLOW = SFR - 30% */
  1421. sym = (sym / 100) * 65536;
  1422. sym /= (state->mclk / 100);
  1423. if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
  1424. goto err;
  1425. if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
  1426. goto err;
  1427. sym = (srate_coarse / 100) * 65536;
  1428. sym /= (state->mclk / 100);
  1429. if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
  1430. goto err;
  1431. if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
  1432. goto err;
  1433. }
  1434. if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
  1435. goto err;
  1436. if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0)
  1437. goto err;
  1438. if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0)
  1439. goto err;
  1440. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */
  1441. goto err;
  1442. }
  1443. return srate_coarse;
  1444. err:
  1445. dprintk(FE_ERROR, 1, "I/O error");
  1446. return -1;
  1447. }
  1448. static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout)
  1449. {
  1450. s32 timer = 0, lock = 0;
  1451. u32 reg;
  1452. u8 stat;
  1453. while ((timer < timeout) && (!lock)) {
  1454. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  1455. stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
  1456. switch (stat) {
  1457. case 0: /* searching */
  1458. case 1: /* first PLH detected */
  1459. default:
  1460. dprintk(FE_DEBUG, 1, "Demodulator searching ..");
  1461. lock = 0;
  1462. break;
  1463. case 2: /* DVB-S2 mode */
  1464. case 3: /* DVB-S1/legacy mode */
  1465. reg = STV090x_READ_DEMOD(state, DSTATUS);
  1466. lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
  1467. break;
  1468. }
  1469. if (!lock)
  1470. msleep(10);
  1471. else
  1472. dprintk(FE_DEBUG, 1, "Demodulator acquired LOCK");
  1473. timer += 10;
  1474. }
  1475. return lock;
  1476. }
  1477. static int stv090x_blind_search(struct stv090x_state *state)
  1478. {
  1479. u32 agc2, reg, srate_coarse;
  1480. s32 timeout_dmd = 500, cpt_fail, agc2_ovflw, i;
  1481. u8 k_ref, k_max, k_min;
  1482. int coarse_fail, lock;
  1483. if (state->dev_ver < 0x20) {
  1484. k_max = 233;
  1485. k_min = 143;
  1486. } else {
  1487. k_max = 120;
  1488. k_min = 30;
  1489. }
  1490. agc2 = stv090x_get_agc2_min_level(state);
  1491. if (agc2 > STV090x_SEARCH_AGC2_TH) {
  1492. lock = 0;
  1493. } else {
  1494. if (state->dev_ver == 0x10) {
  1495. if (STV090x_WRITE_DEMOD(state, CORRELEXP, 0xaa) < 0)
  1496. goto err;
  1497. }
  1498. if (state->dev_ver < 0x20) {
  1499. if (STV090x_WRITE_DEMOD(state, CARHDR, 0x55) < 0)
  1500. goto err;
  1501. }
  1502. if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
  1503. goto err;
  1504. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
  1505. goto err;
  1506. if (state->dev_ver >= 0x20) {
  1507. if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
  1508. goto err;
  1509. if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
  1510. goto err;
  1511. if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
  1512. goto err;
  1513. if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */
  1514. goto err;
  1515. }
  1516. k_ref = k_max;
  1517. do {
  1518. if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0)
  1519. goto err;
  1520. if (stv090x_srate_srch_coarse(state) != 0) {
  1521. srate_coarse = stv090x_srate_srch_fine(state);
  1522. if (srate_coarse != 0) {
  1523. stv090x_get_lock_tmg(state);
  1524. lock = stv090x_get_dmdlock(state, timeout_dmd);
  1525. } else {
  1526. lock = 0;
  1527. }
  1528. } else {
  1529. cpt_fail = 0;
  1530. agc2_ovflw = 0;
  1531. for (i = 0; i < 10; i++) {
  1532. agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
  1533. agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
  1534. if (agc2 >= 0xff00)
  1535. agc2_ovflw++;
  1536. reg = STV090x_READ_DEMOD(state, DSTATUS2);
  1537. if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) &&
  1538. (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01))
  1539. cpt_fail++;
  1540. }
  1541. if ((cpt_fail > 7) || (agc2_ovflw > 7))
  1542. coarse_fail = 1;
  1543. lock = 0;
  1544. }
  1545. k_ref -= 30;
  1546. } while ((k_ref >= k_min) && (!lock) && (!coarse_fail));
  1547. }
  1548. return lock;
  1549. err:
  1550. dprintk(FE_ERROR, 1, "I/O error");
  1551. return -1;
  1552. }
  1553. static int stv090x_chk_tmg(struct stv090x_state *state)
  1554. {
  1555. u32 reg;
  1556. s32 tmg_cpt, i;
  1557. u8 freq, tmg_thh, tmg_thl;
  1558. int tmg_lock;
  1559. freq = STV090x_READ_DEMOD(state, CARFREQ);
  1560. tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE);
  1561. tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL);
  1562. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
  1563. goto err;
  1564. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
  1565. goto err;
  1566. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1567. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */
  1568. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1569. goto err;
  1570. if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0)
  1571. goto err;
  1572. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0)
  1573. goto err;
  1574. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0)
  1575. goto err;
  1576. if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */
  1577. goto err;
  1578. if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
  1579. goto err;
  1580. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0)
  1581. goto err;
  1582. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */
  1583. goto err;
  1584. msleep(10);
  1585. for (i = 0; i < 10; i++) {
  1586. reg = STV090x_READ_DEMOD(state, DSTATUS);
  1587. if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
  1588. tmg_cpt++;
  1589. msleep(1);
  1590. }
  1591. if (tmg_cpt >= 3)
  1592. tmg_lock = 1;
  1593. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
  1594. goto err;
  1595. if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */
  1596. goto err;
  1597. if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */
  1598. goto err;
  1599. if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0)
  1600. goto err;
  1601. if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0)
  1602. goto err;
  1603. if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0)
  1604. goto err;
  1605. return tmg_lock;
  1606. err:
  1607. dprintk(FE_ERROR, 1, "I/O error");
  1608. return -1;
  1609. }
  1610. static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
  1611. {
  1612. struct dvb_frontend *fe = &state->frontend;
  1613. u32 reg;
  1614. s32 car_step, steps, cur_step, dir, freq, timeout_lock;
  1615. int lock = 0;
  1616. if (state->srate >= 10000000)
  1617. timeout_lock = timeout_dmd / 3;
  1618. else
  1619. timeout_lock = timeout_dmd / 2;
  1620. lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */
  1621. if (!lock) {
  1622. if (state->srate >= 10000000) {
  1623. if (stv090x_chk_tmg(state)) {
  1624. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  1625. goto err;
  1626. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
  1627. goto err;
  1628. lock = stv090x_get_dmdlock(state, timeout_dmd);
  1629. } else {
  1630. lock = 0;
  1631. }
  1632. } else {
  1633. if (state->srate <= 4000000)
  1634. car_step = 1000;
  1635. else if (state->srate <= 7000000)
  1636. car_step = 2000;
  1637. else if (state->srate <= 10000000)
  1638. car_step = 3000;
  1639. else
  1640. car_step = 5000;
  1641. steps = (state->search_range / 1000) / car_step;
  1642. steps /= 2;
  1643. steps = 2 * (steps + 1);
  1644. if (steps < 0)
  1645. steps = 2;
  1646. else if (steps > 12)
  1647. steps = 12;
  1648. cur_step = 1;
  1649. dir = 1;
  1650. if (!lock) {
  1651. freq = state->frequency;
  1652. state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate;
  1653. while ((cur_step <= steps) && (!lock)) {
  1654. if (dir > 0)
  1655. freq += cur_step * car_step;
  1656. else
  1657. freq -= cur_step * car_step;
  1658. /* Setup tuner */
  1659. stv090x_i2c_gate_ctrl(fe, 1);
  1660. if (state->config->tuner_set_frequency)
  1661. state->config->tuner_set_frequency(fe, state->frequency);
  1662. if (state->config->tuner_set_bandwidth)
  1663. state->config->tuner_set_bandwidth(fe, state->tuner_bw);
  1664. stv090x_i2c_gate_ctrl(fe, 0);
  1665. msleep(50);
  1666. stv090x_i2c_gate_ctrl(fe, 1);
  1667. if (state->config->tuner_get_status)
  1668. state->config->tuner_get_status(fe, &reg);
  1669. if (reg)
  1670. dprintk(FE_DEBUG, 1, "Tuner phase locked");
  1671. else
  1672. dprintk(FE_DEBUG, 1, "Tuner unlocked");
  1673. stv090x_i2c_gate_ctrl(fe, 0);
  1674. STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c);
  1675. if (state->delsys == STV090x_DVBS2) {
  1676. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  1677. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
  1678. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
  1679. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1680. goto err;
  1681. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  1682. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
  1683. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  1684. goto err;
  1685. }
  1686. if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
  1687. goto err;
  1688. if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
  1689. goto err;
  1690. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  1691. goto err;
  1692. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
  1693. goto err;
  1694. lock = stv090x_get_dmdlock(state, (timeout_dmd / 3));
  1695. dir *= -1;
  1696. cur_step++;
  1697. }
  1698. }
  1699. }
  1700. }
  1701. return lock;
  1702. err:
  1703. dprintk(FE_ERROR, 1, "I/O error");
  1704. return -1;
  1705. }
  1706. static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps)
  1707. {
  1708. s32 timeout, inc, steps_max, srate, car_max;
  1709. srate = state->srate;
  1710. car_max = state->search_range / 1000;
  1711. car_max = 65536 * (car_max / 2);
  1712. car_max /= (state->mclk / 1000);
  1713. if (car_max > 0x4000)
  1714. car_max = 0x4000 ; /* maxcarrier should be<= +-1/4 Mclk */
  1715. inc = srate;
  1716. inc /= state->mclk / 1000;
  1717. inc *= 256;
  1718. inc *= 256;
  1719. inc /= 1000;
  1720. switch (state->algo) {
  1721. case STV090x_SEARCH_DVBS1:
  1722. case STV090x_SEARCH_DSS:
  1723. inc *= 3; /* freq step = 3% of srate */
  1724. timeout = 20;
  1725. break;
  1726. case STV090x_SEARCH_DVBS2:
  1727. inc *= 4;
  1728. timeout = 25;
  1729. break;
  1730. case STV090x_SEARCH_AUTO:
  1731. default:
  1732. inc *= 3;
  1733. timeout = 25;
  1734. break;
  1735. }
  1736. inc /= 100;
  1737. if ((inc > car_max) || (inc < 0))
  1738. inc = car_max / 2; /* increment <= 1/8 Mclk */
  1739. timeout *= 27500; /* 27.5 Msps reference */
  1740. if (srate > 0)
  1741. timeout /= (srate / 1000);
  1742. if ((timeout > 100) || (timeout < 0))
  1743. timeout = 100;
  1744. steps_max = (car_max / inc) + 1; /* min steps = 3 */
  1745. if ((steps_max > 100) || (steps_max < 0)) {
  1746. steps_max = 100; /* max steps <= 100 */
  1747. inc = car_max / steps_max;
  1748. }
  1749. *freq_inc = inc;
  1750. *timeout_sw = timeout;
  1751. *steps = steps_max;
  1752. return 0;
  1753. }
  1754. static int stv090x_chk_signal(struct stv090x_state *state)
  1755. {
  1756. s32 offst_car, agc2, car_max;
  1757. int no_signal;
  1758. offst_car = STV090x_READ_DEMOD(state, CFR2) << 8;
  1759. offst_car |= STV090x_READ_DEMOD(state, CFR1);
  1760. agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
  1761. agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
  1762. car_max = state->search_range / 1000;
  1763. car_max += (car_max / 10); /* 10% margin */
  1764. car_max = (65536 * car_max / 2);
  1765. car_max /= state->mclk / 1000;
  1766. if (car_max > 0x4000)
  1767. car_max = 0x4000;
  1768. if ((agc2 > 0x2000) || (offst_car > 2 * car_max) || (offst_car < -2 * car_max)) {
  1769. no_signal = 1;
  1770. dprintk(FE_DEBUG, 1, "No Signal");
  1771. } else {
  1772. no_signal = 0;
  1773. dprintk(FE_DEBUG, 1, "Found Signal");
  1774. }
  1775. return no_signal;
  1776. }
  1777. static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max)
  1778. {
  1779. int no_signal, lock = 0;
  1780. s32 cpt_step, offst_freq, car_max;
  1781. u32 reg;
  1782. car_max = state->search_range / 1000;
  1783. car_max += (car_max / 10);
  1784. car_max = (65536 * car_max / 2);
  1785. car_max /= (state->mclk / 1000);
  1786. if (car_max > 0x4000)
  1787. car_max = 0x4000;
  1788. if (zigzag)
  1789. offst_freq = 0;
  1790. else
  1791. offst_freq = -car_max + inc;
  1792. cpt_step = 0;
  1793. do {
  1794. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
  1795. goto err;
  1796. if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0)
  1797. goto err;
  1798. if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0)
  1799. goto err;
  1800. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
  1801. goto err;
  1802. reg = STV090x_READ_DEMOD(state, PDELCTRL1);
  1803. STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */
  1804. if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
  1805. goto err;
  1806. if (state->dev_ver == 0x12) {
  1807. reg = STV090x_READ_DEMOD(state, TSCFGH);
  1808. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x1);
  1809. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  1810. goto err;
  1811. }
  1812. if (zigzag) {
  1813. if (offst_freq >= 0)
  1814. offst_freq = -offst_freq - 2 * inc;
  1815. else
  1816. offst_freq = -offst_freq;
  1817. } else {
  1818. offst_freq += 2 * inc;
  1819. }
  1820. lock = stv090x_get_dmdlock(state, timeout);
  1821. no_signal = stv090x_chk_signal(state);
  1822. } while ((!lock) &&
  1823. (!no_signal) &&
  1824. ((offst_freq - inc) < car_max) &&
  1825. ((offst_freq + inc) > -car_max) &&
  1826. (cpt_step < steps_max));
  1827. reg = STV090x_READ_DEMOD(state, PDELCTRL1);
  1828. STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0);
  1829. if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
  1830. goto err;
  1831. return lock;
  1832. err:
  1833. dprintk(FE_ERROR, 1, "I/O error");
  1834. return -1;
  1835. }
  1836. static int stv090x_sw_algo(struct stv090x_state *state)
  1837. {
  1838. int no_signal, zigzag, lock = 0;
  1839. u32 reg;
  1840. s32 dvbs2_fly_wheel;
  1841. s32 inc, timeout_step, trials, steps_max;
  1842. stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max); /* get params */
  1843. switch (state->algo) {
  1844. case STV090x_SEARCH_DVBS1:
  1845. case STV090x_SEARCH_DSS:
  1846. /* accelerate the frequency detector */
  1847. if (state->dev_ver >= 0x20) {
  1848. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0)
  1849. goto err;
  1850. } else {
  1851. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
  1852. goto err;
  1853. }
  1854. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0)
  1855. goto err;
  1856. zigzag = 0;
  1857. break;
  1858. case STV090x_SEARCH_DVBS2:
  1859. if (state->dev_ver >= 0x20) {
  1860. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
  1861. goto err;
  1862. } else {
  1863. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x68) < 0)
  1864. goto err;
  1865. }
  1866. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
  1867. goto err;
  1868. zigzag = 1;
  1869. break;
  1870. case STV090x_SEARCH_AUTO:
  1871. default:
  1872. /* accelerate the frequency detector */
  1873. if (state->dev_ver >= 0x20) {
  1874. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0)
  1875. goto err;
  1876. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
  1877. goto err;
  1878. } else {
  1879. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
  1880. goto err;
  1881. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x68) < 0)
  1882. goto err;
  1883. }
  1884. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x69) < 0)
  1885. goto err;
  1886. zigzag = 0;
  1887. break;
  1888. }
  1889. trials = 0;
  1890. do {
  1891. lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max);
  1892. no_signal = stv090x_chk_signal(state);
  1893. trials++;
  1894. /*run the SW search 2 times maximum*/
  1895. if (lock || no_signal || (trials == 2)) {
  1896. /*Check if the demod is not losing lock in DVBS2*/
  1897. if (state->dev_ver >= 0x20) {
  1898. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
  1899. goto err;
  1900. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
  1901. goto err;
  1902. } else {
  1903. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
  1904. goto err;
  1905. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x88) < 0)
  1906. goto err;
  1907. }
  1908. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  1909. if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) {
  1910. /*Check if the demod is not losing lock in DVBS2*/
  1911. msleep(timeout_step);
  1912. reg = STV090x_READ_DEMOD(state, DMDFLYW);
  1913. dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
  1914. if (dvbs2_fly_wheel < 0xd) { /*if correct frames is decrementing */
  1915. msleep(timeout_step);
  1916. reg = STV090x_READ_DEMOD(state, DMDFLYW);
  1917. dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
  1918. }
  1919. if (dvbs2_fly_wheel < 0xd) {
  1920. /*FALSE lock, The demod is loosing lock */
  1921. lock = 0;
  1922. if (trials < 2) {
  1923. if (state->dev_ver >= 0x20) {
  1924. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
  1925. goto err;
  1926. } else {
  1927. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x68) < 0)
  1928. goto err;
  1929. }
  1930. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
  1931. goto err;
  1932. }
  1933. }
  1934. }
  1935. }
  1936. } while ((!lock) && (trials < 2) && (!no_signal));
  1937. return lock;
  1938. err:
  1939. dprintk(FE_ERROR, 1, "I/O error");
  1940. return -1;
  1941. }
  1942. static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state)
  1943. {
  1944. u32 reg;
  1945. enum stv090x_delsys delsys;
  1946. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  1947. if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2)
  1948. delsys = STV090x_DVBS2;
  1949. else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) {
  1950. reg = STV090x_READ_DEMOD(state, FECM);
  1951. if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1)
  1952. delsys = STV090x_DSS;
  1953. else
  1954. delsys = STV090x_DVBS1;
  1955. } else {
  1956. delsys = STV090x_ERROR;
  1957. }
  1958. return delsys;
  1959. }
  1960. /* in Hz */
  1961. static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk)
  1962. {
  1963. s32 derot, int_1, int_2, tmp_1, tmp_2;
  1964. u32 pow2;
  1965. derot = STV090x_READ_DEMOD(state, CFR2) << 16;
  1966. derot |= STV090x_READ_DEMOD(state, CFR1) << 8;
  1967. derot |= STV090x_READ_DEMOD(state, CFR0);
  1968. derot = comp2(derot, 24);
  1969. pow2 = 1 << 12;
  1970. int_1 = state->mclk / pow2;
  1971. int_2 = derot / pow2;
  1972. tmp_1 = state->mclk % pow2;
  1973. tmp_2 = derot % pow2;
  1974. derot = (int_1 * int_2) +
  1975. ((int_1 * tmp_2) / pow2) +
  1976. ((int_1 * tmp_1) / pow2);
  1977. return derot;
  1978. }
  1979. static int stv090x_get_viterbi(struct stv090x_state *state)
  1980. {
  1981. u32 reg, rate;
  1982. reg = STV090x_READ_DEMOD(state, VITCURPUN);
  1983. rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD);
  1984. switch (rate) {
  1985. case 13:
  1986. state->fec = STV090x_PR12;
  1987. break;
  1988. case 18:
  1989. state->fec = STV090x_PR23;
  1990. break;
  1991. case 21:
  1992. state->fec = STV090x_PR34;
  1993. break;
  1994. case 24:
  1995. state->fec = STV090x_PR56;
  1996. break;
  1997. case 25:
  1998. state->fec = STV090x_PR67;
  1999. break;
  2000. case 26:
  2001. state->fec = STV090x_PR78;
  2002. break;
  2003. default:
  2004. state->fec = STV090x_PRERR;
  2005. break;
  2006. }
  2007. return 0;
  2008. }
  2009. static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state)
  2010. {
  2011. struct dvb_frontend *fe = &state->frontend;
  2012. u8 tmg;
  2013. u32 reg;
  2014. s32 i = 0, offst_freq;
  2015. msleep(5);
  2016. if (state->algo == STV090x_BLIND_SEARCH) {
  2017. tmg = STV090x_READ_DEMOD(state, TMGREG2);
  2018. STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c);
  2019. while ((i <= 50) && (!tmg) && (tmg != 0xff)) {
  2020. tmg = STV090x_READ_DEMOD(state, TMGREG2);
  2021. msleep(5);
  2022. i += 5;
  2023. }
  2024. }
  2025. state->delsys = stv090x_get_std(state);
  2026. stv090x_i2c_gate_ctrl(fe, 1);
  2027. if (state->config->tuner_get_frequency)
  2028. state->config->tuner_get_frequency(fe, &state->frequency);
  2029. stv090x_i2c_gate_ctrl(fe, 0);
  2030. offst_freq = stv090x_get_car_freq(state, state->mclk) / 1000;
  2031. state->frequency += offst_freq;
  2032. stv090x_get_viterbi(state);
  2033. reg = STV090x_READ_DEMOD(state, DMDMODCOD);
  2034. state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
  2035. state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
  2036. state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1;
  2037. reg = STV090x_READ_DEMOD(state, TMGOBS);
  2038. state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
  2039. reg = STV090x_READ_DEMOD(state, FECM);
  2040. state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD);
  2041. if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) {
  2042. stv090x_i2c_gate_ctrl(fe, 1);
  2043. if (state->config->tuner_get_frequency)
  2044. state->config->tuner_get_frequency(fe, &state->frequency);
  2045. stv090x_i2c_gate_ctrl(fe, 0);
  2046. if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
  2047. return STV090x_RANGEOK;
  2048. else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000))
  2049. return STV090x_RANGEOK;
  2050. else
  2051. return STV090x_OUTOFRANGE; /* Out of Range */
  2052. } else {
  2053. if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
  2054. return STV090x_RANGEOK;
  2055. else
  2056. return STV090x_OUTOFRANGE;
  2057. }
  2058. return STV090x_OUTOFRANGE;
  2059. }
  2060. static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate)
  2061. {
  2062. s32 offst_tmg;
  2063. s32 pow2;
  2064. offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16;
  2065. offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8;
  2066. offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0);
  2067. pow2 = 1 << 24;
  2068. offst_tmg = comp2(offst_tmg, 24); /* 2's complement */
  2069. if (!offst_tmg)
  2070. offst_tmg = 1;
  2071. offst_tmg = ((s32) srate * 10) / (pow2 / offst_tmg);
  2072. offst_tmg /= 320;
  2073. return offst_tmg;
  2074. }
  2075. static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots)
  2076. {
  2077. u8 aclc = 0x29;
  2078. s32 i;
  2079. struct stv090x_long_frame_crloop *car_loop;
  2080. if (state->dev_ver <= 0x12)
  2081. car_loop = stv090x_s2_crl;
  2082. else if (state->dev_ver == 0x20)
  2083. car_loop = stv090x_s2_crl_cut20;
  2084. else
  2085. car_loop = stv090x_s2_crl;
  2086. if (modcod < STV090x_QPSK_12) {
  2087. i = 0;
  2088. while ((i < 3) && (modcod != stv090x_s2_lowqpsk_crl_cut20[i].modcod))
  2089. i++;
  2090. if (i >= 3)
  2091. i = 2;
  2092. } else {
  2093. i = 0;
  2094. while ((i < 14) && (modcod != car_loop[i].modcod))
  2095. i++;
  2096. if (i >= 14) {
  2097. i = 0;
  2098. while ((i < 11) && (modcod != stv090x_s2_lowqpsk_crl_cut20[i].modcod))
  2099. i++;
  2100. if (i >= 11)
  2101. i = 10;
  2102. }
  2103. }
  2104. if (modcod <= STV090x_QPSK_25) {
  2105. if (pilots) {
  2106. if (state->srate <= 3000000)
  2107. aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_2;
  2108. else if (state->srate <= 7000000)
  2109. aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_5;
  2110. else if (state->srate <= 15000000)
  2111. aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_10;
  2112. else if (state->srate <= 25000000)
  2113. aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_20;
  2114. else
  2115. aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_on_30;
  2116. } else {
  2117. if (state->srate <= 3000000)
  2118. aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_2;
  2119. else if (state->srate <= 7000000)
  2120. aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_5;
  2121. else if (state->srate <= 15000000)
  2122. aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_10;
  2123. else if (state->srate <= 25000000)
  2124. aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_20;
  2125. else
  2126. aclc = stv090x_s2_lowqpsk_crl_cut20[i].crl_pilots_off_30;
  2127. }
  2128. } else if (modcod <= STV090x_8PSK_910) {
  2129. if (pilots) {
  2130. if (state->srate <= 3000000)
  2131. aclc = car_loop[i].crl_pilots_on_2;
  2132. else if (state->srate <= 7000000)
  2133. aclc = car_loop[i].crl_pilots_on_5;
  2134. else if (state->srate <= 15000000)
  2135. aclc = car_loop[i].crl_pilots_on_10;
  2136. else if (state->srate <= 25000000)
  2137. aclc = car_loop[i].crl_pilots_on_20;
  2138. else
  2139. aclc = car_loop[i].crl_pilots_on_30;
  2140. } else {
  2141. if (state->srate <= 3000000)
  2142. aclc = car_loop[i].crl_pilots_off_2;
  2143. else if (state->srate <= 7000000)
  2144. aclc = car_loop[i].crl_pilots_off_5;
  2145. else if (state->srate <= 15000000)
  2146. aclc = car_loop[i].crl_pilots_off_10;
  2147. else if (state->srate <= 25000000)
  2148. aclc = car_loop[i].crl_pilots_off_20;
  2149. else
  2150. aclc = car_loop[i].crl_pilots_off_30;
  2151. }
  2152. } else { /* 16APSK and 32APSK */
  2153. if (state->srate <= 3000000)
  2154. aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_2;
  2155. else if (state->srate <= 7000000)
  2156. aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_5;
  2157. else if (state->srate <= 15000000)
  2158. aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_10;
  2159. else if (state->srate <= 25000000)
  2160. aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_20;
  2161. else
  2162. aclc = stv090x_s2_apsk_crl_cut20[i].crl_pilots_on_30;
  2163. }
  2164. return aclc;
  2165. }
  2166. static u8 stv090x_optimize_carloop_short(struct stv090x_state *state)
  2167. {
  2168. s32 index = 0;
  2169. u8 aclc = 0x0b;
  2170. switch (state->modulation) {
  2171. case STV090x_QPSK:
  2172. default:
  2173. index = 0;
  2174. break;
  2175. case STV090x_8PSK:
  2176. index = 1;
  2177. break;
  2178. case STV090x_16APSK:
  2179. index = 2;
  2180. break;
  2181. case STV090x_32APSK:
  2182. index = 3;
  2183. break;
  2184. }
  2185. switch (state->dev_ver) {
  2186. case 0x20:
  2187. if (state->srate <= 3000000)
  2188. aclc = stv090x_s2_short_crl[index].crl_cut20_2;
  2189. else if (state->srate <= 7000000)
  2190. aclc = stv090x_s2_short_crl[index].crl_cut20_5;
  2191. else if (state->srate <= 15000000)
  2192. aclc = stv090x_s2_short_crl[index].crl_cut20_10;
  2193. else if (state->srate <= 25000000)
  2194. aclc = stv090x_s2_short_crl[index].crl_cut20_20;
  2195. else
  2196. aclc = stv090x_s2_short_crl[index].crl_cut20_30;
  2197. break;
  2198. case 0x12:
  2199. default:
  2200. if (state->srate <= 3000000)
  2201. aclc = stv090x_s2_short_crl[index].crl_cut12_2;
  2202. else if (state->srate <= 7000000)
  2203. aclc = stv090x_s2_short_crl[index].crl_cut12_5;
  2204. else if (state->srate <= 15000000)
  2205. aclc = stv090x_s2_short_crl[index].crl_cut12_10;
  2206. else if (state->srate <= 25000000)
  2207. aclc = stv090x_s2_short_crl[index].crl_cut12_20;
  2208. else
  2209. aclc = stv090x_s2_short_crl[index].crl_cut12_30;
  2210. break;
  2211. }
  2212. return aclc;
  2213. }
  2214. static int stv090x_optimize_track(struct stv090x_state *state)
  2215. {
  2216. struct dvb_frontend *fe = &state->frontend;
  2217. enum stv090x_rolloff rolloff;
  2218. enum stv090x_modcod modcod;
  2219. s32 srate, pilots, aclc, f_1, f_0, i = 0, blind_tune = 0;
  2220. u32 reg;
  2221. srate = stv090x_get_srate(state, state->mclk);
  2222. srate += stv090x_get_tmgoffst(state, srate);
  2223. switch (state->delsys) {
  2224. case STV090x_DVBS1:
  2225. case STV090x_DSS:
  2226. if (state->algo == STV090x_SEARCH_AUTO) {
  2227. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  2228. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  2229. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
  2230. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  2231. goto err;
  2232. }
  2233. reg = STV090x_READ_DEMOD(state, DEMOD);
  2234. STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
  2235. STV090x_SETFIELD_Px(reg, MANUAL_ROLLOFF_FIELD, 0x01);
  2236. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2237. goto err;
  2238. if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
  2239. goto err;
  2240. break;
  2241. case STV090x_DVBS2:
  2242. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  2243. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  2244. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
  2245. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  2246. goto err;
  2247. if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0)
  2248. goto err;
  2249. if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0)
  2250. goto err;
  2251. if (state->frame_len == STV090x_LONG_FRAME) {
  2252. reg = STV090x_READ_DEMOD(state, DMDMODCOD);
  2253. modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
  2254. pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
  2255. aclc = stv090x_optimize_carloop(state, modcod, pilots);
  2256. if (modcod <= STV090x_QPSK_910) {
  2257. STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc);
  2258. } else if (modcod <= STV090x_8PSK_910) {
  2259. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2260. goto err;
  2261. if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
  2262. goto err;
  2263. }
  2264. if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) {
  2265. if (modcod <= STV090x_16APSK_910) {
  2266. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2267. goto err;
  2268. if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
  2269. goto err;
  2270. } else {
  2271. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2272. goto err;
  2273. if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
  2274. goto err;
  2275. }
  2276. }
  2277. } else {
  2278. /*Carrier loop setting for short frame*/
  2279. aclc = stv090x_optimize_carloop_short(state);
  2280. if (state->modulation == STV090x_QPSK) {
  2281. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0)
  2282. goto err;
  2283. } else if (state->modulation == STV090x_8PSK) {
  2284. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2285. goto err;
  2286. if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
  2287. goto err;
  2288. } else if (state->modulation == STV090x_16APSK) {
  2289. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2290. goto err;
  2291. if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
  2292. goto err;
  2293. } else if (state->modulation == STV090x_32APSK) {
  2294. if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
  2295. goto err;
  2296. if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
  2297. goto err;
  2298. }
  2299. }
  2300. if (state->dev_ver <= 0x11) {
  2301. if (state->demod_mode != STV090x_SINGLE)
  2302. stv090x_activate_modcod(state); /* link to LDPC after demod LOCK */
  2303. }
  2304. STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67); /* PER */
  2305. break;
  2306. case STV090x_UNKNOWN:
  2307. default:
  2308. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  2309. STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
  2310. STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
  2311. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  2312. goto err;
  2313. break;
  2314. }
  2315. f_1 = STV090x_READ_DEMOD(state, CFR2);
  2316. f_0 = STV090x_READ_DEMOD(state, CFR1);
  2317. reg = STV090x_READ_DEMOD(state, TMGOBS);
  2318. rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
  2319. if (state->algo == STV090x_BLIND_SEARCH) {
  2320. STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00);
  2321. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  2322. STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00);
  2323. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
  2324. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  2325. goto err;
  2326. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x01) < 0)
  2327. goto err;
  2328. stv090x_set_srate(state, srate);
  2329. stv090x_set_max_srate(state, state->mclk, srate);
  2330. stv090x_set_min_srate(state, state->mclk, srate);
  2331. blind_tune = 1;
  2332. }
  2333. if (state->dev_ver >= 0x20) {
  2334. if ((state->search_mode == STV090x_SEARCH_DVBS1) ||
  2335. (state->search_mode == STV090x_SEARCH_DSS) ||
  2336. (state->search_mode == STV090x_SEARCH_AUTO)) {
  2337. if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0)
  2338. goto err;
  2339. if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0)
  2340. goto err;
  2341. }
  2342. }
  2343. if (state->dev_ver < 0x20) {
  2344. if (STV090x_WRITE_DEMOD(state, CARHDR, 0x08) < 0)
  2345. goto err;
  2346. }
  2347. if (state->dev_ver == 0x10) {
  2348. if (STV090x_WRITE_DEMOD(state, CORRELEXP, 0x0a) < 0)
  2349. goto err;
  2350. }
  2351. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
  2352. goto err;
  2353. if ((state->dev_ver >= 0x20) || (blind_tune == 1) || (state->srate < 10000000)) {
  2354. if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
  2355. goto err;
  2356. if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
  2357. goto err;
  2358. state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000;
  2359. if ((state->dev_ver >= 0x20) || (blind_tune == 1)) {
  2360. if (state->algo != STV090x_WARM_SEARCH) {
  2361. stv090x_i2c_gate_ctrl(fe, 1);
  2362. if (state->config->tuner_set_bandwidth)
  2363. state->config->tuner_set_bandwidth(fe, state->tuner_bw);
  2364. stv090x_i2c_gate_ctrl(fe, 0);
  2365. }
  2366. }
  2367. if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000))
  2368. msleep(50); /* blind search: wait 50ms for SR stabilization */
  2369. else
  2370. msleep(5);
  2371. stv090x_get_lock_tmg(state);
  2372. if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) {
  2373. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  2374. goto err;
  2375. if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
  2376. goto err;
  2377. if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
  2378. goto err;
  2379. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
  2380. goto err;
  2381. i = 0;
  2382. while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) {
  2383. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
  2384. goto err;
  2385. if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
  2386. goto err;
  2387. if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
  2388. goto err;
  2389. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
  2390. goto err;
  2391. i++;
  2392. }
  2393. }
  2394. }
  2395. if (state->dev_ver >= 0x20) {
  2396. if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
  2397. goto err;
  2398. }
  2399. if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS))
  2400. stv090x_set_vit_thtracq(state);
  2401. return 0;
  2402. err:
  2403. dprintk(FE_ERROR, 1, "I/O error");
  2404. return -1;
  2405. }
  2406. static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout)
  2407. {
  2408. s32 timer = 0, lock = 0, stat;
  2409. u32 reg;
  2410. while ((timer < timeout) && (!lock)) {
  2411. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  2412. stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
  2413. switch (stat) {
  2414. case 0: /* searching */
  2415. case 1: /* first PLH detected */
  2416. default:
  2417. lock = 0;
  2418. break;
  2419. case 2: /* DVB-S2 mode */
  2420. reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
  2421. lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD);
  2422. break;
  2423. case 3: /* DVB-S1/legacy mode */
  2424. reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
  2425. lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD);
  2426. break;
  2427. }
  2428. if (!lock) {
  2429. msleep(10);
  2430. timer += 10;
  2431. }
  2432. }
  2433. return lock;
  2434. }
  2435. static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec)
  2436. {
  2437. u32 reg;
  2438. s32 timer = 0;
  2439. int lock;
  2440. lock = stv090x_get_dmdlock(state, timeout_dmd);
  2441. if (lock)
  2442. lock = stv090x_get_feclock(state, timeout_fec);
  2443. if (lock) {
  2444. lock = 0;
  2445. while ((timer < timeout_fec) && (!lock)) {
  2446. reg = STV090x_READ_DEMOD(state, TSSTATUS);
  2447. lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD);
  2448. msleep(1);
  2449. timer++;
  2450. }
  2451. }
  2452. return lock;
  2453. }
  2454. static int stv090x_set_s2rolloff(struct stv090x_state *state)
  2455. {
  2456. s32 rolloff;
  2457. u32 reg;
  2458. if (state->dev_ver == 0x10) {
  2459. reg = STV090x_READ_DEMOD(state, DEMOD);
  2460. STV090x_SETFIELD_Px(reg, MANUAL_ROLLOFF_FIELD, 0x01);
  2461. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2462. goto err;
  2463. rolloff = STV090x_READ_DEMOD(state, MATSTR1) & 0x03;
  2464. reg = STV090x_READ_DEMOD(state, DEMOD);
  2465. STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, reg);
  2466. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2467. goto err;
  2468. } else {
  2469. reg = STV090x_READ_DEMOD(state, DEMOD);
  2470. STV090x_SETFIELD_Px(reg, MANUAL_ROLLOFF_FIELD, 0x00);
  2471. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2472. goto err;
  2473. }
  2474. return 0;
  2475. err:
  2476. dprintk(FE_ERROR, 1, "I/O error");
  2477. return -1;
  2478. }
  2479. static enum stv090x_signal_state stv090x_acq_fixs1(struct stv090x_state *state)
  2480. {
  2481. s32 srate, f_1, f_2;
  2482. enum stv090x_signal_state signal_state = STV090x_NODATA;
  2483. u32 reg;
  2484. int lock;
  2485. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  2486. if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) { /* DVB-S mode */
  2487. srate = stv090x_get_srate(state, state->mclk);
  2488. srate += stv090x_get_tmgoffst(state, state->srate);
  2489. if (state->algo == STV090x_BLIND_SEARCH)
  2490. stv090x_set_srate(state, state->srate);
  2491. stv090x_get_lock_tmg(state);
  2492. f_1 = STV090x_READ_DEMOD(state, CFR2);
  2493. f_2 = STV090x_READ_DEMOD(state, CFR1);
  2494. reg = STV090x_READ_DEMOD(state, DMDCFGMD);
  2495. STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
  2496. if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
  2497. goto err;
  2498. reg = STV090x_READ_DEMOD(state, DEMOD);
  2499. STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, STV090x_IQ_SWAP);
  2500. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2501. goto err;
  2502. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0) /* stop demod */
  2503. goto err;
  2504. if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
  2505. goto err;
  2506. if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_2) < 0)
  2507. goto err;
  2508. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* warm start trigger */
  2509. goto err;
  2510. if (stv090x_get_lock(state, state->DemodTimeout, state->FecTimeout)) {
  2511. lock = 1;
  2512. stv090x_get_sig_params(state);
  2513. stv090x_optimize_track(state);
  2514. } else {
  2515. reg = STV090x_READ_DEMOD(state, DEMOD);
  2516. STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, STV090x_IQ_NORMAL);
  2517. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2518. goto err;
  2519. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
  2520. goto err;
  2521. if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
  2522. goto err;
  2523. if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_2) < 0)
  2524. goto err;
  2525. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* warm start trigger */
  2526. goto err;
  2527. if (stv090x_get_lock(state, state->DemodTimeout, state->FecTimeout)) {
  2528. lock = 1;
  2529. signal_state = stv090x_get_sig_params(state);
  2530. stv090x_optimize_track(state);
  2531. }
  2532. }
  2533. } else {
  2534. lock = 0;
  2535. }
  2536. return signal_state;
  2537. err:
  2538. dprintk(FE_ERROR, 1, "I/O error");
  2539. return -1;
  2540. }
  2541. static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
  2542. {
  2543. struct dvb_frontend *fe = &state->frontend;
  2544. enum stv090x_signal_state signal_state = STV090x_NOCARRIER;
  2545. u32 reg;
  2546. s32 timeout_dmd = 500, timeout_fec = 50;
  2547. int lock = 0, low_sr, no_signal = 0;
  2548. reg = STV090x_READ_DEMOD(state, TSCFGH);
  2549. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */
  2550. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2551. goto err;
  2552. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */
  2553. goto err;
  2554. if (state->dev_ver >= 0x20) {
  2555. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0) /* cut 2.0 */
  2556. goto err;
  2557. } else {
  2558. if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x88) < 0) /* cut 1.x */
  2559. goto err;
  2560. }
  2561. stv090x_get_lock_tmg(state);
  2562. if (state->algo == STV090x_BLIND_SEARCH) {
  2563. state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */
  2564. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x00) < 0) /* wider srate scan */
  2565. goto err;
  2566. stv090x_set_srate(state, 1000000); /* inital srate = 1Msps */
  2567. } else {
  2568. /* known srate */
  2569. if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
  2570. goto err;
  2571. if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
  2572. goto err;
  2573. if (state->srate >= 10000000) {
  2574. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0) /* High SR */
  2575. goto err;
  2576. } else {
  2577. if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x60) < 0) /* Low SR */
  2578. goto err;
  2579. }
  2580. if (state->dev_ver >= 0x20) {
  2581. if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0)
  2582. goto err;
  2583. if (state->algo == STV090x_COLD_SEARCH)
  2584. state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 1000000)) / 10;
  2585. else if (state->algo == STV090x_WARM_SEARCH)
  2586. state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000;
  2587. } else {
  2588. if (STV090x_WRITE_DEMOD(state, KREFTMG, 0xc1) < 0)
  2589. goto err;
  2590. state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10;
  2591. }
  2592. if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0x01) < 0) /* narrow srate scan */
  2593. goto err;
  2594. stv090x_set_srate(state, state->srate);
  2595. stv090x_set_max_srate(state, state->mclk, state->srate);
  2596. stv090x_set_min_srate(state, state->mclk, state->srate);
  2597. if (state->srate >= 10000000)
  2598. low_sr = 1;
  2599. }
  2600. /* Setup tuner */
  2601. stv090x_i2c_gate_ctrl(fe, 1);
  2602. if (state->config->tuner_set_bbgain)
  2603. state->config->tuner_set_bbgain(fe, 10); /* 10dB */
  2604. if (state->config->tuner_set_frequency)
  2605. state->config->tuner_set_frequency(fe, state->frequency);
  2606. if (state->config->tuner_set_bandwidth)
  2607. state->config->tuner_set_bandwidth(fe, state->tuner_bw);
  2608. stv090x_i2c_gate_ctrl(fe, 0);
  2609. msleep(50);
  2610. stv090x_i2c_gate_ctrl(fe, 1);
  2611. if (state->config->tuner_get_status)
  2612. state->config->tuner_get_status(fe, &reg);
  2613. if (reg)
  2614. dprintk(FE_DEBUG, 1, "Tuner phase locked");
  2615. else
  2616. dprintk(FE_DEBUG, 1, "Tuner unlocked");
  2617. stv090x_i2c_gate_ctrl(fe, 0);
  2618. reg = STV090x_READ_DEMOD(state, DEMOD);
  2619. STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion);
  2620. STV090x_SETFIELD_Px(reg, MANUAL_ROLLOFF_FIELD, 1);
  2621. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  2622. goto err;
  2623. stv090x_delivery_search(state);
  2624. if (state->algo == STV090x_BLIND_SEARCH)
  2625. stv090x_start_search(state);
  2626. if (state->dev_ver == 0x12) {
  2627. reg = STV090x_READ_DEMOD(state, TSCFGH);
  2628. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
  2629. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2630. goto err;
  2631. msleep(3);
  2632. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
  2633. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2634. goto err;
  2635. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
  2636. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2637. goto err;
  2638. }
  2639. if (state->algo == STV090x_BLIND_SEARCH)
  2640. lock = stv090x_blind_search(state);
  2641. else if (state->algo == STV090x_COLD_SEARCH)
  2642. lock = stv090x_get_coldlock(state, timeout_dmd);
  2643. else if (state->algo == STV090x_WARM_SEARCH)
  2644. lock = stv090x_get_dmdlock(state, timeout_dmd);
  2645. if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) {
  2646. if (!low_sr) {
  2647. if (stv090x_chk_tmg(state))
  2648. lock = stv090x_sw_algo(state);
  2649. }
  2650. }
  2651. if (lock)
  2652. signal_state = stv090x_get_sig_params(state);
  2653. if ((lock) && (signal_state == STV090x_RANGEOK)) { /* signal within Range */
  2654. stv090x_optimize_track(state);
  2655. if (state->dev_ver <= 0x11) { /*workaround for dual DVBS1 cut 1.1 and 1.0 only*/
  2656. if (stv090x_get_std(state) == STV090x_DVBS1) {
  2657. msleep(20);
  2658. reg = STV090x_READ_DEMOD(state, TSCFGH);
  2659. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
  2660. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2661. goto err;
  2662. } else {
  2663. reg = STV090x_READ_DEMOD(state, TSCFGH);
  2664. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
  2665. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2666. goto err;
  2667. msleep(3);
  2668. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
  2669. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2670. goto err;
  2671. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
  2672. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2673. goto err;
  2674. }
  2675. } else if (state->dev_ver == 0x20) { /*cut 2.0 :release TS reset after demod lock and TrackingOptimization*/
  2676. reg = STV090x_READ_DEMOD(state, TSCFGH);
  2677. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
  2678. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2679. goto err;
  2680. msleep(3);
  2681. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
  2682. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2683. goto err;
  2684. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
  2685. if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
  2686. goto err;
  2687. }
  2688. if (stv090x_get_lock(state, timeout_fec, timeout_fec)) {
  2689. lock = 1;
  2690. if (state->delsys == STV090x_DVBS2) {
  2691. stv090x_set_s2rolloff(state);
  2692. if (STV090x_WRITE_DEMOD(state, PDELCTRL2, 0x40) < 0)
  2693. goto err;
  2694. if (STV090x_WRITE_DEMOD(state, PDELCTRL2, 0x00) < 0) /* RESET counter */
  2695. goto err;
  2696. if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67) < 0) /* PER */
  2697. goto err;
  2698. } else {
  2699. if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
  2700. goto err;
  2701. }
  2702. if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0)
  2703. goto err;
  2704. if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
  2705. goto err;
  2706. } else {
  2707. lock = 0;
  2708. signal_state = STV090x_NODATA;
  2709. no_signal = stv090x_chk_signal(state);
  2710. }
  2711. }
  2712. if ((signal_state == STV090x_NODATA) && (!no_signal)) {
  2713. if (state->dev_ver <= 0x11) {
  2714. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  2715. if (((STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD)) == STV090x_DVBS2) && (state->inversion == INVERSION_AUTO))
  2716. signal_state = stv090x_acq_fixs1(state);
  2717. }
  2718. }
  2719. return signal_state;
  2720. err:
  2721. dprintk(FE_ERROR, 1, "I/O error");
  2722. return -1;
  2723. }
  2724. static enum dvbfe_search stv090x_search(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
  2725. {
  2726. struct stv090x_state *state = fe->demodulator_priv;
  2727. struct dtv_frontend_properties *props = &fe->dtv_property_cache;
  2728. state->delsys = props->delivery_system;
  2729. state->frequency = p->frequency;
  2730. state->srate = p->u.qpsk.symbol_rate;
  2731. if (!stv090x_algo(state)) {
  2732. dprintk(FE_DEBUG, 1, "Search success!");
  2733. return DVBFE_ALGO_SEARCH_SUCCESS;
  2734. } else {
  2735. dprintk(FE_DEBUG, 1, "Search failed!");
  2736. return DVBFE_ALGO_SEARCH_FAILED;
  2737. }
  2738. return DVBFE_ALGO_SEARCH_ERROR;
  2739. }
  2740. /* FIXME! */
  2741. static int stv090x_read_status(struct dvb_frontend *fe, enum fe_status *status)
  2742. {
  2743. struct stv090x_state *state = fe->demodulator_priv;
  2744. u32 reg;
  2745. u8 search_state;
  2746. int locked = 0;
  2747. reg = STV090x_READ_DEMOD(state, DMDSTATE);
  2748. search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
  2749. switch (search_state) {
  2750. case 0: /* searching */
  2751. case 1: /* first PLH detected */
  2752. default:
  2753. dprintk(FE_DEBUG, 1, "Status: Unlocked (Searching ..)");
  2754. locked = 0;
  2755. break;
  2756. case 2: /* DVB-S2 mode */
  2757. dprintk(FE_DEBUG, 1, "Delivery system: DVB-S2");
  2758. reg = STV090x_READ_DEMOD(state, DSTATUS);
  2759. if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
  2760. reg = STV090x_READ_DEMOD(state, TSSTATUS);
  2761. if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
  2762. locked = 1;
  2763. *status = FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
  2764. }
  2765. }
  2766. break;
  2767. case 3: /* DVB-S1/legacy mode */
  2768. dprintk(FE_DEBUG, 1, "Delivery system: DVB-S");
  2769. reg = STV090x_READ_DEMOD(state, DSTATUS);
  2770. if (STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD)) {
  2771. reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
  2772. if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) {
  2773. reg = STV090x_READ_DEMOD(state, TSSTATUS);
  2774. if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD)) {
  2775. locked = 1;
  2776. *status = FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
  2777. }
  2778. }
  2779. }
  2780. break;
  2781. }
  2782. return locked;
  2783. }
  2784. static int stv090x_read_per(struct dvb_frontend *fe, u32 *per)
  2785. {
  2786. struct stv090x_state *state = fe->demodulator_priv;
  2787. s32 count_4, count_3, count_2, count_1, count_0, count;
  2788. u32 reg, h, m, l;
  2789. enum fe_status status;
  2790. if (!stv090x_read_status(fe, &status)) {
  2791. *per = 1 << 23; /* Max PER */
  2792. } else {
  2793. /* Counter 2 */
  2794. reg = STV090x_READ_DEMOD(state, ERRCNT22);
  2795. h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD);
  2796. reg = STV090x_READ_DEMOD(state, ERRCNT21);
  2797. m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD);
  2798. reg = STV090x_READ_DEMOD(state, ERRCNT20);
  2799. l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD);
  2800. *per = ((h << 16) | (m << 8) | l);
  2801. count_4 = STV090x_READ_DEMOD(state, FBERCPT4);
  2802. count_3 = STV090x_READ_DEMOD(state, FBERCPT3);
  2803. count_2 = STV090x_READ_DEMOD(state, FBERCPT2);
  2804. count_1 = STV090x_READ_DEMOD(state, FBERCPT1);
  2805. count_0 = STV090x_READ_DEMOD(state, FBERCPT0);
  2806. if ((!count_4) && (!count_3)) {
  2807. count = (count_2 & 0xff) << 16;
  2808. count |= (count_1 & 0xff) << 8;
  2809. count |= count_0 & 0xff;
  2810. } else {
  2811. count = 1 << 24;
  2812. }
  2813. if (count == 0)
  2814. *per = 1;
  2815. }
  2816. if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0)
  2817. goto err;
  2818. if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
  2819. goto err;
  2820. return 0;
  2821. err:
  2822. dprintk(FE_ERROR, 1, "I/O error");
  2823. return -1;
  2824. }
  2825. static int stv090x_table_lookup(const struct stv090x_tab *tab, int max, int val)
  2826. {
  2827. int res = 0;
  2828. int min = 0, med;
  2829. if (val < tab[min].read)
  2830. res = tab[min].real;
  2831. else if (val >= tab[max].read)
  2832. res = tab[max].real;
  2833. else {
  2834. while ((max - min) > 1) {
  2835. med = (max + min) / 2;
  2836. if (val >= tab[min].read && val < tab[med].read)
  2837. max = med;
  2838. else
  2839. min = med;
  2840. }
  2841. res = ((val - tab[min].read) *
  2842. (tab[max].real - tab[min].real) /
  2843. (tab[max].read - tab[min].read)) +
  2844. tab[min].real;
  2845. }
  2846. return res;
  2847. }
  2848. static int stv090x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
  2849. {
  2850. struct stv090x_state *state = fe->demodulator_priv;
  2851. u32 reg;
  2852. s32 agc;
  2853. reg = STV090x_READ_DEMOD(state, AGCIQIN1);
  2854. agc = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
  2855. *strength = stv090x_table_lookup(stv090x_rf_tab, ARRAY_SIZE(stv090x_rf_tab) - 1, agc);
  2856. if (agc > stv090x_rf_tab[0].read)
  2857. *strength = 5;
  2858. else if (agc < stv090x_rf_tab[ARRAY_SIZE(stv090x_rf_tab) - 1].read)
  2859. *strength = -100;
  2860. return 0;
  2861. }
  2862. static int stv090x_read_cnr(struct dvb_frontend *fe, u16 *cnr)
  2863. {
  2864. struct stv090x_state *state = fe->demodulator_priv;
  2865. u32 reg_0, reg_1, reg, i;
  2866. s32 val_0, val_1, val = 0;
  2867. u8 lock_f;
  2868. switch (state->delsys) {
  2869. case STV090x_DVBS2:
  2870. reg = STV090x_READ_DEMOD(state, DSTATUS);
  2871. lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
  2872. if (lock_f) {
  2873. msleep(5);
  2874. for (i = 0; i < 16; i++) {
  2875. reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1);
  2876. val_1 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
  2877. reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0);
  2878. val_0 = STV090x_GETFIELD_Px(reg_1, NOSPLHT_NORMED_FIELD);
  2879. val += MAKEWORD16(val_1, val_0);
  2880. msleep(1);
  2881. }
  2882. val /= 16;
  2883. *cnr = stv090x_table_lookup(stv090x_s2cn_tab, ARRAY_SIZE(stv090x_s2cn_tab) - 1, val);
  2884. if (val < stv090x_s2cn_tab[ARRAY_SIZE(stv090x_s2cn_tab) - 1].read)
  2885. *cnr = 1000;
  2886. }
  2887. break;
  2888. case STV090x_DVBS1:
  2889. case STV090x_DSS:
  2890. reg = STV090x_READ_DEMOD(state, DSTATUS);
  2891. lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
  2892. if (lock_f) {
  2893. msleep(5);
  2894. for (i = 0; i < 16; i++) {
  2895. reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1);
  2896. val_1 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
  2897. reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0);
  2898. val_0 = STV090x_GETFIELD_Px(reg_1, NOSDATAT_UNNORMED_FIELD);
  2899. val += MAKEWORD16(val_1, val_0);
  2900. msleep(1);
  2901. }
  2902. val /= 16;
  2903. *cnr = stv090x_table_lookup(stv090x_s1cn_tab, ARRAY_SIZE(stv090x_s1cn_tab) - 1, val);
  2904. if (val < stv090x_s2cn_tab[ARRAY_SIZE(stv090x_s1cn_tab) - 1].read)
  2905. *cnr = 1000;
  2906. }
  2907. break;
  2908. default:
  2909. break;
  2910. }
  2911. return 0;
  2912. }
  2913. static int stv090x_set_tone(struct dvb_frontend *fe, fe_sec_tone_mode_t tone)
  2914. {
  2915. struct stv090x_state *state = fe->demodulator_priv;
  2916. u32 reg;
  2917. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  2918. switch (tone) {
  2919. case SEC_TONE_ON:
  2920. STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
  2921. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
  2922. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  2923. goto err;
  2924. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
  2925. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  2926. goto err;
  2927. break;
  2928. case SEC_TONE_OFF:
  2929. STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
  2930. STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
  2931. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  2932. goto err;
  2933. break;
  2934. default:
  2935. return -EINVAL;
  2936. }
  2937. return 0;
  2938. err:
  2939. dprintk(FE_ERROR, 1, "I/O error");
  2940. return -1;
  2941. }
  2942. static enum dvbfe_algo stv090x_frontend_algo(struct dvb_frontend *fe)
  2943. {
  2944. return DVBFE_ALGO_CUSTOM;
  2945. }
  2946. static int stv090x_send_diseqc_msg(struct dvb_frontend *fe, struct dvb_diseqc_master_cmd *cmd)
  2947. {
  2948. struct stv090x_state *state = fe->demodulator_priv;
  2949. u32 reg, idle = 0, fifo_full = 1;
  2950. int i;
  2951. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  2952. STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
  2953. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  2954. goto err;
  2955. for (i = 0; i < cmd->msg_len; i++) {
  2956. while (fifo_full) {
  2957. reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
  2958. fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
  2959. }
  2960. if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0)
  2961. goto err;
  2962. i++;
  2963. }
  2964. reg = STV090x_READ_DEMOD(state, DISTXCTL);
  2965. STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
  2966. if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
  2967. goto err;
  2968. i = 0;
  2969. while ((!idle) && (i < 10)) {
  2970. reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
  2971. idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
  2972. msleep(10);
  2973. i++;
  2974. }
  2975. return 0;
  2976. err:
  2977. dprintk(FE_ERROR, 1, "I/O error");
  2978. return -1;
  2979. }
  2980. static int stv090x_recv_slave_reply(struct dvb_frontend *fe, struct dvb_diseqc_slave_reply *reply)
  2981. {
  2982. struct stv090x_state *state = fe->demodulator_priv;
  2983. u32 reg = 0, i = 0, rx_end = 0;
  2984. while ((rx_end != 1) && (i < 10)) {
  2985. msleep(10);
  2986. i++;
  2987. reg = STV090x_READ_DEMOD(state, DISRX_ST0);
  2988. rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD);
  2989. }
  2990. if (rx_end) {
  2991. reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD);
  2992. for (i = 0; i < reply->msg_len; i++)
  2993. reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA);
  2994. }
  2995. return 0;
  2996. }
  2997. static int stv090x_sleep(struct dvb_frontend *fe)
  2998. {
  2999. struct stv090x_state *state = fe->demodulator_priv;
  3000. u32 reg;
  3001. dprintk(FE_DEBUG, 1, "Set %s to sleep",
  3002. state->device == STV0900 ? "STV0900" : "STV0903");
  3003. reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
  3004. STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01);
  3005. if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
  3006. goto err;
  3007. return 0;
  3008. err:
  3009. dprintk(FE_ERROR, 1, "I/O error");
  3010. return -1;
  3011. }
  3012. static int stv090x_wakeup(struct dvb_frontend *fe)
  3013. {
  3014. struct stv090x_state *state = fe->demodulator_priv;
  3015. u32 reg;
  3016. dprintk(FE_DEBUG, 1, "Wake %s from standby",
  3017. state->device == STV0900 ? "STV0900" : "STV0903");
  3018. reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
  3019. STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00);
  3020. if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
  3021. goto err;
  3022. return 0;
  3023. err:
  3024. dprintk(FE_ERROR, 1, "I/O error");
  3025. return -1;
  3026. }
  3027. static void stv090x_release(struct dvb_frontend *fe)
  3028. {
  3029. struct stv090x_state *state = fe->demodulator_priv;
  3030. kfree(state);
  3031. }
  3032. static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode)
  3033. {
  3034. u32 reg;
  3035. switch (ldpc_mode) {
  3036. case STV090x_DUAL:
  3037. default:
  3038. reg = stv090x_read_reg(state, STV090x_GENCFG);
  3039. if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) {
  3040. /* follow LDPC default state */
  3041. if (stv090x_write_reg(state, STV090x_GENCFG, reg) < 0)
  3042. goto err;
  3043. state->demod_mode = STV090x_DUAL;
  3044. reg = stv090x_read_reg(state, STV090x_TSTRES0);
  3045. STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
  3046. if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
  3047. goto err;
  3048. STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
  3049. if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
  3050. goto err;
  3051. }
  3052. break;
  3053. case STV090x_SINGLE:
  3054. if (state->demod == STV090x_DEMODULATOR_1) {
  3055. if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */
  3056. goto err;
  3057. } else {
  3058. if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */
  3059. goto err;
  3060. }
  3061. reg = stv090x_read_reg(state, STV090x_TSTRES0);
  3062. STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
  3063. if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
  3064. goto err;
  3065. STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
  3066. if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
  3067. goto err;
  3068. reg = STV090x_READ_DEMOD(state, PDELCTRL1);
  3069. STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01);
  3070. if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
  3071. goto err;
  3072. STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00);
  3073. if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
  3074. goto err;
  3075. break;
  3076. }
  3077. return 0;
  3078. err:
  3079. dprintk(FE_ERROR, 1, "I/O error");
  3080. return -1;
  3081. }
  3082. /* return (Hz), clk in Hz*/
  3083. static u32 stv090x_get_mclk(struct stv090x_state *state)
  3084. {
  3085. const struct stv090x_config *config = state->config;
  3086. u32 div, reg;
  3087. u8 ratio;
  3088. div = stv090x_read_reg(state, STV090x_NCOARSE);
  3089. reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
  3090. ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6;
  3091. return (div + 1) * config->xtal / ratio; /* kHz */
  3092. }
  3093. static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk)
  3094. {
  3095. const struct stv090x_config *config = state->config;
  3096. u32 reg, div, clk_sel;
  3097. reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
  3098. clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6);
  3099. div = ((clk_sel * mclk) / config->xtal) - 1;
  3100. reg = stv090x_read_reg(state, STV090x_NCOARSE);
  3101. STV090x_SETFIELD(reg, M_DIV_FIELD, div);
  3102. if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0)
  3103. goto err;
  3104. state->mclk = stv090x_get_mclk(state);
  3105. return 0;
  3106. err:
  3107. dprintk(FE_ERROR, 1, "I/O error");
  3108. return -1;
  3109. }
  3110. static int stv090x_set_tspath(struct stv090x_state *state)
  3111. {
  3112. u32 reg;
  3113. if (state->dev_ver >= 0x20) {
  3114. switch (state->config->ts1_mode) {
  3115. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3116. case STV090x_TSMODE_DVBCI:
  3117. switch (state->config->ts2_mode) {
  3118. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3119. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3120. default:
  3121. stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
  3122. break;
  3123. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3124. case STV090x_TSMODE_DVBCI:
  3125. if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */
  3126. goto err;
  3127. reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
  3128. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
  3129. if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
  3130. goto err;
  3131. reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
  3132. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
  3133. if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
  3134. goto err;
  3135. if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
  3136. goto err;
  3137. if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
  3138. goto err;
  3139. break;
  3140. }
  3141. break;
  3142. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3143. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3144. default:
  3145. switch (state->config->ts2_mode) {
  3146. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3147. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3148. default:
  3149. if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
  3150. goto err;
  3151. break;
  3152. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3153. case STV090x_TSMODE_DVBCI:
  3154. if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0)
  3155. goto err;
  3156. break;
  3157. }
  3158. break;
  3159. }
  3160. } else {
  3161. switch (state->config->ts1_mode) {
  3162. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3163. case STV090x_TSMODE_DVBCI:
  3164. switch (state->config->ts2_mode) {
  3165. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3166. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3167. default:
  3168. break;
  3169. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3170. case STV090x_TSMODE_DVBCI:
  3171. reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
  3172. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
  3173. if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
  3174. goto err;
  3175. reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
  3176. STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0);
  3177. if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
  3178. goto err;
  3179. if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
  3180. goto err;
  3181. if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
  3182. goto err;
  3183. break;
  3184. }
  3185. break;
  3186. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3187. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3188. default:
  3189. switch (state->config->ts2_mode) {
  3190. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3191. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3192. default:
  3193. break;
  3194. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3195. case STV090x_TSMODE_DVBCI:
  3196. break;
  3197. }
  3198. break;
  3199. }
  3200. }
  3201. switch (state->config->ts1_mode) {
  3202. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3203. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3204. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
  3205. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
  3206. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3207. goto err;
  3208. break;
  3209. case STV090x_TSMODE_DVBCI:
  3210. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3211. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
  3212. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
  3213. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3214. goto err;
  3215. break;
  3216. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3217. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3218. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
  3219. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
  3220. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3221. goto err;
  3222. break;
  3223. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3224. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3225. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
  3226. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
  3227. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3228. goto err;
  3229. break;
  3230. default:
  3231. break;
  3232. }
  3233. switch (state->config->ts2_mode) {
  3234. case STV090x_TSMODE_PARALLEL_PUNCTURED:
  3235. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3236. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
  3237. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
  3238. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3239. goto err;
  3240. break;
  3241. case STV090x_TSMODE_DVBCI:
  3242. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3243. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
  3244. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
  3245. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3246. goto err;
  3247. break;
  3248. case STV090x_TSMODE_SERIAL_PUNCTURED:
  3249. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3250. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
  3251. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
  3252. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3253. goto err;
  3254. break;
  3255. case STV090x_TSMODE_SERIAL_CONTINUOUS:
  3256. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3257. STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
  3258. STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
  3259. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3260. goto err;
  3261. break;
  3262. default:
  3263. break;
  3264. }
  3265. reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
  3266. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
  3267. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3268. goto err;
  3269. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
  3270. if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
  3271. goto err;
  3272. reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
  3273. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
  3274. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3275. goto err;
  3276. STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
  3277. if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
  3278. goto err;
  3279. return 0;
  3280. err:
  3281. dprintk(FE_ERROR, 1, "I/O error");
  3282. return -1;
  3283. }
  3284. static int stv090x_init(struct dvb_frontend *fe)
  3285. {
  3286. struct stv090x_state *state = fe->demodulator_priv;
  3287. const struct stv090x_config *config = state->config;
  3288. u32 reg;
  3289. stv090x_ldpc_mode(state, state->demod_mode);
  3290. reg = STV090x_READ_DEMOD(state, TNRCFG2);
  3291. STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion);
  3292. if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0)
  3293. goto err;
  3294. reg = STV090x_READ_DEMOD(state, DEMOD);
  3295. STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
  3296. if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
  3297. goto err;
  3298. stv090x_i2c_gate_ctrl(fe, 1);
  3299. if (config->tuner_init)
  3300. config->tuner_init(fe);
  3301. stv090x_i2c_gate_ctrl(fe, 0);
  3302. stv090x_set_tspath(state);
  3303. return 0;
  3304. err:
  3305. dprintk(FE_ERROR, 1, "I/O error");
  3306. return -1;
  3307. }
  3308. static int stv090x_setup(struct dvb_frontend *fe)
  3309. {
  3310. struct stv090x_state *state = fe->demodulator_priv;
  3311. const struct stv090x_config *config = state->config;
  3312. const struct stv090x_reg *stv090x_initval = NULL;
  3313. const struct stv090x_reg *stv090x_cut20_val = NULL;
  3314. unsigned long t1_size = 0, t2_size = 0;
  3315. u32 reg = 0;
  3316. int i;
  3317. if (state->device == STV0900) {
  3318. dprintk(FE_DEBUG, 1, "Initializing STV0900");
  3319. stv090x_initval = stv0900_initval;
  3320. t1_size = ARRAY_SIZE(stv0900_initval);
  3321. stv090x_cut20_val = stv0900_cut20_val;
  3322. t2_size = ARRAY_SIZE(stv0900_cut20_val);
  3323. } else if (state->device == STV0903) {
  3324. dprintk(FE_DEBUG, 1, "Initializing STV0903");
  3325. stv090x_initval = stv0903_initval;
  3326. t1_size = ARRAY_SIZE(stv0903_initval);
  3327. stv090x_cut20_val = stv0903_cut20_val;
  3328. t2_size = ARRAY_SIZE(stv0903_cut20_val);
  3329. }
  3330. /* STV090x init */
  3331. if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Stop Demod */
  3332. goto err;
  3333. msleep(5);
  3334. if (STV090x_WRITE_DEMOD(state, TNRCFG, 0x6c) < 0) /* check register ! (No Tuner Mode) */
  3335. goto err;
  3336. STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level);
  3337. if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0) /* repeater OFF */
  3338. goto err;
  3339. if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */
  3340. goto err;
  3341. msleep(5);
  3342. if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */
  3343. goto err;
  3344. if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */
  3345. goto err;
  3346. msleep(5);
  3347. /* write initval */
  3348. for (i = 0; i < t1_size; i++) {
  3349. dprintk(FE_DEBUG, 1, "Setting up initial values");
  3350. if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0)
  3351. goto err;
  3352. }
  3353. if (state->dev_ver >= 0x20) {
  3354. if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
  3355. goto err;
  3356. /* write cut20_val*/
  3357. dprintk(FE_DEBUG, 1, "Setting up Cut 2.0 initial values");
  3358. for (i = 0; i < t2_size; i++) {
  3359. if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0)
  3360. goto err;
  3361. }
  3362. }
  3363. if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0)
  3364. goto err;
  3365. if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0)
  3366. goto err;
  3367. stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */
  3368. msleep(5);
  3369. if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0)
  3370. goto err;
  3371. stv090x_get_mclk(state);
  3372. return 0;
  3373. err:
  3374. dprintk(FE_ERROR, 1, "I/O error");
  3375. return -1;
  3376. }
  3377. static struct dvb_frontend_ops stv090x_ops = {
  3378. .info = {
  3379. .name = "STV090x Multistandard",
  3380. },
  3381. .release = stv090x_release,
  3382. .init = stv090x_init,
  3383. .sleep = stv090x_sleep,
  3384. .get_frontend_algo = stv090x_frontend_algo,
  3385. .i2c_gate_ctrl = stv090x_i2c_gate_ctrl,
  3386. .diseqc_send_master_cmd = stv090x_send_diseqc_msg,
  3387. .diseqc_recv_slave_reply = stv090x_recv_slave_reply,
  3388. .set_tone = stv090x_set_tone,
  3389. .search = stv090x_search,
  3390. .read_status = stv090x_read_status,
  3391. .read_ber = stv090x_read_per,
  3392. .read_signal_strength = stv090x_read_signal_strength,
  3393. .read_snr = stv090x_read_cnr
  3394. };
  3395. struct dvb_frontend *stv090x_attach(const struct stv090x_config *config,
  3396. struct i2c_adapter *i2c,
  3397. enum stv090x_demodulator demod)
  3398. {
  3399. struct stv090x_state *state = NULL;
  3400. state = kzalloc(sizeof (struct stv090x_state), GFP_KERNEL);
  3401. if (state == NULL)
  3402. goto error;
  3403. state->verbose = &verbose;
  3404. state->config = config;
  3405. state->i2c = i2c;
  3406. state->frontend.ops = stv090x_ops;
  3407. state->frontend.demodulator_priv = state;
  3408. state->demod_mode = config->demod_mode; /* Single or Dual mode */
  3409. state->device = config->device;
  3410. state->rolloff = 35; /* default */
  3411. if (state->demod == STV090x_DEMODULATOR_0)
  3412. mutex_init(&demod_lock);
  3413. if (stv090x_sleep(&state->frontend) < 0) {
  3414. dprintk(FE_ERROR, 1, "Error putting device to sleep");
  3415. goto error;
  3416. }
  3417. if (stv090x_setup(&state->frontend) < 0) {
  3418. dprintk(FE_ERROR, 1, "Error setting up device");
  3419. goto error;
  3420. }
  3421. if (stv090x_wakeup(&state->frontend) < 0) {
  3422. dprintk(FE_ERROR, 1, "Error waking device");
  3423. goto error;
  3424. }
  3425. state->dev_ver = stv090x_read_reg(state, STV090x_MID);
  3426. dprintk(FE_ERROR, 1, "Attaching %s demodulator(%d) Cut=0x%02x\n",
  3427. state->device == STV0900 ? "STV0900" : "STV0903",
  3428. demod,
  3429. state->dev_ver);
  3430. return &state->frontend;
  3431. error:
  3432. kfree(state);
  3433. return NULL;
  3434. }
  3435. EXPORT_SYMBOL(stv090x_attach);
  3436. MODULE_PARM_DESC(verbose, "Set Verbosity level");
  3437. MODULE_AUTHOR("Manu Abraham");
  3438. MODULE_DESCRIPTION("STV090x Multi-Std Broadcast frontend");
  3439. MODULE_LICENSE("GPL");