nv04_display.h 3.0 KB

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  1. #ifndef __NV04_DISPLAY_H__
  2. #define __NV04_DISPLAY_H__
  3. enum nv04_fp_display_regs {
  4. FP_DISPLAY_END,
  5. FP_TOTAL,
  6. FP_CRTC,
  7. FP_SYNC_START,
  8. FP_SYNC_END,
  9. FP_VALID_START,
  10. FP_VALID_END
  11. };
  12. struct nv04_crtc_reg {
  13. unsigned char MiscOutReg;
  14. uint8_t CRTC[0xa0];
  15. uint8_t CR58[0x10];
  16. uint8_t Sequencer[5];
  17. uint8_t Graphics[9];
  18. uint8_t Attribute[21];
  19. unsigned char DAC[768];
  20. /* PCRTC regs */
  21. uint32_t fb_start;
  22. uint32_t crtc_cfg;
  23. uint32_t cursor_cfg;
  24. uint32_t gpio_ext;
  25. uint32_t crtc_830;
  26. uint32_t crtc_834;
  27. uint32_t crtc_850;
  28. uint32_t crtc_eng_ctrl;
  29. /* PRAMDAC regs */
  30. uint32_t nv10_cursync;
  31. struct nouveau_pll_vals pllvals;
  32. uint32_t ramdac_gen_ctrl;
  33. uint32_t ramdac_630;
  34. uint32_t ramdac_634;
  35. uint32_t tv_setup;
  36. uint32_t tv_vtotal;
  37. uint32_t tv_vskew;
  38. uint32_t tv_vsync_delay;
  39. uint32_t tv_htotal;
  40. uint32_t tv_hskew;
  41. uint32_t tv_hsync_delay;
  42. uint32_t tv_hsync_delay2;
  43. uint32_t fp_horiz_regs[7];
  44. uint32_t fp_vert_regs[7];
  45. uint32_t dither;
  46. uint32_t fp_control;
  47. uint32_t dither_regs[6];
  48. uint32_t fp_debug_0;
  49. uint32_t fp_debug_1;
  50. uint32_t fp_debug_2;
  51. uint32_t fp_margin_color;
  52. uint32_t ramdac_8c0;
  53. uint32_t ramdac_a20;
  54. uint32_t ramdac_a24;
  55. uint32_t ramdac_a34;
  56. uint32_t ctv_regs[38];
  57. };
  58. struct nv04_output_reg {
  59. uint32_t output;
  60. int head;
  61. };
  62. struct nv04_mode_state {
  63. struct nv04_crtc_reg crtc_reg[2];
  64. uint32_t pllsel;
  65. uint32_t sel_clk;
  66. };
  67. struct nv04_display {
  68. struct nv04_mode_state mode_reg;
  69. struct nv04_mode_state saved_reg;
  70. uint32_t saved_vga_font[4][16384];
  71. uint32_t dac_users[4];
  72. };
  73. static inline struct nv04_display *
  74. nv04_display(struct drm_device *dev)
  75. {
  76. struct drm_nouveau_private *dev_priv = dev->dev_private;
  77. return dev_priv->engine.display.priv;
  78. }
  79. /* nv04_display.c */
  80. int nv04_display_early_init(struct drm_device *);
  81. void nv04_display_late_takedown(struct drm_device *);
  82. int nv04_display_create(struct drm_device *);
  83. void nv04_display_destroy(struct drm_device *);
  84. int nv04_display_init(struct drm_device *);
  85. void nv04_display_fini(struct drm_device *);
  86. /* nv04_crtc.c */
  87. int nv04_crtc_create(struct drm_device *, int index);
  88. /* nv04_dac.c */
  89. int nv04_dac_create(struct drm_connector *, struct dcb_output *);
  90. uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
  91. int nv04_dac_output_offset(struct drm_encoder *encoder);
  92. void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
  93. bool nv04_dac_in_use(struct drm_encoder *encoder);
  94. /* nv04_dfp.c */
  95. int nv04_dfp_create(struct drm_connector *, struct dcb_output *);
  96. int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_output *dcbent);
  97. void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_output *dcbent,
  98. int head, bool dl);
  99. void nv04_dfp_disable(struct drm_device *dev, int head);
  100. void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
  101. /* nv04_tv.c */
  102. int nv04_tv_identify(struct drm_device *dev, int i2c_index);
  103. int nv04_tv_create(struct drm_connector *, struct dcb_output *);
  104. /* nv17_tv.c */
  105. int nv17_tv_create(struct drm_connector *, struct dcb_output *);
  106. #endif