cputable.c 29 KB

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  1. /*
  2. * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
  3. *
  4. * Modifications for ppc64:
  5. * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. */
  12. #include <linux/config.h>
  13. #include <linux/string.h>
  14. #include <linux/sched.h>
  15. #include <linux/threads.h>
  16. #include <linux/init.h>
  17. #include <linux/module.h>
  18. #include <asm/oprofile_impl.h>
  19. #include <asm/cputable.h>
  20. struct cpu_spec* cur_cpu_spec = NULL;
  21. EXPORT_SYMBOL(cur_cpu_spec);
  22. /* NOTE:
  23. * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's
  24. * the responsibility of the appropriate CPU save/restore functions to
  25. * eventually copy these settings over. Those save/restore aren't yet
  26. * part of the cputable though. That has to be fixed for both ppc32
  27. * and ppc64
  28. */
  29. #ifdef CONFIG_PPC64
  30. extern void __setup_cpu_power3(unsigned long offset, struct cpu_spec* spec);
  31. extern void __setup_cpu_power4(unsigned long offset, struct cpu_spec* spec);
  32. extern void __setup_cpu_be(unsigned long offset, struct cpu_spec* spec);
  33. #else
  34. extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec);
  35. extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec);
  36. extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec);
  37. extern void __setup_cpu_750cx(unsigned long offset, struct cpu_spec* spec);
  38. extern void __setup_cpu_750fx(unsigned long offset, struct cpu_spec* spec);
  39. extern void __setup_cpu_7400(unsigned long offset, struct cpu_spec* spec);
  40. extern void __setup_cpu_7410(unsigned long offset, struct cpu_spec* spec);
  41. extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec);
  42. #endif /* CONFIG_PPC32 */
  43. extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
  44. /* This table only contains "desktop" CPUs, it need to be filled with embedded
  45. * ones as well...
  46. */
  47. #define COMMON_USER (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
  48. PPC_FEATURE_HAS_MMU)
  49. #define COMMON_USER_PPC64 (COMMON_USER | PPC_FEATURE_64)
  50. #define COMMON_USER_POWER4 (COMMON_USER_PPC64 | PPC_FEATURE_POWER4)
  51. #define COMMON_USER_POWER5 (COMMON_USER_PPC64 | PPC_FEATURE_POWER5)
  52. #define COMMON_USER_POWER5_PLUS (COMMON_USER_PPC64 | PPC_FEATURE_POWER5_PLUS)
  53. /* We only set the spe features if the kernel was compiled with
  54. * spe support
  55. */
  56. #ifdef CONFIG_SPE
  57. #define PPC_FEATURE_SPE_COMP PPC_FEATURE_HAS_SPE
  58. #else
  59. #define PPC_FEATURE_SPE_COMP 0
  60. #endif
  61. struct cpu_spec cpu_specs[] = {
  62. #ifdef CONFIG_PPC64
  63. { /* Power3 */
  64. .pvr_mask = 0xffff0000,
  65. .pvr_value = 0x00400000,
  66. .cpu_name = "POWER3 (630)",
  67. .cpu_features = CPU_FTRS_POWER3,
  68. .cpu_user_features = COMMON_USER_PPC64,
  69. .icache_bsize = 128,
  70. .dcache_bsize = 128,
  71. .num_pmcs = 8,
  72. .cpu_setup = __setup_cpu_power3,
  73. #ifdef CONFIG_OPROFILE
  74. .oprofile_cpu_type = "ppc64/power3",
  75. .oprofile_model = &op_model_rs64,
  76. #endif
  77. },
  78. { /* Power3+ */
  79. .pvr_mask = 0xffff0000,
  80. .pvr_value = 0x00410000,
  81. .cpu_name = "POWER3 (630+)",
  82. .cpu_features = CPU_FTRS_POWER3,
  83. .cpu_user_features = COMMON_USER_PPC64,
  84. .icache_bsize = 128,
  85. .dcache_bsize = 128,
  86. .num_pmcs = 8,
  87. .cpu_setup = __setup_cpu_power3,
  88. #ifdef CONFIG_OPROFILE
  89. .oprofile_cpu_type = "ppc64/power3",
  90. .oprofile_model = &op_model_rs64,
  91. #endif
  92. },
  93. { /* Northstar */
  94. .pvr_mask = 0xffff0000,
  95. .pvr_value = 0x00330000,
  96. .cpu_name = "RS64-II (northstar)",
  97. .cpu_features = CPU_FTRS_RS64,
  98. .cpu_user_features = COMMON_USER_PPC64,
  99. .icache_bsize = 128,
  100. .dcache_bsize = 128,
  101. .num_pmcs = 8,
  102. .cpu_setup = __setup_cpu_power3,
  103. #ifdef CONFIG_OPROFILE
  104. .oprofile_cpu_type = "ppc64/rs64",
  105. .oprofile_model = &op_model_rs64,
  106. #endif
  107. },
  108. { /* Pulsar */
  109. .pvr_mask = 0xffff0000,
  110. .pvr_value = 0x00340000,
  111. .cpu_name = "RS64-III (pulsar)",
  112. .cpu_features = CPU_FTRS_RS64,
  113. .cpu_user_features = COMMON_USER_PPC64,
  114. .icache_bsize = 128,
  115. .dcache_bsize = 128,
  116. .num_pmcs = 8,
  117. .cpu_setup = __setup_cpu_power3,
  118. #ifdef CONFIG_OPROFILE
  119. .oprofile_cpu_type = "ppc64/rs64",
  120. .oprofile_model = &op_model_rs64,
  121. #endif
  122. },
  123. { /* I-star */
  124. .pvr_mask = 0xffff0000,
  125. .pvr_value = 0x00360000,
  126. .cpu_name = "RS64-III (icestar)",
  127. .cpu_features = CPU_FTRS_RS64,
  128. .cpu_user_features = COMMON_USER_PPC64,
  129. .icache_bsize = 128,
  130. .dcache_bsize = 128,
  131. .num_pmcs = 8,
  132. .cpu_setup = __setup_cpu_power3,
  133. #ifdef CONFIG_OPROFILE
  134. .oprofile_cpu_type = "ppc64/rs64",
  135. .oprofile_model = &op_model_rs64,
  136. #endif
  137. },
  138. { /* S-star */
  139. .pvr_mask = 0xffff0000,
  140. .pvr_value = 0x00370000,
  141. .cpu_name = "RS64-IV (sstar)",
  142. .cpu_features = CPU_FTRS_RS64,
  143. .cpu_user_features = COMMON_USER_PPC64,
  144. .icache_bsize = 128,
  145. .dcache_bsize = 128,
  146. .num_pmcs = 8,
  147. .cpu_setup = __setup_cpu_power3,
  148. #ifdef CONFIG_OPROFILE
  149. .oprofile_cpu_type = "ppc64/rs64",
  150. .oprofile_model = &op_model_rs64,
  151. #endif
  152. },
  153. { /* Power4 */
  154. .pvr_mask = 0xffff0000,
  155. .pvr_value = 0x00350000,
  156. .cpu_name = "POWER4 (gp)",
  157. .cpu_features = CPU_FTRS_POWER4,
  158. .cpu_user_features = COMMON_USER_POWER4,
  159. .icache_bsize = 128,
  160. .dcache_bsize = 128,
  161. .num_pmcs = 8,
  162. .cpu_setup = __setup_cpu_power4,
  163. #ifdef CONFIG_OPROFILE
  164. .oprofile_cpu_type = "ppc64/power4",
  165. .oprofile_model = &op_model_rs64,
  166. #endif
  167. },
  168. { /* Power4+ */
  169. .pvr_mask = 0xffff0000,
  170. .pvr_value = 0x00380000,
  171. .cpu_name = "POWER4+ (gq)",
  172. .cpu_features = CPU_FTRS_POWER4,
  173. .cpu_user_features = COMMON_USER_POWER4,
  174. .icache_bsize = 128,
  175. .dcache_bsize = 128,
  176. .num_pmcs = 8,
  177. .cpu_setup = __setup_cpu_power4,
  178. #ifdef CONFIG_OPROFILE
  179. .oprofile_cpu_type = "ppc64/power4",
  180. .oprofile_model = &op_model_power4,
  181. #endif
  182. },
  183. { /* PPC970 */
  184. .pvr_mask = 0xffff0000,
  185. .pvr_value = 0x00390000,
  186. .cpu_name = "PPC970",
  187. .cpu_features = CPU_FTRS_PPC970,
  188. .cpu_user_features = COMMON_USER_POWER4 |
  189. PPC_FEATURE_HAS_ALTIVEC_COMP,
  190. .icache_bsize = 128,
  191. .dcache_bsize = 128,
  192. .num_pmcs = 8,
  193. .cpu_setup = __setup_cpu_ppc970,
  194. #ifdef CONFIG_OPROFILE
  195. .oprofile_cpu_type = "ppc64/970",
  196. .oprofile_model = &op_model_power4,
  197. #endif
  198. },
  199. #endif /* CONFIG_PPC64 */
  200. #if defined(CONFIG_PPC64) || defined(CONFIG_POWER4)
  201. { /* PPC970FX */
  202. .pvr_mask = 0xffff0000,
  203. .pvr_value = 0x003c0000,
  204. .cpu_name = "PPC970FX",
  205. #ifdef CONFIG_PPC32
  206. .cpu_features = CPU_FTRS_970_32,
  207. #else
  208. .cpu_features = CPU_FTRS_PPC970,
  209. #endif
  210. .cpu_user_features = COMMON_USER_POWER4 |
  211. PPC_FEATURE_HAS_ALTIVEC_COMP,
  212. .icache_bsize = 128,
  213. .dcache_bsize = 128,
  214. .num_pmcs = 8,
  215. .cpu_setup = __setup_cpu_ppc970,
  216. #ifdef CONFIG_OPROFILE
  217. .oprofile_cpu_type = "ppc64/970",
  218. .oprofile_model = &op_model_power4,
  219. #endif
  220. },
  221. #endif /* defined(CONFIG_PPC64) || defined(CONFIG_POWER4) */
  222. #ifdef CONFIG_PPC64
  223. { /* PPC970MP */
  224. .pvr_mask = 0xffff0000,
  225. .pvr_value = 0x00440000,
  226. .cpu_name = "PPC970MP",
  227. .cpu_features = CPU_FTRS_PPC970,
  228. .cpu_user_features = COMMON_USER_POWER4 |
  229. PPC_FEATURE_HAS_ALTIVEC_COMP,
  230. .icache_bsize = 128,
  231. .dcache_bsize = 128,
  232. .cpu_setup = __setup_cpu_ppc970,
  233. #ifdef CONFIG_OPROFILE
  234. .oprofile_cpu_type = "ppc64/970",
  235. .oprofile_model = &op_model_power4,
  236. #endif
  237. },
  238. { /* Power5 GR */
  239. .pvr_mask = 0xffff0000,
  240. .pvr_value = 0x003a0000,
  241. .cpu_name = "POWER5 (gr)",
  242. .cpu_features = CPU_FTRS_POWER5,
  243. .cpu_user_features = COMMON_USER_POWER5,
  244. .icache_bsize = 128,
  245. .dcache_bsize = 128,
  246. .num_pmcs = 6,
  247. .cpu_setup = __setup_cpu_power4,
  248. #ifdef CONFIG_OPROFILE
  249. .oprofile_cpu_type = "ppc64/power5",
  250. .oprofile_model = &op_model_power4,
  251. #endif
  252. },
  253. { /* Power5 GS */
  254. .pvr_mask = 0xffff0000,
  255. .pvr_value = 0x003b0000,
  256. .cpu_name = "POWER5 (gs)",
  257. .cpu_features = CPU_FTRS_POWER5,
  258. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  259. .icache_bsize = 128,
  260. .dcache_bsize = 128,
  261. .num_pmcs = 6,
  262. .cpu_setup = __setup_cpu_power4,
  263. #ifdef CONFIG_OPROFILE
  264. .oprofile_cpu_type = "ppc64/power5",
  265. .oprofile_model = &op_model_power4,
  266. #endif
  267. },
  268. { /* BE DD1.x */
  269. .pvr_mask = 0xffff0000,
  270. .pvr_value = 0x00700000,
  271. .cpu_name = "Cell Broadband Engine",
  272. .cpu_features = CPU_FTRS_CELL,
  273. .cpu_user_features = COMMON_USER_PPC64 |
  274. PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP,
  275. .icache_bsize = 128,
  276. .dcache_bsize = 128,
  277. .cpu_setup = __setup_cpu_be,
  278. },
  279. { /* default match */
  280. .pvr_mask = 0x00000000,
  281. .pvr_value = 0x00000000,
  282. .cpu_name = "POWER4 (compatible)",
  283. .cpu_features = CPU_FTRS_COMPATIBLE,
  284. .cpu_user_features = COMMON_USER_PPC64,
  285. .icache_bsize = 128,
  286. .dcache_bsize = 128,
  287. .num_pmcs = 6,
  288. .cpu_setup = __setup_cpu_power4,
  289. }
  290. #endif /* CONFIG_PPC64 */
  291. #ifdef CONFIG_PPC32
  292. #if CLASSIC_PPC
  293. { /* 601 */
  294. .pvr_mask = 0xffff0000,
  295. .pvr_value = 0x00010000,
  296. .cpu_name = "601",
  297. .cpu_features = CPU_FTRS_PPC601,
  298. .cpu_user_features = COMMON_USER | PPC_FEATURE_601_INSTR |
  299. PPC_FEATURE_UNIFIED_CACHE | PPC_FEATURE_NO_TB,
  300. .icache_bsize = 32,
  301. .dcache_bsize = 32,
  302. },
  303. { /* 603 */
  304. .pvr_mask = 0xffff0000,
  305. .pvr_value = 0x00030000,
  306. .cpu_name = "603",
  307. .cpu_features = CPU_FTRS_603,
  308. .cpu_user_features = COMMON_USER,
  309. .icache_bsize = 32,
  310. .dcache_bsize = 32,
  311. .cpu_setup = __setup_cpu_603
  312. },
  313. { /* 603e */
  314. .pvr_mask = 0xffff0000,
  315. .pvr_value = 0x00060000,
  316. .cpu_name = "603e",
  317. .cpu_features = CPU_FTRS_603,
  318. .cpu_user_features = COMMON_USER,
  319. .icache_bsize = 32,
  320. .dcache_bsize = 32,
  321. .cpu_setup = __setup_cpu_603
  322. },
  323. { /* 603ev */
  324. .pvr_mask = 0xffff0000,
  325. .pvr_value = 0x00070000,
  326. .cpu_name = "603ev",
  327. .cpu_features = CPU_FTRS_603,
  328. .cpu_user_features = COMMON_USER,
  329. .icache_bsize = 32,
  330. .dcache_bsize = 32,
  331. .cpu_setup = __setup_cpu_603
  332. },
  333. { /* 604 */
  334. .pvr_mask = 0xffff0000,
  335. .pvr_value = 0x00040000,
  336. .cpu_name = "604",
  337. .cpu_features = CPU_FTRS_604,
  338. .cpu_user_features = COMMON_USER,
  339. .icache_bsize = 32,
  340. .dcache_bsize = 32,
  341. .num_pmcs = 2,
  342. .cpu_setup = __setup_cpu_604
  343. },
  344. { /* 604e */
  345. .pvr_mask = 0xfffff000,
  346. .pvr_value = 0x00090000,
  347. .cpu_name = "604e",
  348. .cpu_features = CPU_FTRS_604,
  349. .cpu_user_features = COMMON_USER,
  350. .icache_bsize = 32,
  351. .dcache_bsize = 32,
  352. .num_pmcs = 4,
  353. .cpu_setup = __setup_cpu_604
  354. },
  355. { /* 604r */
  356. .pvr_mask = 0xffff0000,
  357. .pvr_value = 0x00090000,
  358. .cpu_name = "604r",
  359. .cpu_features = CPU_FTRS_604,
  360. .cpu_user_features = COMMON_USER,
  361. .icache_bsize = 32,
  362. .dcache_bsize = 32,
  363. .num_pmcs = 4,
  364. .cpu_setup = __setup_cpu_604
  365. },
  366. { /* 604ev */
  367. .pvr_mask = 0xffff0000,
  368. .pvr_value = 0x000a0000,
  369. .cpu_name = "604ev",
  370. .cpu_features = CPU_FTRS_604,
  371. .cpu_user_features = COMMON_USER,
  372. .icache_bsize = 32,
  373. .dcache_bsize = 32,
  374. .num_pmcs = 4,
  375. .cpu_setup = __setup_cpu_604
  376. },
  377. { /* 740/750 (0x4202, don't support TAU ?) */
  378. .pvr_mask = 0xffffffff,
  379. .pvr_value = 0x00084202,
  380. .cpu_name = "740/750",
  381. .cpu_features = CPU_FTRS_740_NOTAU,
  382. .cpu_user_features = COMMON_USER,
  383. .icache_bsize = 32,
  384. .dcache_bsize = 32,
  385. .num_pmcs = 4,
  386. .cpu_setup = __setup_cpu_750
  387. },
  388. { /* 750CX (80100 and 8010x?) */
  389. .pvr_mask = 0xfffffff0,
  390. .pvr_value = 0x00080100,
  391. .cpu_name = "750CX",
  392. .cpu_features = CPU_FTRS_750,
  393. .cpu_user_features = COMMON_USER,
  394. .icache_bsize = 32,
  395. .dcache_bsize = 32,
  396. .num_pmcs = 4,
  397. .cpu_setup = __setup_cpu_750cx
  398. },
  399. { /* 750CX (82201 and 82202) */
  400. .pvr_mask = 0xfffffff0,
  401. .pvr_value = 0x00082200,
  402. .cpu_name = "750CX",
  403. .cpu_features = CPU_FTRS_750,
  404. .cpu_user_features = COMMON_USER,
  405. .icache_bsize = 32,
  406. .dcache_bsize = 32,
  407. .num_pmcs = 4,
  408. .cpu_setup = __setup_cpu_750cx
  409. },
  410. { /* 750CXe (82214) */
  411. .pvr_mask = 0xfffffff0,
  412. .pvr_value = 0x00082210,
  413. .cpu_name = "750CXe",
  414. .cpu_features = CPU_FTRS_750,
  415. .cpu_user_features = COMMON_USER,
  416. .icache_bsize = 32,
  417. .dcache_bsize = 32,
  418. .num_pmcs = 4,
  419. .cpu_setup = __setup_cpu_750cx
  420. },
  421. { /* 750CXe "Gekko" (83214) */
  422. .pvr_mask = 0xffffffff,
  423. .pvr_value = 0x00083214,
  424. .cpu_name = "750CXe",
  425. .cpu_features = CPU_FTRS_750,
  426. .cpu_user_features = COMMON_USER,
  427. .icache_bsize = 32,
  428. .dcache_bsize = 32,
  429. .num_pmcs = 4,
  430. .cpu_setup = __setup_cpu_750cx
  431. },
  432. { /* 745/755 */
  433. .pvr_mask = 0xfffff000,
  434. .pvr_value = 0x00083000,
  435. .cpu_name = "745/755",
  436. .cpu_features = CPU_FTRS_750,
  437. .cpu_user_features = COMMON_USER,
  438. .icache_bsize = 32,
  439. .dcache_bsize = 32,
  440. .num_pmcs = 4,
  441. .cpu_setup = __setup_cpu_750
  442. },
  443. { /* 750FX rev 1.x */
  444. .pvr_mask = 0xffffff00,
  445. .pvr_value = 0x70000100,
  446. .cpu_name = "750FX",
  447. .cpu_features = CPU_FTRS_750FX1,
  448. .cpu_user_features = COMMON_USER,
  449. .icache_bsize = 32,
  450. .dcache_bsize = 32,
  451. .num_pmcs = 4,
  452. .cpu_setup = __setup_cpu_750
  453. },
  454. { /* 750FX rev 2.0 must disable HID0[DPM] */
  455. .pvr_mask = 0xffffffff,
  456. .pvr_value = 0x70000200,
  457. .cpu_name = "750FX",
  458. .cpu_features = CPU_FTRS_750FX2,
  459. .cpu_user_features = COMMON_USER,
  460. .icache_bsize = 32,
  461. .dcache_bsize = 32,
  462. .num_pmcs = 4,
  463. .cpu_setup = __setup_cpu_750
  464. },
  465. { /* 750FX (All revs except 2.0) */
  466. .pvr_mask = 0xffff0000,
  467. .pvr_value = 0x70000000,
  468. .cpu_name = "750FX",
  469. .cpu_features = CPU_FTRS_750FX,
  470. .cpu_user_features = COMMON_USER,
  471. .icache_bsize = 32,
  472. .dcache_bsize = 32,
  473. .num_pmcs = 4,
  474. .cpu_setup = __setup_cpu_750fx
  475. },
  476. { /* 750GX */
  477. .pvr_mask = 0xffff0000,
  478. .pvr_value = 0x70020000,
  479. .cpu_name = "750GX",
  480. .cpu_features = CPU_FTRS_750GX,
  481. .cpu_user_features = COMMON_USER,
  482. .icache_bsize = 32,
  483. .dcache_bsize = 32,
  484. .num_pmcs = 4,
  485. .cpu_setup = __setup_cpu_750fx
  486. },
  487. { /* 740/750 (L2CR bit need fixup for 740) */
  488. .pvr_mask = 0xffff0000,
  489. .pvr_value = 0x00080000,
  490. .cpu_name = "740/750",
  491. .cpu_features = CPU_FTRS_740,
  492. .cpu_user_features = COMMON_USER,
  493. .icache_bsize = 32,
  494. .dcache_bsize = 32,
  495. .num_pmcs = 4,
  496. .cpu_setup = __setup_cpu_750
  497. },
  498. { /* 7400 rev 1.1 ? (no TAU) */
  499. .pvr_mask = 0xffffffff,
  500. .pvr_value = 0x000c1101,
  501. .cpu_name = "7400 (1.1)",
  502. .cpu_features = CPU_FTRS_7400_NOTAU,
  503. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  504. .icache_bsize = 32,
  505. .dcache_bsize = 32,
  506. .num_pmcs = 4,
  507. .cpu_setup = __setup_cpu_7400
  508. },
  509. { /* 7400 */
  510. .pvr_mask = 0xffff0000,
  511. .pvr_value = 0x000c0000,
  512. .cpu_name = "7400",
  513. .cpu_features = CPU_FTRS_7400,
  514. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  515. .icache_bsize = 32,
  516. .dcache_bsize = 32,
  517. .num_pmcs = 4,
  518. .cpu_setup = __setup_cpu_7400
  519. },
  520. { /* 7410 */
  521. .pvr_mask = 0xffff0000,
  522. .pvr_value = 0x800c0000,
  523. .cpu_name = "7410",
  524. .cpu_features = CPU_FTRS_7400,
  525. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  526. .icache_bsize = 32,
  527. .dcache_bsize = 32,
  528. .num_pmcs = 4,
  529. .cpu_setup = __setup_cpu_7410
  530. },
  531. { /* 7450 2.0 - no doze/nap */
  532. .pvr_mask = 0xffffffff,
  533. .pvr_value = 0x80000200,
  534. .cpu_name = "7450",
  535. .cpu_features = CPU_FTRS_7450_20,
  536. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  537. .icache_bsize = 32,
  538. .dcache_bsize = 32,
  539. .num_pmcs = 6,
  540. .cpu_setup = __setup_cpu_745x,
  541. #ifdef CONFIG_OPROFILE
  542. .oprofile_cpu_type = "ppc/7450",
  543. .oprofile_model = &op_model_7450,
  544. #endif
  545. },
  546. { /* 7450 2.1 */
  547. .pvr_mask = 0xffffffff,
  548. .pvr_value = 0x80000201,
  549. .cpu_name = "7450",
  550. .cpu_features = CPU_FTRS_7450_21,
  551. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  552. .icache_bsize = 32,
  553. .dcache_bsize = 32,
  554. .num_pmcs = 6,
  555. .cpu_setup = __setup_cpu_745x,
  556. #ifdef CONFIG_OPROFILE
  557. .oprofile_cpu_type = "ppc/7450",
  558. .oprofile_model = &op_model_7450,
  559. #endif
  560. },
  561. { /* 7450 2.3 and newer */
  562. .pvr_mask = 0xffff0000,
  563. .pvr_value = 0x80000000,
  564. .cpu_name = "7450",
  565. .cpu_features = CPU_FTRS_7450_23,
  566. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  567. .icache_bsize = 32,
  568. .dcache_bsize = 32,
  569. .num_pmcs = 6,
  570. .cpu_setup = __setup_cpu_745x,
  571. #ifdef CONFIG_OPROFILE
  572. .oprofile_cpu_type = "ppc/7450",
  573. .oprofile_model = &op_model_7450,
  574. #endif
  575. },
  576. { /* 7455 rev 1.x */
  577. .pvr_mask = 0xffffff00,
  578. .pvr_value = 0x80010100,
  579. .cpu_name = "7455",
  580. .cpu_features = CPU_FTRS_7455_1,
  581. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  582. .icache_bsize = 32,
  583. .dcache_bsize = 32,
  584. .num_pmcs = 6,
  585. .cpu_setup = __setup_cpu_745x,
  586. #ifdef CONFIG_OPROFILE
  587. .oprofile_cpu_type = "ppc/7450",
  588. .oprofile_model = &op_model_7450,
  589. #endif
  590. },
  591. { /* 7455 rev 2.0 */
  592. .pvr_mask = 0xffffffff,
  593. .pvr_value = 0x80010200,
  594. .cpu_name = "7455",
  595. .cpu_features = CPU_FTRS_7455_20,
  596. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  597. .icache_bsize = 32,
  598. .dcache_bsize = 32,
  599. .num_pmcs = 6,
  600. .cpu_setup = __setup_cpu_745x,
  601. #ifdef CONFIG_OPROFILE
  602. .oprofile_cpu_type = "ppc/7450",
  603. .oprofile_model = &op_model_7450,
  604. #endif
  605. },
  606. { /* 7455 others */
  607. .pvr_mask = 0xffff0000,
  608. .pvr_value = 0x80010000,
  609. .cpu_name = "7455",
  610. .cpu_features = CPU_FTRS_7455,
  611. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  612. .icache_bsize = 32,
  613. .dcache_bsize = 32,
  614. .num_pmcs = 6,
  615. .cpu_setup = __setup_cpu_745x,
  616. #ifdef CONFIG_OPROFILE
  617. .oprofile_cpu_type = "ppc/7450",
  618. .oprofile_model = &op_model_7450,
  619. #endif
  620. },
  621. { /* 7447/7457 Rev 1.0 */
  622. .pvr_mask = 0xffffffff,
  623. .pvr_value = 0x80020100,
  624. .cpu_name = "7447/7457",
  625. .cpu_features = CPU_FTRS_7447_10,
  626. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  627. .icache_bsize = 32,
  628. .dcache_bsize = 32,
  629. .num_pmcs = 6,
  630. .cpu_setup = __setup_cpu_745x,
  631. #ifdef CONFIG_OPROFILE
  632. .oprofile_cpu_type = "ppc/7450",
  633. .oprofile_model = &op_model_7450,
  634. #endif
  635. },
  636. { /* 7447/7457 Rev 1.1 */
  637. .pvr_mask = 0xffffffff,
  638. .pvr_value = 0x80020101,
  639. .cpu_name = "7447/7457",
  640. .cpu_features = CPU_FTRS_7447_10,
  641. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  642. .icache_bsize = 32,
  643. .dcache_bsize = 32,
  644. .num_pmcs = 6,
  645. .cpu_setup = __setup_cpu_745x,
  646. #ifdef CONFIG_OPROFILE
  647. .oprofile_cpu_type = "ppc/7450",
  648. .oprofile_model = &op_model_7450,
  649. #endif
  650. },
  651. { /* 7447/7457 Rev 1.2 and later */
  652. .pvr_mask = 0xffff0000,
  653. .pvr_value = 0x80020000,
  654. .cpu_name = "7447/7457",
  655. .cpu_features = CPU_FTRS_7447,
  656. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  657. .icache_bsize = 32,
  658. .dcache_bsize = 32,
  659. .num_pmcs = 6,
  660. .cpu_setup = __setup_cpu_745x,
  661. #ifdef CONFIG_OPROFILE
  662. .oprofile_cpu_type = "ppc/7450",
  663. .oprofile_model = &op_model_7450,
  664. #endif
  665. },
  666. { /* 7447A */
  667. .pvr_mask = 0xffff0000,
  668. .pvr_value = 0x80030000,
  669. .cpu_name = "7447A",
  670. .cpu_features = CPU_FTRS_7447A,
  671. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  672. .icache_bsize = 32,
  673. .dcache_bsize = 32,
  674. .num_pmcs = 6,
  675. .cpu_setup = __setup_cpu_745x,
  676. #ifdef CONFIG_OPROFILE
  677. .oprofile_cpu_type = "ppc/7450",
  678. .oprofile_model = &op_model_7450,
  679. #endif
  680. },
  681. { /* 7448 */
  682. .pvr_mask = 0xffff0000,
  683. .pvr_value = 0x80040000,
  684. .cpu_name = "7448",
  685. .cpu_features = CPU_FTRS_7447A,
  686. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  687. .icache_bsize = 32,
  688. .dcache_bsize = 32,
  689. .num_pmcs = 6,
  690. .cpu_setup = __setup_cpu_745x,
  691. #ifdef CONFIG_OPROFILE
  692. .oprofile_cpu_type = "ppc/7450",
  693. .oprofile_model = &op_model_7450,
  694. #endif
  695. },
  696. { /* 82xx (8240, 8245, 8260 are all 603e cores) */
  697. .pvr_mask = 0x7fff0000,
  698. .pvr_value = 0x00810000,
  699. .cpu_name = "82xx",
  700. .cpu_features = CPU_FTRS_82XX,
  701. .cpu_user_features = COMMON_USER,
  702. .icache_bsize = 32,
  703. .dcache_bsize = 32,
  704. .cpu_setup = __setup_cpu_603
  705. },
  706. { /* All G2_LE (603e core, plus some) have the same pvr */
  707. .pvr_mask = 0x7fff0000,
  708. .pvr_value = 0x00820000,
  709. .cpu_name = "G2_LE",
  710. .cpu_features = CPU_FTRS_G2_LE,
  711. .cpu_user_features = COMMON_USER,
  712. .icache_bsize = 32,
  713. .dcache_bsize = 32,
  714. .cpu_setup = __setup_cpu_603
  715. },
  716. { /* e300 (a 603e core, plus some) on 83xx */
  717. .pvr_mask = 0x7fff0000,
  718. .pvr_value = 0x00830000,
  719. .cpu_name = "e300",
  720. .cpu_features = CPU_FTRS_E300,
  721. .cpu_user_features = COMMON_USER,
  722. .icache_bsize = 32,
  723. .dcache_bsize = 32,
  724. .cpu_setup = __setup_cpu_603
  725. },
  726. { /* default match, we assume split I/D cache & TB (non-601)... */
  727. .pvr_mask = 0x00000000,
  728. .pvr_value = 0x00000000,
  729. .cpu_name = "(generic PPC)",
  730. .cpu_features = CPU_FTRS_CLASSIC32,
  731. .cpu_user_features = COMMON_USER,
  732. .icache_bsize = 32,
  733. .dcache_bsize = 32,
  734. },
  735. #endif /* CLASSIC_PPC */
  736. #ifdef CONFIG_8xx
  737. { /* 8xx */
  738. .pvr_mask = 0xffff0000,
  739. .pvr_value = 0x00500000,
  740. .cpu_name = "8xx",
  741. /* CPU_FTR_MAYBE_CAN_DOZE is possible,
  742. * if the 8xx code is there.... */
  743. .cpu_features = CPU_FTRS_8XX,
  744. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  745. .icache_bsize = 16,
  746. .dcache_bsize = 16,
  747. },
  748. #endif /* CONFIG_8xx */
  749. #ifdef CONFIG_40x
  750. { /* 403GC */
  751. .pvr_mask = 0xffffff00,
  752. .pvr_value = 0x00200200,
  753. .cpu_name = "403GC",
  754. .cpu_features = CPU_FTRS_40X,
  755. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  756. .icache_bsize = 16,
  757. .dcache_bsize = 16,
  758. },
  759. { /* 403GCX */
  760. .pvr_mask = 0xffffff00,
  761. .pvr_value = 0x00201400,
  762. .cpu_name = "403GCX",
  763. .cpu_features = CPU_FTRS_40X,
  764. .cpu_user_features = PPC_FEATURE_32 |
  765. PPC_FEATURE_HAS_MMU | PPC_FEATURE_NO_TB,
  766. .icache_bsize = 16,
  767. .dcache_bsize = 16,
  768. },
  769. { /* 403G ?? */
  770. .pvr_mask = 0xffff0000,
  771. .pvr_value = 0x00200000,
  772. .cpu_name = "403G ??",
  773. .cpu_features = CPU_FTRS_40X,
  774. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  775. .icache_bsize = 16,
  776. .dcache_bsize = 16,
  777. },
  778. { /* 405GP */
  779. .pvr_mask = 0xffff0000,
  780. .pvr_value = 0x40110000,
  781. .cpu_name = "405GP",
  782. .cpu_features = CPU_FTRS_40X,
  783. .cpu_user_features = PPC_FEATURE_32 |
  784. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  785. .icache_bsize = 32,
  786. .dcache_bsize = 32,
  787. },
  788. { /* STB 03xxx */
  789. .pvr_mask = 0xffff0000,
  790. .pvr_value = 0x40130000,
  791. .cpu_name = "STB03xxx",
  792. .cpu_features = CPU_FTRS_40X,
  793. .cpu_user_features = PPC_FEATURE_32 |
  794. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  795. .icache_bsize = 32,
  796. .dcache_bsize = 32,
  797. },
  798. { /* STB 04xxx */
  799. .pvr_mask = 0xffff0000,
  800. .pvr_value = 0x41810000,
  801. .cpu_name = "STB04xxx",
  802. .cpu_features = CPU_FTRS_40X,
  803. .cpu_user_features = PPC_FEATURE_32 |
  804. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  805. .icache_bsize = 32,
  806. .dcache_bsize = 32,
  807. },
  808. { /* NP405L */
  809. .pvr_mask = 0xffff0000,
  810. .pvr_value = 0x41610000,
  811. .cpu_name = "NP405L",
  812. .cpu_features = CPU_FTRS_40X,
  813. .cpu_user_features = PPC_FEATURE_32 |
  814. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  815. .icache_bsize = 32,
  816. .dcache_bsize = 32,
  817. },
  818. { /* NP4GS3 */
  819. .pvr_mask = 0xffff0000,
  820. .pvr_value = 0x40B10000,
  821. .cpu_name = "NP4GS3",
  822. .cpu_features = CPU_FTRS_40X,
  823. .cpu_user_features = PPC_FEATURE_32 |
  824. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  825. .icache_bsize = 32,
  826. .dcache_bsize = 32,
  827. },
  828. { /* NP405H */
  829. .pvr_mask = 0xffff0000,
  830. .pvr_value = 0x41410000,
  831. .cpu_name = "NP405H",
  832. .cpu_features = CPU_FTRS_40X,
  833. .cpu_user_features = PPC_FEATURE_32 |
  834. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  835. .icache_bsize = 32,
  836. .dcache_bsize = 32,
  837. },
  838. { /* 405GPr */
  839. .pvr_mask = 0xffff0000,
  840. .pvr_value = 0x50910000,
  841. .cpu_name = "405GPr",
  842. .cpu_features = CPU_FTRS_40X,
  843. .cpu_user_features = PPC_FEATURE_32 |
  844. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  845. .icache_bsize = 32,
  846. .dcache_bsize = 32,
  847. },
  848. { /* STBx25xx */
  849. .pvr_mask = 0xffff0000,
  850. .pvr_value = 0x51510000,
  851. .cpu_name = "STBx25xx",
  852. .cpu_features = CPU_FTRS_40X,
  853. .cpu_user_features = PPC_FEATURE_32 |
  854. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  855. .icache_bsize = 32,
  856. .dcache_bsize = 32,
  857. },
  858. { /* 405LP */
  859. .pvr_mask = 0xffff0000,
  860. .pvr_value = 0x41F10000,
  861. .cpu_name = "405LP",
  862. .cpu_features = CPU_FTRS_40X,
  863. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  864. .icache_bsize = 32,
  865. .dcache_bsize = 32,
  866. },
  867. { /* Xilinx Virtex-II Pro */
  868. .pvr_mask = 0xffff0000,
  869. .pvr_value = 0x20010000,
  870. .cpu_name = "Virtex-II Pro",
  871. .cpu_features = CPU_FTRS_40X,
  872. .cpu_user_features = PPC_FEATURE_32 |
  873. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  874. .icache_bsize = 32,
  875. .dcache_bsize = 32,
  876. },
  877. { /* 405EP */
  878. .pvr_mask = 0xffff0000,
  879. .pvr_value = 0x51210000,
  880. .cpu_name = "405EP",
  881. .cpu_features = CPU_FTRS_40X,
  882. .cpu_user_features = PPC_FEATURE_32 |
  883. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  884. .icache_bsize = 32,
  885. .dcache_bsize = 32,
  886. },
  887. #endif /* CONFIG_40x */
  888. #ifdef CONFIG_44x
  889. {
  890. .pvr_mask = 0xf0000fff,
  891. .pvr_value = 0x40000850,
  892. .cpu_name = "440EP Rev. A",
  893. .cpu_features = CPU_FTRS_44X,
  894. .cpu_user_features = COMMON_USER, /* 440EP has an FPU */
  895. .icache_bsize = 32,
  896. .dcache_bsize = 32,
  897. },
  898. {
  899. .pvr_mask = 0xf0000fff,
  900. .pvr_value = 0x400008d3,
  901. .cpu_name = "440EP Rev. B",
  902. .cpu_features = CPU_FTRS_44X,
  903. .cpu_user_features = COMMON_USER, /* 440EP has an FPU */
  904. .icache_bsize = 32,
  905. .dcache_bsize = 32,
  906. },
  907. { /* 440GP Rev. B */
  908. .pvr_mask = 0xf0000fff,
  909. .pvr_value = 0x40000440,
  910. .cpu_name = "440GP Rev. B",
  911. .cpu_features = CPU_FTRS_44X,
  912. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  913. .icache_bsize = 32,
  914. .dcache_bsize = 32,
  915. },
  916. { /* 440GP Rev. C */
  917. .pvr_mask = 0xf0000fff,
  918. .pvr_value = 0x40000481,
  919. .cpu_name = "440GP Rev. C",
  920. .cpu_features = CPU_FTRS_44X,
  921. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  922. .icache_bsize = 32,
  923. .dcache_bsize = 32,
  924. },
  925. { /* 440GX Rev. A */
  926. .pvr_mask = 0xf0000fff,
  927. .pvr_value = 0x50000850,
  928. .cpu_name = "440GX Rev. A",
  929. .cpu_features = CPU_FTRS_44X,
  930. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  931. .icache_bsize = 32,
  932. .dcache_bsize = 32,
  933. },
  934. { /* 440GX Rev. B */
  935. .pvr_mask = 0xf0000fff,
  936. .pvr_value = 0x50000851,
  937. .cpu_name = "440GX Rev. B",
  938. .cpu_features = CPU_FTRS_44X,
  939. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  940. .icache_bsize = 32,
  941. .dcache_bsize = 32,
  942. },
  943. { /* 440GX Rev. C */
  944. .pvr_mask = 0xf0000fff,
  945. .pvr_value = 0x50000892,
  946. .cpu_name = "440GX Rev. C",
  947. .cpu_features = CPU_FTRS_44X,
  948. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  949. .icache_bsize = 32,
  950. .dcache_bsize = 32,
  951. },
  952. { /* 440GX Rev. F */
  953. .pvr_mask = 0xf0000fff,
  954. .pvr_value = 0x50000894,
  955. .cpu_name = "440GX Rev. F",
  956. .cpu_features = CPU_FTRS_44X,
  957. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  958. .icache_bsize = 32,
  959. .dcache_bsize = 32,
  960. },
  961. { /* 440SP Rev. A */
  962. .pvr_mask = 0xff000fff,
  963. .pvr_value = 0x53000891,
  964. .cpu_name = "440SP Rev. A",
  965. .cpu_features = CPU_FTRS_44X,
  966. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  967. .icache_bsize = 32,
  968. .dcache_bsize = 32,
  969. },
  970. { /* 440SPe Rev. A */
  971. .pvr_mask = 0xff000fff,
  972. .pvr_value = 0x53000890,
  973. .cpu_name = "440SPe Rev. A",
  974. .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
  975. CPU_FTR_USE_TB,
  976. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  977. .icache_bsize = 32,
  978. .dcache_bsize = 32,
  979. },
  980. #endif /* CONFIG_44x */
  981. #ifdef CONFIG_FSL_BOOKE
  982. { /* e200z5 */
  983. .pvr_mask = 0xfff00000,
  984. .pvr_value = 0x81000000,
  985. .cpu_name = "e200z5",
  986. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  987. .cpu_features = CPU_FTRS_E200,
  988. .cpu_user_features = PPC_FEATURE_32 |
  989. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_EFP_SINGLE |
  990. PPC_FEATURE_UNIFIED_CACHE,
  991. .dcache_bsize = 32,
  992. },
  993. { /* e200z6 */
  994. .pvr_mask = 0xfff00000,
  995. .pvr_value = 0x81100000,
  996. .cpu_name = "e200z6",
  997. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  998. .cpu_features = CPU_FTRS_E200,
  999. .cpu_user_features = PPC_FEATURE_32 |
  1000. PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
  1001. PPC_FEATURE_HAS_EFP_SINGLE |
  1002. PPC_FEATURE_UNIFIED_CACHE,
  1003. .dcache_bsize = 32,
  1004. },
  1005. { /* e500 */
  1006. .pvr_mask = 0xffff0000,
  1007. .pvr_value = 0x80200000,
  1008. .cpu_name = "e500",
  1009. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1010. .cpu_features = CPU_FTRS_E500,
  1011. .cpu_user_features = PPC_FEATURE_32 |
  1012. PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
  1013. PPC_FEATURE_HAS_EFP_SINGLE,
  1014. .icache_bsize = 32,
  1015. .dcache_bsize = 32,
  1016. .num_pmcs = 4,
  1017. #ifdef CONFIG_OPROFILE
  1018. .oprofile_cpu_type = "ppc/e500",
  1019. .oprofile_model = &op_model_fsl_booke,
  1020. #endif
  1021. },
  1022. { /* e500v2 */
  1023. .pvr_mask = 0xffff0000,
  1024. .pvr_value = 0x80210000,
  1025. .cpu_name = "e500v2",
  1026. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1027. .cpu_features = CPU_FTRS_E500_2,
  1028. .cpu_user_features = PPC_FEATURE_32 |
  1029. PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
  1030. PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_HAS_EFP_DOUBLE,
  1031. .icache_bsize = 32,
  1032. .dcache_bsize = 32,
  1033. .num_pmcs = 4,
  1034. #ifdef CONFIG_OPROFILE
  1035. .oprofile_cpu_type = "ppc/e500",
  1036. .oprofile_model = &op_model_fsl_booke,
  1037. #endif
  1038. },
  1039. #endif
  1040. #if !CLASSIC_PPC
  1041. { /* default match */
  1042. .pvr_mask = 0x00000000,
  1043. .pvr_value = 0x00000000,
  1044. .cpu_name = "(generic PPC)",
  1045. .cpu_features = CPU_FTRS_GENERIC_32,
  1046. .cpu_user_features = PPC_FEATURE_32,
  1047. .icache_bsize = 32,
  1048. .dcache_bsize = 32,
  1049. }
  1050. #endif /* !CLASSIC_PPC */
  1051. #endif /* CONFIG_PPC32 */
  1052. };