qeth_core_main.c 130 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791379237933794379537963797379837993800380138023803380438053806380738083809381038113812381338143815381638173818381938203821382238233824382538263827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503851385238533854385538563857385838593860386138623863386438653866386738683869387038713872387338743875387638773878387938803881388238833884388538863887388838893890389138923893389438953896389738983899390039013902390339043905390639073908390939103911391239133914391539163917391839193920392139223923392439253926392739283929393039313932393339343935393639373938393939403941394239433944394539463947394839493950395139523953395439553956395739583959396039613962396339643965396639673968396939703971397239733974397539763977397839793980398139823983398439853986398739883989399039913992399339943995399639973998399940004001400240034004400540064007400840094010401140124013401440154016401740184019402040214022402340244025402640274028402940304031403240334034403540364037403840394040404140424043404440454046404740484049405040514052405340544055405640574058405940604061406240634064406540664067406840694070407140724073407440754076407740784079408040814082408340844085408640874088408940904091409240934094409540964097409840994100410141024103410441054106410741084109411041114112411341144115411641174118411941204121412241234124412541264127412841294130413141324133413441354136413741384139414041414142414341444145414641474148414941504151415241534154415541564157415841594160416141624163416441654166416741684169417041714172417341744175417641774178417941804181418241834184418541864187418841894190419141924193419441954196419741984199420042014202420342044205420642074208420942104211421242134214421542164217421842194220422142224223422442254226422742284229423042314232423342344235423642374238423942404241424242434244424542464247424842494250425142524253425442554256425742584259426042614262426342644265426642674268426942704271427242734274427542764277427842794280428142824283428442854286428742884289429042914292429342944295429642974298429943004301430243034304430543064307430843094310431143124313431443154316431743184319432043214322432343244325432643274328432943304331433243334334433543364337433843394340434143424343434443454346434743484349435043514352435343544355435643574358435943604361436243634364436543664367436843694370437143724373437443754376437743784379438043814382438343844385438643874388438943904391439243934394439543964397439843994400440144024403440444054406440744084409441044114412441344144415441644174418441944204421442244234424442544264427442844294430443144324433443444354436443744384439444044414442444344444445444644474448444944504451445244534454445544564457445844594460446144624463446444654466446744684469447044714472447344744475447644774478447944804481448244834484448544864487448844894490449144924493449444954496449744984499450045014502450345044505450645074508450945104511451245134514451545164517451845194520452145224523452445254526452745284529453045314532453345344535453645374538453945404541454245434544454545464547454845494550455145524553455445554556455745584559456045614562456345644565456645674568456945704571457245734574457545764577457845794580458145824583458445854586458745884589459045914592459345944595459645974598459946004601460246034604460546064607460846094610461146124613461446154616461746184619462046214622462346244625462646274628462946304631463246334634463546364637463846394640464146424643464446454646464746484649465046514652465346544655465646574658465946604661466246634664466546664667466846694670467146724673467446754676467746784679468046814682468346844685468646874688468946904691469246934694469546964697469846994700470147024703470447054706470747084709471047114712471347144715471647174718471947204721472247234724472547264727472847294730473147324733473447354736473747384739474047414742474347444745474647474748474947504751475247534754475547564757475847594760476147624763476447654766476747684769477047714772
  1. /*
  2. * drivers/s390/net/qeth_core_main.c
  3. *
  4. * Copyright IBM Corp. 2007, 2009
  5. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  6. * Frank Pavlic <fpavlic@de.ibm.com>,
  7. * Thomas Spatzier <tspat@de.ibm.com>,
  8. * Frank Blaschka <frank.blaschka@de.ibm.com>
  9. */
  10. #define KMSG_COMPONENT "qeth"
  11. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/string.h>
  15. #include <linux/errno.h>
  16. #include <linux/kernel.h>
  17. #include <linux/ip.h>
  18. #include <linux/tcp.h>
  19. #include <linux/mii.h>
  20. #include <linux/kthread.h>
  21. #include <linux/slab.h>
  22. #include <asm/ebcdic.h>
  23. #include <asm/io.h>
  24. #include "qeth_core.h"
  25. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  26. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  27. /* N P A M L V H */
  28. [QETH_DBF_SETUP] = {"qeth_setup",
  29. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  30. [QETH_DBF_MSG] = {"qeth_msg",
  31. 8, 1, 128, 3, &debug_sprintf_view, NULL},
  32. [QETH_DBF_CTRL] = {"qeth_control",
  33. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  34. };
  35. EXPORT_SYMBOL_GPL(qeth_dbf);
  36. struct qeth_card_list_struct qeth_core_card_list;
  37. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  38. struct kmem_cache *qeth_core_header_cache;
  39. EXPORT_SYMBOL_GPL(qeth_core_header_cache);
  40. static struct device *qeth_core_root_dev;
  41. static unsigned int known_devices[][6] = QETH_MODELLIST_ARRAY;
  42. static struct lock_class_key qdio_out_skb_queue_key;
  43. static void qeth_send_control_data_cb(struct qeth_channel *,
  44. struct qeth_cmd_buffer *);
  45. static int qeth_issue_next_read(struct qeth_card *);
  46. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  47. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  48. static void qeth_free_buffer_pool(struct qeth_card *);
  49. static int qeth_qdio_establish(struct qeth_card *);
  50. static inline const char *qeth_get_cardname(struct qeth_card *card)
  51. {
  52. if (card->info.guestlan) {
  53. switch (card->info.type) {
  54. case QETH_CARD_TYPE_OSD:
  55. return " Guest LAN QDIO";
  56. case QETH_CARD_TYPE_IQD:
  57. return " Guest LAN Hiper";
  58. case QETH_CARD_TYPE_OSM:
  59. return " Guest LAN QDIO - OSM";
  60. case QETH_CARD_TYPE_OSX:
  61. return " Guest LAN QDIO - OSX";
  62. default:
  63. return " unknown";
  64. }
  65. } else {
  66. switch (card->info.type) {
  67. case QETH_CARD_TYPE_OSD:
  68. return " OSD Express";
  69. case QETH_CARD_TYPE_IQD:
  70. return " HiperSockets";
  71. case QETH_CARD_TYPE_OSN:
  72. return " OSN QDIO";
  73. case QETH_CARD_TYPE_OSM:
  74. return " OSM QDIO";
  75. case QETH_CARD_TYPE_OSX:
  76. return " OSX QDIO";
  77. default:
  78. return " unknown";
  79. }
  80. }
  81. return " n/a";
  82. }
  83. /* max length to be returned: 14 */
  84. const char *qeth_get_cardname_short(struct qeth_card *card)
  85. {
  86. if (card->info.guestlan) {
  87. switch (card->info.type) {
  88. case QETH_CARD_TYPE_OSD:
  89. return "GuestLAN QDIO";
  90. case QETH_CARD_TYPE_IQD:
  91. return "GuestLAN Hiper";
  92. case QETH_CARD_TYPE_OSM:
  93. return "GuestLAN OSM";
  94. case QETH_CARD_TYPE_OSX:
  95. return "GuestLAN OSX";
  96. default:
  97. return "unknown";
  98. }
  99. } else {
  100. switch (card->info.type) {
  101. case QETH_CARD_TYPE_OSD:
  102. switch (card->info.link_type) {
  103. case QETH_LINK_TYPE_FAST_ETH:
  104. return "OSD_100";
  105. case QETH_LINK_TYPE_HSTR:
  106. return "HSTR";
  107. case QETH_LINK_TYPE_GBIT_ETH:
  108. return "OSD_1000";
  109. case QETH_LINK_TYPE_10GBIT_ETH:
  110. return "OSD_10GIG";
  111. case QETH_LINK_TYPE_LANE_ETH100:
  112. return "OSD_FE_LANE";
  113. case QETH_LINK_TYPE_LANE_TR:
  114. return "OSD_TR_LANE";
  115. case QETH_LINK_TYPE_LANE_ETH1000:
  116. return "OSD_GbE_LANE";
  117. case QETH_LINK_TYPE_LANE:
  118. return "OSD_ATM_LANE";
  119. default:
  120. return "OSD_Express";
  121. }
  122. case QETH_CARD_TYPE_IQD:
  123. return "HiperSockets";
  124. case QETH_CARD_TYPE_OSN:
  125. return "OSN";
  126. case QETH_CARD_TYPE_OSM:
  127. return "OSM_1000";
  128. case QETH_CARD_TYPE_OSX:
  129. return "OSX_10GIG";
  130. default:
  131. return "unknown";
  132. }
  133. }
  134. return "n/a";
  135. }
  136. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  137. int clear_start_mask)
  138. {
  139. unsigned long flags;
  140. spin_lock_irqsave(&card->thread_mask_lock, flags);
  141. card->thread_allowed_mask = threads;
  142. if (clear_start_mask)
  143. card->thread_start_mask &= threads;
  144. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  145. wake_up(&card->wait_q);
  146. }
  147. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  148. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  149. {
  150. unsigned long flags;
  151. int rc = 0;
  152. spin_lock_irqsave(&card->thread_mask_lock, flags);
  153. rc = (card->thread_running_mask & threads);
  154. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  155. return rc;
  156. }
  157. EXPORT_SYMBOL_GPL(qeth_threads_running);
  158. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  159. {
  160. return wait_event_interruptible(card->wait_q,
  161. qeth_threads_running(card, threads) == 0);
  162. }
  163. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  164. void qeth_clear_working_pool_list(struct qeth_card *card)
  165. {
  166. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  167. QETH_CARD_TEXT(card, 5, "clwrklst");
  168. list_for_each_entry_safe(pool_entry, tmp,
  169. &card->qdio.in_buf_pool.entry_list, list){
  170. list_del(&pool_entry->list);
  171. }
  172. }
  173. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  174. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  175. {
  176. struct qeth_buffer_pool_entry *pool_entry;
  177. void *ptr;
  178. int i, j;
  179. QETH_CARD_TEXT(card, 5, "alocpool");
  180. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  181. pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
  182. if (!pool_entry) {
  183. qeth_free_buffer_pool(card);
  184. return -ENOMEM;
  185. }
  186. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  187. ptr = (void *) __get_free_page(GFP_KERNEL);
  188. if (!ptr) {
  189. while (j > 0)
  190. free_page((unsigned long)
  191. pool_entry->elements[--j]);
  192. kfree(pool_entry);
  193. qeth_free_buffer_pool(card);
  194. return -ENOMEM;
  195. }
  196. pool_entry->elements[j] = ptr;
  197. }
  198. list_add(&pool_entry->init_list,
  199. &card->qdio.init_pool.entry_list);
  200. }
  201. return 0;
  202. }
  203. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  204. {
  205. QETH_CARD_TEXT(card, 2, "realcbp");
  206. if ((card->state != CARD_STATE_DOWN) &&
  207. (card->state != CARD_STATE_RECOVER))
  208. return -EPERM;
  209. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  210. qeth_clear_working_pool_list(card);
  211. qeth_free_buffer_pool(card);
  212. card->qdio.in_buf_pool.buf_count = bufcnt;
  213. card->qdio.init_pool.buf_count = bufcnt;
  214. return qeth_alloc_buffer_pool(card);
  215. }
  216. EXPORT_SYMBOL_GPL(qeth_realloc_buffer_pool);
  217. static int qeth_issue_next_read(struct qeth_card *card)
  218. {
  219. int rc;
  220. struct qeth_cmd_buffer *iob;
  221. QETH_CARD_TEXT(card, 5, "issnxrd");
  222. if (card->read.state != CH_STATE_UP)
  223. return -EIO;
  224. iob = qeth_get_buffer(&card->read);
  225. if (!iob) {
  226. dev_warn(&card->gdev->dev, "The qeth device driver "
  227. "failed to recover an error on the device\n");
  228. QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob "
  229. "available\n", dev_name(&card->gdev->dev));
  230. return -ENOMEM;
  231. }
  232. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  233. QETH_CARD_TEXT(card, 6, "noirqpnd");
  234. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  235. (addr_t) iob, 0, 0);
  236. if (rc) {
  237. QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! "
  238. "rc=%i\n", dev_name(&card->gdev->dev), rc);
  239. atomic_set(&card->read.irq_pending, 0);
  240. qeth_schedule_recovery(card);
  241. wake_up(&card->wait_q);
  242. }
  243. return rc;
  244. }
  245. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  246. {
  247. struct qeth_reply *reply;
  248. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  249. if (reply) {
  250. atomic_set(&reply->refcnt, 1);
  251. atomic_set(&reply->received, 0);
  252. reply->card = card;
  253. };
  254. return reply;
  255. }
  256. static void qeth_get_reply(struct qeth_reply *reply)
  257. {
  258. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  259. atomic_inc(&reply->refcnt);
  260. }
  261. static void qeth_put_reply(struct qeth_reply *reply)
  262. {
  263. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  264. if (atomic_dec_and_test(&reply->refcnt))
  265. kfree(reply);
  266. }
  267. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  268. struct qeth_card *card)
  269. {
  270. char *ipa_name;
  271. int com = cmd->hdr.command;
  272. ipa_name = qeth_get_ipa_cmd_name(com);
  273. if (rc)
  274. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s returned x%X \"%s\"\n",
  275. ipa_name, com, QETH_CARD_IFNAME(card),
  276. rc, qeth_get_ipa_msg(rc));
  277. else
  278. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s succeeded\n",
  279. ipa_name, com, QETH_CARD_IFNAME(card));
  280. }
  281. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  282. struct qeth_cmd_buffer *iob)
  283. {
  284. struct qeth_ipa_cmd *cmd = NULL;
  285. QETH_CARD_TEXT(card, 5, "chkipad");
  286. if (IS_IPA(iob->data)) {
  287. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  288. if (IS_IPA_REPLY(cmd)) {
  289. if (cmd->hdr.command != IPA_CMD_SETCCID &&
  290. cmd->hdr.command != IPA_CMD_DELCCID &&
  291. cmd->hdr.command != IPA_CMD_MODCCID &&
  292. cmd->hdr.command != IPA_CMD_SET_DIAG_ASS)
  293. qeth_issue_ipa_msg(cmd,
  294. cmd->hdr.return_code, card);
  295. return cmd;
  296. } else {
  297. switch (cmd->hdr.command) {
  298. case IPA_CMD_STOPLAN:
  299. dev_warn(&card->gdev->dev,
  300. "The link for interface %s on CHPID"
  301. " 0x%X failed\n",
  302. QETH_CARD_IFNAME(card),
  303. card->info.chpid);
  304. card->lan_online = 0;
  305. if (card->dev && netif_carrier_ok(card->dev))
  306. netif_carrier_off(card->dev);
  307. return NULL;
  308. case IPA_CMD_STARTLAN:
  309. dev_info(&card->gdev->dev,
  310. "The link for %s on CHPID 0x%X has"
  311. " been restored\n",
  312. QETH_CARD_IFNAME(card),
  313. card->info.chpid);
  314. netif_carrier_on(card->dev);
  315. card->lan_online = 1;
  316. qeth_schedule_recovery(card);
  317. return NULL;
  318. case IPA_CMD_MODCCID:
  319. return cmd;
  320. case IPA_CMD_REGISTER_LOCAL_ADDR:
  321. QETH_CARD_TEXT(card, 3, "irla");
  322. break;
  323. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  324. QETH_CARD_TEXT(card, 3, "urla");
  325. break;
  326. default:
  327. QETH_DBF_MESSAGE(2, "Received data is IPA "
  328. "but not a reply!\n");
  329. break;
  330. }
  331. }
  332. }
  333. return cmd;
  334. }
  335. void qeth_clear_ipacmd_list(struct qeth_card *card)
  336. {
  337. struct qeth_reply *reply, *r;
  338. unsigned long flags;
  339. QETH_CARD_TEXT(card, 4, "clipalst");
  340. spin_lock_irqsave(&card->lock, flags);
  341. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  342. qeth_get_reply(reply);
  343. reply->rc = -EIO;
  344. atomic_inc(&reply->received);
  345. list_del_init(&reply->list);
  346. wake_up(&reply->wait_q);
  347. qeth_put_reply(reply);
  348. }
  349. spin_unlock_irqrestore(&card->lock, flags);
  350. }
  351. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  352. static int qeth_check_idx_response(struct qeth_card *card,
  353. unsigned char *buffer)
  354. {
  355. if (!buffer)
  356. return 0;
  357. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  358. if ((buffer[2] & 0xc0) == 0xc0) {
  359. QETH_DBF_MESSAGE(2, "received an IDX TERMINATE "
  360. "with cause code 0x%02x%s\n",
  361. buffer[4],
  362. ((buffer[4] == 0x22) ?
  363. " -- try another portname" : ""));
  364. QETH_CARD_TEXT(card, 2, "ckidxres");
  365. QETH_CARD_TEXT(card, 2, " idxterm");
  366. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  367. if (buffer[4] == 0xf6) {
  368. dev_err(&card->gdev->dev,
  369. "The qeth device is not configured "
  370. "for the OSI layer required by z/VM\n");
  371. return -EPERM;
  372. }
  373. return -EIO;
  374. }
  375. return 0;
  376. }
  377. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  378. __u32 len)
  379. {
  380. struct qeth_card *card;
  381. card = CARD_FROM_CDEV(channel->ccwdev);
  382. QETH_CARD_TEXT(card, 4, "setupccw");
  383. if (channel == &card->read)
  384. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  385. else
  386. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  387. channel->ccw.count = len;
  388. channel->ccw.cda = (__u32) __pa(iob);
  389. }
  390. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  391. {
  392. __u8 index;
  393. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "getbuff");
  394. index = channel->io_buf_no;
  395. do {
  396. if (channel->iob[index].state == BUF_STATE_FREE) {
  397. channel->iob[index].state = BUF_STATE_LOCKED;
  398. channel->io_buf_no = (channel->io_buf_no + 1) %
  399. QETH_CMD_BUFFER_NO;
  400. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  401. return channel->iob + index;
  402. }
  403. index = (index + 1) % QETH_CMD_BUFFER_NO;
  404. } while (index != channel->io_buf_no);
  405. return NULL;
  406. }
  407. void qeth_release_buffer(struct qeth_channel *channel,
  408. struct qeth_cmd_buffer *iob)
  409. {
  410. unsigned long flags;
  411. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "relbuff");
  412. spin_lock_irqsave(&channel->iob_lock, flags);
  413. memset(iob->data, 0, QETH_BUFSIZE);
  414. iob->state = BUF_STATE_FREE;
  415. iob->callback = qeth_send_control_data_cb;
  416. iob->rc = 0;
  417. spin_unlock_irqrestore(&channel->iob_lock, flags);
  418. }
  419. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  420. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  421. {
  422. struct qeth_cmd_buffer *buffer = NULL;
  423. unsigned long flags;
  424. spin_lock_irqsave(&channel->iob_lock, flags);
  425. buffer = __qeth_get_buffer(channel);
  426. spin_unlock_irqrestore(&channel->iob_lock, flags);
  427. return buffer;
  428. }
  429. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  430. {
  431. struct qeth_cmd_buffer *buffer;
  432. wait_event(channel->wait_q,
  433. ((buffer = qeth_get_buffer(channel)) != NULL));
  434. return buffer;
  435. }
  436. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  437. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  438. {
  439. int cnt;
  440. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  441. qeth_release_buffer(channel, &channel->iob[cnt]);
  442. channel->buf_no = 0;
  443. channel->io_buf_no = 0;
  444. }
  445. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  446. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  447. struct qeth_cmd_buffer *iob)
  448. {
  449. struct qeth_card *card;
  450. struct qeth_reply *reply, *r;
  451. struct qeth_ipa_cmd *cmd;
  452. unsigned long flags;
  453. int keep_reply;
  454. int rc = 0;
  455. card = CARD_FROM_CDEV(channel->ccwdev);
  456. QETH_CARD_TEXT(card, 4, "sndctlcb");
  457. rc = qeth_check_idx_response(card, iob->data);
  458. switch (rc) {
  459. case 0:
  460. break;
  461. case -EIO:
  462. qeth_clear_ipacmd_list(card);
  463. qeth_schedule_recovery(card);
  464. default:
  465. goto out;
  466. }
  467. cmd = qeth_check_ipa_data(card, iob);
  468. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  469. goto out;
  470. /*in case of OSN : check if cmd is set */
  471. if (card->info.type == QETH_CARD_TYPE_OSN &&
  472. cmd &&
  473. cmd->hdr.command != IPA_CMD_STARTLAN &&
  474. card->osn_info.assist_cb != NULL) {
  475. card->osn_info.assist_cb(card->dev, cmd);
  476. goto out;
  477. }
  478. spin_lock_irqsave(&card->lock, flags);
  479. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  480. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  481. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  482. qeth_get_reply(reply);
  483. list_del_init(&reply->list);
  484. spin_unlock_irqrestore(&card->lock, flags);
  485. keep_reply = 0;
  486. if (reply->callback != NULL) {
  487. if (cmd) {
  488. reply->offset = (__u16)((char *)cmd -
  489. (char *)iob->data);
  490. keep_reply = reply->callback(card,
  491. reply,
  492. (unsigned long)cmd);
  493. } else
  494. keep_reply = reply->callback(card,
  495. reply,
  496. (unsigned long)iob);
  497. }
  498. if (cmd)
  499. reply->rc = (u16) cmd->hdr.return_code;
  500. else if (iob->rc)
  501. reply->rc = iob->rc;
  502. if (keep_reply) {
  503. spin_lock_irqsave(&card->lock, flags);
  504. list_add_tail(&reply->list,
  505. &card->cmd_waiter_list);
  506. spin_unlock_irqrestore(&card->lock, flags);
  507. } else {
  508. atomic_inc(&reply->received);
  509. wake_up(&reply->wait_q);
  510. }
  511. qeth_put_reply(reply);
  512. goto out;
  513. }
  514. }
  515. spin_unlock_irqrestore(&card->lock, flags);
  516. out:
  517. memcpy(&card->seqno.pdu_hdr_ack,
  518. QETH_PDU_HEADER_SEQ_NO(iob->data),
  519. QETH_SEQ_NO_LENGTH);
  520. qeth_release_buffer(channel, iob);
  521. }
  522. static int qeth_setup_channel(struct qeth_channel *channel)
  523. {
  524. int cnt;
  525. QETH_DBF_TEXT(SETUP, 2, "setupch");
  526. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  527. channel->iob[cnt].data =
  528. kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  529. if (channel->iob[cnt].data == NULL)
  530. break;
  531. channel->iob[cnt].state = BUF_STATE_FREE;
  532. channel->iob[cnt].channel = channel;
  533. channel->iob[cnt].callback = qeth_send_control_data_cb;
  534. channel->iob[cnt].rc = 0;
  535. }
  536. if (cnt < QETH_CMD_BUFFER_NO) {
  537. while (cnt-- > 0)
  538. kfree(channel->iob[cnt].data);
  539. return -ENOMEM;
  540. }
  541. channel->buf_no = 0;
  542. channel->io_buf_no = 0;
  543. atomic_set(&channel->irq_pending, 0);
  544. spin_lock_init(&channel->iob_lock);
  545. init_waitqueue_head(&channel->wait_q);
  546. return 0;
  547. }
  548. static int qeth_set_thread_start_bit(struct qeth_card *card,
  549. unsigned long thread)
  550. {
  551. unsigned long flags;
  552. spin_lock_irqsave(&card->thread_mask_lock, flags);
  553. if (!(card->thread_allowed_mask & thread) ||
  554. (card->thread_start_mask & thread)) {
  555. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  556. return -EPERM;
  557. }
  558. card->thread_start_mask |= thread;
  559. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  560. return 0;
  561. }
  562. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  563. {
  564. unsigned long flags;
  565. spin_lock_irqsave(&card->thread_mask_lock, flags);
  566. card->thread_start_mask &= ~thread;
  567. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  568. wake_up(&card->wait_q);
  569. }
  570. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  571. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  572. {
  573. unsigned long flags;
  574. spin_lock_irqsave(&card->thread_mask_lock, flags);
  575. card->thread_running_mask &= ~thread;
  576. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  577. wake_up(&card->wait_q);
  578. }
  579. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  580. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  581. {
  582. unsigned long flags;
  583. int rc = 0;
  584. spin_lock_irqsave(&card->thread_mask_lock, flags);
  585. if (card->thread_start_mask & thread) {
  586. if ((card->thread_allowed_mask & thread) &&
  587. !(card->thread_running_mask & thread)) {
  588. rc = 1;
  589. card->thread_start_mask &= ~thread;
  590. card->thread_running_mask |= thread;
  591. } else
  592. rc = -EPERM;
  593. }
  594. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  595. return rc;
  596. }
  597. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  598. {
  599. int rc = 0;
  600. wait_event(card->wait_q,
  601. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  602. return rc;
  603. }
  604. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  605. void qeth_schedule_recovery(struct qeth_card *card)
  606. {
  607. QETH_CARD_TEXT(card, 2, "startrec");
  608. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  609. schedule_work(&card->kernel_thread_starter);
  610. }
  611. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  612. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  613. {
  614. int dstat, cstat;
  615. char *sense;
  616. struct qeth_card *card;
  617. sense = (char *) irb->ecw;
  618. cstat = irb->scsw.cmd.cstat;
  619. dstat = irb->scsw.cmd.dstat;
  620. card = CARD_FROM_CDEV(cdev);
  621. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  622. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  623. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  624. QETH_CARD_TEXT(card, 2, "CGENCHK");
  625. dev_warn(&cdev->dev, "The qeth device driver "
  626. "failed to recover an error on the device\n");
  627. QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x\n",
  628. dev_name(&cdev->dev), dstat, cstat);
  629. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  630. 16, 1, irb, 64, 1);
  631. return 1;
  632. }
  633. if (dstat & DEV_STAT_UNIT_CHECK) {
  634. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  635. SENSE_RESETTING_EVENT_FLAG) {
  636. QETH_CARD_TEXT(card, 2, "REVIND");
  637. return 1;
  638. }
  639. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  640. SENSE_COMMAND_REJECT_FLAG) {
  641. QETH_CARD_TEXT(card, 2, "CMDREJi");
  642. return 1;
  643. }
  644. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  645. QETH_CARD_TEXT(card, 2, "AFFE");
  646. return 1;
  647. }
  648. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  649. QETH_CARD_TEXT(card, 2, "ZEROSEN");
  650. return 0;
  651. }
  652. QETH_CARD_TEXT(card, 2, "DGENCHK");
  653. return 1;
  654. }
  655. return 0;
  656. }
  657. static long __qeth_check_irb_error(struct ccw_device *cdev,
  658. unsigned long intparm, struct irb *irb)
  659. {
  660. struct qeth_card *card;
  661. card = CARD_FROM_CDEV(cdev);
  662. if (!IS_ERR(irb))
  663. return 0;
  664. switch (PTR_ERR(irb)) {
  665. case -EIO:
  666. QETH_DBF_MESSAGE(2, "%s i/o-error on device\n",
  667. dev_name(&cdev->dev));
  668. QETH_CARD_TEXT(card, 2, "ckirberr");
  669. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  670. break;
  671. case -ETIMEDOUT:
  672. dev_warn(&cdev->dev, "A hardware operation timed out"
  673. " on the device\n");
  674. QETH_CARD_TEXT(card, 2, "ckirberr");
  675. QETH_CARD_TEXT_(card, 2, " rc%d", -ETIMEDOUT);
  676. if (intparm == QETH_RCD_PARM) {
  677. if (card && (card->data.ccwdev == cdev)) {
  678. card->data.state = CH_STATE_DOWN;
  679. wake_up(&card->wait_q);
  680. }
  681. }
  682. break;
  683. default:
  684. QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n",
  685. dev_name(&cdev->dev), PTR_ERR(irb));
  686. QETH_CARD_TEXT(card, 2, "ckirberr");
  687. QETH_CARD_TEXT(card, 2, " rc???");
  688. }
  689. return PTR_ERR(irb);
  690. }
  691. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  692. struct irb *irb)
  693. {
  694. int rc;
  695. int cstat, dstat;
  696. struct qeth_cmd_buffer *buffer;
  697. struct qeth_channel *channel;
  698. struct qeth_card *card;
  699. struct qeth_cmd_buffer *iob;
  700. __u8 index;
  701. if (__qeth_check_irb_error(cdev, intparm, irb))
  702. return;
  703. cstat = irb->scsw.cmd.cstat;
  704. dstat = irb->scsw.cmd.dstat;
  705. card = CARD_FROM_CDEV(cdev);
  706. if (!card)
  707. return;
  708. QETH_CARD_TEXT(card, 5, "irq");
  709. if (card->read.ccwdev == cdev) {
  710. channel = &card->read;
  711. QETH_CARD_TEXT(card, 5, "read");
  712. } else if (card->write.ccwdev == cdev) {
  713. channel = &card->write;
  714. QETH_CARD_TEXT(card, 5, "write");
  715. } else {
  716. channel = &card->data;
  717. QETH_CARD_TEXT(card, 5, "data");
  718. }
  719. atomic_set(&channel->irq_pending, 0);
  720. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  721. channel->state = CH_STATE_STOPPED;
  722. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  723. channel->state = CH_STATE_HALTED;
  724. /*let's wake up immediately on data channel*/
  725. if ((channel == &card->data) && (intparm != 0) &&
  726. (intparm != QETH_RCD_PARM))
  727. goto out;
  728. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  729. QETH_CARD_TEXT(card, 6, "clrchpar");
  730. /* we don't have to handle this further */
  731. intparm = 0;
  732. }
  733. if (intparm == QETH_HALT_CHANNEL_PARM) {
  734. QETH_CARD_TEXT(card, 6, "hltchpar");
  735. /* we don't have to handle this further */
  736. intparm = 0;
  737. }
  738. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  739. (dstat & DEV_STAT_UNIT_CHECK) ||
  740. (cstat)) {
  741. if (irb->esw.esw0.erw.cons) {
  742. dev_warn(&channel->ccwdev->dev,
  743. "The qeth device driver failed to recover "
  744. "an error on the device\n");
  745. QETH_DBF_MESSAGE(2, "%s sense data available. cstat "
  746. "0x%X dstat 0x%X\n",
  747. dev_name(&channel->ccwdev->dev), cstat, dstat);
  748. print_hex_dump(KERN_WARNING, "qeth: irb ",
  749. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  750. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  751. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  752. }
  753. if (intparm == QETH_RCD_PARM) {
  754. channel->state = CH_STATE_DOWN;
  755. goto out;
  756. }
  757. rc = qeth_get_problem(cdev, irb);
  758. if (rc) {
  759. qeth_clear_ipacmd_list(card);
  760. qeth_schedule_recovery(card);
  761. goto out;
  762. }
  763. }
  764. if (intparm == QETH_RCD_PARM) {
  765. channel->state = CH_STATE_RCD_DONE;
  766. goto out;
  767. }
  768. if (intparm) {
  769. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  770. buffer->state = BUF_STATE_PROCESSED;
  771. }
  772. if (channel == &card->data)
  773. return;
  774. if (channel == &card->read &&
  775. channel->state == CH_STATE_UP)
  776. qeth_issue_next_read(card);
  777. iob = channel->iob;
  778. index = channel->buf_no;
  779. while (iob[index].state == BUF_STATE_PROCESSED) {
  780. if (iob[index].callback != NULL)
  781. iob[index].callback(channel, iob + index);
  782. index = (index + 1) % QETH_CMD_BUFFER_NO;
  783. }
  784. channel->buf_no = index;
  785. out:
  786. wake_up(&card->wait_q);
  787. return;
  788. }
  789. static void __qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  790. struct qeth_qdio_out_buffer *buf, unsigned int qeth_skip_skb)
  791. {
  792. int i;
  793. struct sk_buff *skb;
  794. /* is PCI flag set on buffer? */
  795. if (buf->buffer->element[0].flags & 0x40)
  796. atomic_dec(&queue->set_pci_flags_count);
  797. if (!qeth_skip_skb) {
  798. skb = skb_dequeue(&buf->skb_list);
  799. while (skb) {
  800. atomic_dec(&skb->users);
  801. dev_kfree_skb_any(skb);
  802. skb = skb_dequeue(&buf->skb_list);
  803. }
  804. }
  805. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  806. if (buf->buffer->element[i].addr && buf->is_header[i])
  807. kmem_cache_free(qeth_core_header_cache,
  808. buf->buffer->element[i].addr);
  809. buf->is_header[i] = 0;
  810. buf->buffer->element[i].length = 0;
  811. buf->buffer->element[i].addr = NULL;
  812. buf->buffer->element[i].flags = 0;
  813. }
  814. buf->buffer->element[15].flags = 0;
  815. buf->next_element_to_fill = 0;
  816. atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
  817. }
  818. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  819. struct qeth_qdio_out_buffer *buf)
  820. {
  821. __qeth_clear_output_buffer(queue, buf, 0);
  822. }
  823. void qeth_clear_qdio_buffers(struct qeth_card *card)
  824. {
  825. int i, j;
  826. QETH_CARD_TEXT(card, 2, "clearqdbf");
  827. /* clear outbound buffers to free skbs */
  828. for (i = 0; i < card->qdio.no_out_queues; ++i)
  829. if (card->qdio.out_qs[i]) {
  830. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  831. qeth_clear_output_buffer(card->qdio.out_qs[i],
  832. &card->qdio.out_qs[i]->bufs[j]);
  833. }
  834. }
  835. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  836. static void qeth_free_buffer_pool(struct qeth_card *card)
  837. {
  838. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  839. int i = 0;
  840. list_for_each_entry_safe(pool_entry, tmp,
  841. &card->qdio.init_pool.entry_list, init_list){
  842. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  843. free_page((unsigned long)pool_entry->elements[i]);
  844. list_del(&pool_entry->init_list);
  845. kfree(pool_entry);
  846. }
  847. }
  848. static void qeth_free_qdio_buffers(struct qeth_card *card)
  849. {
  850. int i, j;
  851. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  852. QETH_QDIO_UNINITIALIZED)
  853. return;
  854. kfree(card->qdio.in_q);
  855. card->qdio.in_q = NULL;
  856. /* inbound buffer pool */
  857. qeth_free_buffer_pool(card);
  858. /* free outbound qdio_qs */
  859. if (card->qdio.out_qs) {
  860. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  861. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  862. qeth_clear_output_buffer(card->qdio.out_qs[i],
  863. &card->qdio.out_qs[i]->bufs[j]);
  864. kfree(card->qdio.out_qs[i]);
  865. }
  866. kfree(card->qdio.out_qs);
  867. card->qdio.out_qs = NULL;
  868. }
  869. }
  870. static void qeth_clean_channel(struct qeth_channel *channel)
  871. {
  872. int cnt;
  873. QETH_DBF_TEXT(SETUP, 2, "freech");
  874. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  875. kfree(channel->iob[cnt].data);
  876. }
  877. static void qeth_get_channel_path_desc(struct qeth_card *card)
  878. {
  879. struct ccw_device *ccwdev;
  880. struct channelPath_dsc {
  881. u8 flags;
  882. u8 lsn;
  883. u8 desc;
  884. u8 chpid;
  885. u8 swla;
  886. u8 zeroes;
  887. u8 chla;
  888. u8 chpp;
  889. } *chp_dsc;
  890. QETH_DBF_TEXT(SETUP, 2, "chp_desc");
  891. ccwdev = card->data.ccwdev;
  892. chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
  893. if (chp_dsc != NULL) {
  894. /* CHPP field bit 6 == 1 -> single queue */
  895. if ((chp_dsc->chpp & 0x02) == 0x02)
  896. card->qdio.no_out_queues = 1;
  897. card->info.func_level = 0x4100 + chp_dsc->desc;
  898. kfree(chp_dsc);
  899. }
  900. if (card->qdio.no_out_queues == 1) {
  901. card->qdio.default_out_queue = 0;
  902. dev_info(&card->gdev->dev,
  903. "Priority Queueing not supported\n");
  904. }
  905. QETH_DBF_TEXT_(SETUP, 2, "nr:%x", card->qdio.no_out_queues);
  906. QETH_DBF_TEXT_(SETUP, 2, "lvl:%02x", card->info.func_level);
  907. return;
  908. }
  909. static void qeth_init_qdio_info(struct qeth_card *card)
  910. {
  911. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  912. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  913. /* inbound */
  914. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  915. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  916. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  917. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  918. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  919. }
  920. static void qeth_set_intial_options(struct qeth_card *card)
  921. {
  922. card->options.route4.type = NO_ROUTER;
  923. card->options.route6.type = NO_ROUTER;
  924. card->options.checksum_type = QETH_CHECKSUM_DEFAULT;
  925. card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
  926. card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
  927. card->options.fake_broadcast = 0;
  928. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  929. card->options.performance_stats = 0;
  930. card->options.rx_sg_cb = QETH_RX_SG_CB;
  931. card->options.isolation = ISOLATION_MODE_NONE;
  932. }
  933. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  934. {
  935. unsigned long flags;
  936. int rc = 0;
  937. spin_lock_irqsave(&card->thread_mask_lock, flags);
  938. QETH_CARD_TEXT_(card, 4, " %02x%02x%02x",
  939. (u8) card->thread_start_mask,
  940. (u8) card->thread_allowed_mask,
  941. (u8) card->thread_running_mask);
  942. rc = (card->thread_start_mask & thread);
  943. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  944. return rc;
  945. }
  946. static void qeth_start_kernel_thread(struct work_struct *work)
  947. {
  948. struct qeth_card *card = container_of(work, struct qeth_card,
  949. kernel_thread_starter);
  950. QETH_CARD_TEXT(card , 2, "strthrd");
  951. if (card->read.state != CH_STATE_UP &&
  952. card->write.state != CH_STATE_UP)
  953. return;
  954. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
  955. kthread_run(card->discipline.recover, (void *) card,
  956. "qeth_recover");
  957. }
  958. static int qeth_setup_card(struct qeth_card *card)
  959. {
  960. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  961. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  962. card->read.state = CH_STATE_DOWN;
  963. card->write.state = CH_STATE_DOWN;
  964. card->data.state = CH_STATE_DOWN;
  965. card->state = CARD_STATE_DOWN;
  966. card->lan_online = 0;
  967. card->use_hard_stop = 0;
  968. card->dev = NULL;
  969. spin_lock_init(&card->vlanlock);
  970. spin_lock_init(&card->mclock);
  971. card->vlangrp = NULL;
  972. spin_lock_init(&card->lock);
  973. spin_lock_init(&card->ip_lock);
  974. spin_lock_init(&card->thread_mask_lock);
  975. mutex_init(&card->conf_mutex);
  976. card->thread_start_mask = 0;
  977. card->thread_allowed_mask = 0;
  978. card->thread_running_mask = 0;
  979. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  980. INIT_LIST_HEAD(&card->ip_list);
  981. INIT_LIST_HEAD(card->ip_tbd_list);
  982. INIT_LIST_HEAD(&card->cmd_waiter_list);
  983. init_waitqueue_head(&card->wait_q);
  984. /* intial options */
  985. qeth_set_intial_options(card);
  986. /* IP address takeover */
  987. INIT_LIST_HEAD(&card->ipato.entries);
  988. card->ipato.enabled = 0;
  989. card->ipato.invert4 = 0;
  990. card->ipato.invert6 = 0;
  991. /* init QDIO stuff */
  992. qeth_init_qdio_info(card);
  993. return 0;
  994. }
  995. static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
  996. {
  997. struct qeth_card *card = container_of(slr, struct qeth_card,
  998. qeth_service_level);
  999. if (card->info.mcl_level[0])
  1000. seq_printf(m, "qeth: %s firmware level %s\n",
  1001. CARD_BUS_ID(card), card->info.mcl_level);
  1002. }
  1003. static struct qeth_card *qeth_alloc_card(void)
  1004. {
  1005. struct qeth_card *card;
  1006. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1007. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1008. if (!card)
  1009. goto out;
  1010. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1011. card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
  1012. if (!card->ip_tbd_list) {
  1013. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1014. goto out_card;
  1015. }
  1016. if (qeth_setup_channel(&card->read))
  1017. goto out_ip;
  1018. if (qeth_setup_channel(&card->write))
  1019. goto out_channel;
  1020. card->options.layer2 = -1;
  1021. card->qeth_service_level.seq_print = qeth_core_sl_print;
  1022. register_service_level(&card->qeth_service_level);
  1023. return card;
  1024. out_channel:
  1025. qeth_clean_channel(&card->read);
  1026. out_ip:
  1027. kfree(card->ip_tbd_list);
  1028. out_card:
  1029. kfree(card);
  1030. out:
  1031. return NULL;
  1032. }
  1033. static int qeth_determine_card_type(struct qeth_card *card)
  1034. {
  1035. int i = 0;
  1036. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1037. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1038. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1039. while (known_devices[i][QETH_DEV_MODEL_IND]) {
  1040. if ((CARD_RDEV(card)->id.dev_type ==
  1041. known_devices[i][QETH_DEV_TYPE_IND]) &&
  1042. (CARD_RDEV(card)->id.dev_model ==
  1043. known_devices[i][QETH_DEV_MODEL_IND])) {
  1044. card->info.type = known_devices[i][QETH_DEV_MODEL_IND];
  1045. card->qdio.no_out_queues =
  1046. known_devices[i][QETH_QUEUE_NO_IND];
  1047. card->info.is_multicast_different =
  1048. known_devices[i][QETH_MULTICAST_IND];
  1049. qeth_get_channel_path_desc(card);
  1050. return 0;
  1051. }
  1052. i++;
  1053. }
  1054. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1055. dev_err(&card->gdev->dev, "The adapter hardware is of an "
  1056. "unknown type\n");
  1057. return -ENOENT;
  1058. }
  1059. static int qeth_clear_channel(struct qeth_channel *channel)
  1060. {
  1061. unsigned long flags;
  1062. struct qeth_card *card;
  1063. int rc;
  1064. card = CARD_FROM_CDEV(channel->ccwdev);
  1065. QETH_CARD_TEXT(card, 3, "clearch");
  1066. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1067. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1068. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1069. if (rc)
  1070. return rc;
  1071. rc = wait_event_interruptible_timeout(card->wait_q,
  1072. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1073. if (rc == -ERESTARTSYS)
  1074. return rc;
  1075. if (channel->state != CH_STATE_STOPPED)
  1076. return -ETIME;
  1077. channel->state = CH_STATE_DOWN;
  1078. return 0;
  1079. }
  1080. static int qeth_halt_channel(struct qeth_channel *channel)
  1081. {
  1082. unsigned long flags;
  1083. struct qeth_card *card;
  1084. int rc;
  1085. card = CARD_FROM_CDEV(channel->ccwdev);
  1086. QETH_CARD_TEXT(card, 3, "haltch");
  1087. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1088. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1089. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1090. if (rc)
  1091. return rc;
  1092. rc = wait_event_interruptible_timeout(card->wait_q,
  1093. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1094. if (rc == -ERESTARTSYS)
  1095. return rc;
  1096. if (channel->state != CH_STATE_HALTED)
  1097. return -ETIME;
  1098. return 0;
  1099. }
  1100. static int qeth_halt_channels(struct qeth_card *card)
  1101. {
  1102. int rc1 = 0, rc2 = 0, rc3 = 0;
  1103. QETH_CARD_TEXT(card, 3, "haltchs");
  1104. rc1 = qeth_halt_channel(&card->read);
  1105. rc2 = qeth_halt_channel(&card->write);
  1106. rc3 = qeth_halt_channel(&card->data);
  1107. if (rc1)
  1108. return rc1;
  1109. if (rc2)
  1110. return rc2;
  1111. return rc3;
  1112. }
  1113. static int qeth_clear_channels(struct qeth_card *card)
  1114. {
  1115. int rc1 = 0, rc2 = 0, rc3 = 0;
  1116. QETH_CARD_TEXT(card, 3, "clearchs");
  1117. rc1 = qeth_clear_channel(&card->read);
  1118. rc2 = qeth_clear_channel(&card->write);
  1119. rc3 = qeth_clear_channel(&card->data);
  1120. if (rc1)
  1121. return rc1;
  1122. if (rc2)
  1123. return rc2;
  1124. return rc3;
  1125. }
  1126. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1127. {
  1128. int rc = 0;
  1129. QETH_CARD_TEXT(card, 3, "clhacrd");
  1130. if (halt)
  1131. rc = qeth_halt_channels(card);
  1132. if (rc)
  1133. return rc;
  1134. return qeth_clear_channels(card);
  1135. }
  1136. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1137. {
  1138. int rc = 0;
  1139. QETH_CARD_TEXT(card, 3, "qdioclr");
  1140. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1141. QETH_QDIO_CLEANING)) {
  1142. case QETH_QDIO_ESTABLISHED:
  1143. if (card->info.type == QETH_CARD_TYPE_IQD)
  1144. rc = qdio_shutdown(CARD_DDEV(card),
  1145. QDIO_FLAG_CLEANUP_USING_HALT);
  1146. else
  1147. rc = qdio_shutdown(CARD_DDEV(card),
  1148. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1149. if (rc)
  1150. QETH_CARD_TEXT_(card, 3, "1err%d", rc);
  1151. qdio_free(CARD_DDEV(card));
  1152. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1153. break;
  1154. case QETH_QDIO_CLEANING:
  1155. return rc;
  1156. default:
  1157. break;
  1158. }
  1159. rc = qeth_clear_halt_card(card, use_halt);
  1160. if (rc)
  1161. QETH_CARD_TEXT_(card, 3, "2err%d", rc);
  1162. card->state = CARD_STATE_DOWN;
  1163. return rc;
  1164. }
  1165. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1166. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1167. int *length)
  1168. {
  1169. struct ciw *ciw;
  1170. char *rcd_buf;
  1171. int ret;
  1172. struct qeth_channel *channel = &card->data;
  1173. unsigned long flags;
  1174. /*
  1175. * scan for RCD command in extended SenseID data
  1176. */
  1177. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1178. if (!ciw || ciw->cmd == 0)
  1179. return -EOPNOTSUPP;
  1180. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1181. if (!rcd_buf)
  1182. return -ENOMEM;
  1183. channel->ccw.cmd_code = ciw->cmd;
  1184. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1185. channel->ccw.count = ciw->count;
  1186. channel->ccw.flags = CCW_FLAG_SLI;
  1187. channel->state = CH_STATE_RCD;
  1188. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1189. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1190. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1191. QETH_RCD_TIMEOUT);
  1192. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1193. if (!ret)
  1194. wait_event(card->wait_q,
  1195. (channel->state == CH_STATE_RCD_DONE ||
  1196. channel->state == CH_STATE_DOWN));
  1197. if (channel->state == CH_STATE_DOWN)
  1198. ret = -EIO;
  1199. else
  1200. channel->state = CH_STATE_DOWN;
  1201. if (ret) {
  1202. kfree(rcd_buf);
  1203. *buffer = NULL;
  1204. *length = 0;
  1205. } else {
  1206. *length = ciw->count;
  1207. *buffer = rcd_buf;
  1208. }
  1209. return ret;
  1210. }
  1211. static void qeth_configure_unitaddr(struct qeth_card *card, char *prcd)
  1212. {
  1213. QETH_DBF_TEXT(SETUP, 2, "cfgunit");
  1214. card->info.chpid = prcd[30];
  1215. card->info.unit_addr2 = prcd[31];
  1216. card->info.cula = prcd[63];
  1217. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1218. (prcd[0x11] == _ascebc['M']));
  1219. }
  1220. static void qeth_configure_blkt_default(struct qeth_card *card, char *prcd)
  1221. {
  1222. QETH_DBF_TEXT(SETUP, 2, "cfgblkt");
  1223. if (prcd[74] == 0xF0 && prcd[75] == 0xF0 && prcd[76] == 0xF5) {
  1224. card->info.blkt.time_total = 250;
  1225. card->info.blkt.inter_packet = 5;
  1226. card->info.blkt.inter_packet_jumbo = 15;
  1227. } else {
  1228. card->info.blkt.time_total = 0;
  1229. card->info.blkt.inter_packet = 0;
  1230. card->info.blkt.inter_packet_jumbo = 0;
  1231. }
  1232. }
  1233. static void qeth_init_tokens(struct qeth_card *card)
  1234. {
  1235. card->token.issuer_rm_w = 0x00010103UL;
  1236. card->token.cm_filter_w = 0x00010108UL;
  1237. card->token.cm_connection_w = 0x0001010aUL;
  1238. card->token.ulp_filter_w = 0x0001010bUL;
  1239. card->token.ulp_connection_w = 0x0001010dUL;
  1240. }
  1241. static void qeth_init_func_level(struct qeth_card *card)
  1242. {
  1243. switch (card->info.type) {
  1244. case QETH_CARD_TYPE_IQD:
  1245. if (card->ipato.enabled)
  1246. card->info.func_level =
  1247. QETH_IDX_FUNC_LEVEL_IQD_ENA_IPAT;
  1248. else
  1249. card->info.func_level =
  1250. QETH_IDX_FUNC_LEVEL_IQD_DIS_IPAT;
  1251. break;
  1252. case QETH_CARD_TYPE_OSD:
  1253. case QETH_CARD_TYPE_OSN:
  1254. card->info.func_level = QETH_IDX_FUNC_LEVEL_OSD;
  1255. break;
  1256. default:
  1257. break;
  1258. }
  1259. }
  1260. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1261. void (*idx_reply_cb)(struct qeth_channel *,
  1262. struct qeth_cmd_buffer *))
  1263. {
  1264. struct qeth_cmd_buffer *iob;
  1265. unsigned long flags;
  1266. int rc;
  1267. struct qeth_card *card;
  1268. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1269. card = CARD_FROM_CDEV(channel->ccwdev);
  1270. iob = qeth_get_buffer(channel);
  1271. iob->callback = idx_reply_cb;
  1272. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1273. channel->ccw.count = QETH_BUFSIZE;
  1274. channel->ccw.cda = (__u32) __pa(iob->data);
  1275. wait_event(card->wait_q,
  1276. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1277. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1278. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1279. rc = ccw_device_start(channel->ccwdev,
  1280. &channel->ccw, (addr_t) iob, 0, 0);
  1281. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1282. if (rc) {
  1283. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1284. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1285. atomic_set(&channel->irq_pending, 0);
  1286. wake_up(&card->wait_q);
  1287. return rc;
  1288. }
  1289. rc = wait_event_interruptible_timeout(card->wait_q,
  1290. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1291. if (rc == -ERESTARTSYS)
  1292. return rc;
  1293. if (channel->state != CH_STATE_UP) {
  1294. rc = -ETIME;
  1295. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1296. qeth_clear_cmd_buffers(channel);
  1297. } else
  1298. rc = 0;
  1299. return rc;
  1300. }
  1301. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1302. void (*idx_reply_cb)(struct qeth_channel *,
  1303. struct qeth_cmd_buffer *))
  1304. {
  1305. struct qeth_card *card;
  1306. struct qeth_cmd_buffer *iob;
  1307. unsigned long flags;
  1308. __u16 temp;
  1309. __u8 tmp;
  1310. int rc;
  1311. struct ccw_dev_id temp_devid;
  1312. card = CARD_FROM_CDEV(channel->ccwdev);
  1313. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1314. iob = qeth_get_buffer(channel);
  1315. iob->callback = idx_reply_cb;
  1316. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1317. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1318. channel->ccw.cda = (__u32) __pa(iob->data);
  1319. if (channel == &card->write) {
  1320. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1321. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1322. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1323. card->seqno.trans_hdr++;
  1324. } else {
  1325. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1326. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1327. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1328. }
  1329. tmp = ((__u8)card->info.portno) | 0x80;
  1330. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1331. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1332. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1333. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1334. &card->info.func_level, sizeof(__u16));
  1335. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1336. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1337. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1338. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1339. wait_event(card->wait_q,
  1340. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1341. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1342. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1343. rc = ccw_device_start(channel->ccwdev,
  1344. &channel->ccw, (addr_t) iob, 0, 0);
  1345. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1346. if (rc) {
  1347. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1348. rc);
  1349. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1350. atomic_set(&channel->irq_pending, 0);
  1351. wake_up(&card->wait_q);
  1352. return rc;
  1353. }
  1354. rc = wait_event_interruptible_timeout(card->wait_q,
  1355. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1356. if (rc == -ERESTARTSYS)
  1357. return rc;
  1358. if (channel->state != CH_STATE_ACTIVATING) {
  1359. dev_warn(&channel->ccwdev->dev, "The qeth device driver"
  1360. " failed to recover an error on the device\n");
  1361. QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n",
  1362. dev_name(&channel->ccwdev->dev));
  1363. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1364. qeth_clear_cmd_buffers(channel);
  1365. return -ETIME;
  1366. }
  1367. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1368. }
  1369. static int qeth_peer_func_level(int level)
  1370. {
  1371. if ((level & 0xff) == 8)
  1372. return (level & 0xff) + 0x400;
  1373. if (((level >> 8) & 3) == 1)
  1374. return (level & 0xff) + 0x200;
  1375. return level;
  1376. }
  1377. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1378. struct qeth_cmd_buffer *iob)
  1379. {
  1380. struct qeth_card *card;
  1381. __u16 temp;
  1382. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1383. if (channel->state == CH_STATE_DOWN) {
  1384. channel->state = CH_STATE_ACTIVATING;
  1385. goto out;
  1386. }
  1387. card = CARD_FROM_CDEV(channel->ccwdev);
  1388. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1389. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == QETH_IDX_ACT_ERR_EXCL)
  1390. dev_err(&card->write.ccwdev->dev,
  1391. "The adapter is used exclusively by another "
  1392. "host\n");
  1393. else
  1394. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:"
  1395. " negative reply\n",
  1396. dev_name(&card->write.ccwdev->dev));
  1397. goto out;
  1398. }
  1399. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1400. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1401. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: "
  1402. "function level mismatch (sent: 0x%x, received: "
  1403. "0x%x)\n", dev_name(&card->write.ccwdev->dev),
  1404. card->info.func_level, temp);
  1405. goto out;
  1406. }
  1407. channel->state = CH_STATE_UP;
  1408. out:
  1409. qeth_release_buffer(channel, iob);
  1410. }
  1411. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1412. struct qeth_cmd_buffer *iob)
  1413. {
  1414. struct qeth_card *card;
  1415. __u16 temp;
  1416. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1417. if (channel->state == CH_STATE_DOWN) {
  1418. channel->state = CH_STATE_ACTIVATING;
  1419. goto out;
  1420. }
  1421. card = CARD_FROM_CDEV(channel->ccwdev);
  1422. if (qeth_check_idx_response(card, iob->data))
  1423. goto out;
  1424. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1425. switch (QETH_IDX_ACT_CAUSE_CODE(iob->data)) {
  1426. case QETH_IDX_ACT_ERR_EXCL:
  1427. dev_err(&card->write.ccwdev->dev,
  1428. "The adapter is used exclusively by another "
  1429. "host\n");
  1430. break;
  1431. case QETH_IDX_ACT_ERR_AUTH:
  1432. dev_err(&card->read.ccwdev->dev,
  1433. "Setting the device online failed because of "
  1434. "insufficient LPAR authorization\n");
  1435. break;
  1436. default:
  1437. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:"
  1438. " negative reply\n",
  1439. dev_name(&card->read.ccwdev->dev));
  1440. }
  1441. goto out;
  1442. }
  1443. /**
  1444. * * temporary fix for microcode bug
  1445. * * to revert it,replace OR by AND
  1446. * */
  1447. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1448. (card->info.type == QETH_CARD_TYPE_OSD))
  1449. card->info.portname_required = 1;
  1450. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1451. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1452. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function "
  1453. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1454. dev_name(&card->read.ccwdev->dev),
  1455. card->info.func_level, temp);
  1456. goto out;
  1457. }
  1458. memcpy(&card->token.issuer_rm_r,
  1459. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1460. QETH_MPC_TOKEN_LENGTH);
  1461. memcpy(&card->info.mcl_level[0],
  1462. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1463. channel->state = CH_STATE_UP;
  1464. out:
  1465. qeth_release_buffer(channel, iob);
  1466. }
  1467. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1468. struct qeth_cmd_buffer *iob)
  1469. {
  1470. qeth_setup_ccw(&card->write, iob->data, len);
  1471. iob->callback = qeth_release_buffer;
  1472. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1473. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1474. card->seqno.trans_hdr++;
  1475. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1476. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1477. card->seqno.pdu_hdr++;
  1478. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1479. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1480. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1481. }
  1482. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1483. int qeth_send_control_data(struct qeth_card *card, int len,
  1484. struct qeth_cmd_buffer *iob,
  1485. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1486. unsigned long),
  1487. void *reply_param)
  1488. {
  1489. int rc;
  1490. unsigned long flags;
  1491. struct qeth_reply *reply = NULL;
  1492. unsigned long timeout, event_timeout;
  1493. struct qeth_ipa_cmd *cmd;
  1494. QETH_CARD_TEXT(card, 2, "sendctl");
  1495. reply = qeth_alloc_reply(card);
  1496. if (!reply) {
  1497. return -ENOMEM;
  1498. }
  1499. reply->callback = reply_cb;
  1500. reply->param = reply_param;
  1501. if (card->state == CARD_STATE_DOWN)
  1502. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1503. else
  1504. reply->seqno = card->seqno.ipa++;
  1505. init_waitqueue_head(&reply->wait_q);
  1506. spin_lock_irqsave(&card->lock, flags);
  1507. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1508. spin_unlock_irqrestore(&card->lock, flags);
  1509. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1510. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1511. qeth_prepare_control_data(card, len, iob);
  1512. if (IS_IPA(iob->data))
  1513. event_timeout = QETH_IPA_TIMEOUT;
  1514. else
  1515. event_timeout = QETH_TIMEOUT;
  1516. timeout = jiffies + event_timeout;
  1517. QETH_CARD_TEXT(card, 6, "noirqpnd");
  1518. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1519. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1520. (addr_t) iob, 0, 0);
  1521. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1522. if (rc) {
  1523. QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: "
  1524. "ccw_device_start rc = %i\n",
  1525. dev_name(&card->write.ccwdev->dev), rc);
  1526. QETH_CARD_TEXT_(card, 2, " err%d", rc);
  1527. spin_lock_irqsave(&card->lock, flags);
  1528. list_del_init(&reply->list);
  1529. qeth_put_reply(reply);
  1530. spin_unlock_irqrestore(&card->lock, flags);
  1531. qeth_release_buffer(iob->channel, iob);
  1532. atomic_set(&card->write.irq_pending, 0);
  1533. wake_up(&card->wait_q);
  1534. return rc;
  1535. }
  1536. /* we have only one long running ipassist, since we can ensure
  1537. process context of this command we can sleep */
  1538. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  1539. if ((cmd->hdr.command == IPA_CMD_SETIP) &&
  1540. (cmd->hdr.prot_version == QETH_PROT_IPV4)) {
  1541. if (!wait_event_timeout(reply->wait_q,
  1542. atomic_read(&reply->received), event_timeout))
  1543. goto time_err;
  1544. } else {
  1545. while (!atomic_read(&reply->received)) {
  1546. if (time_after(jiffies, timeout))
  1547. goto time_err;
  1548. cpu_relax();
  1549. };
  1550. }
  1551. rc = reply->rc;
  1552. qeth_put_reply(reply);
  1553. return rc;
  1554. time_err:
  1555. spin_lock_irqsave(&reply->card->lock, flags);
  1556. list_del_init(&reply->list);
  1557. spin_unlock_irqrestore(&reply->card->lock, flags);
  1558. reply->rc = -ETIME;
  1559. atomic_inc(&reply->received);
  1560. wake_up(&reply->wait_q);
  1561. rc = reply->rc;
  1562. qeth_put_reply(reply);
  1563. return rc;
  1564. }
  1565. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1566. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1567. unsigned long data)
  1568. {
  1569. struct qeth_cmd_buffer *iob;
  1570. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1571. iob = (struct qeth_cmd_buffer *) data;
  1572. memcpy(&card->token.cm_filter_r,
  1573. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1574. QETH_MPC_TOKEN_LENGTH);
  1575. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1576. return 0;
  1577. }
  1578. static int qeth_cm_enable(struct qeth_card *card)
  1579. {
  1580. int rc;
  1581. struct qeth_cmd_buffer *iob;
  1582. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1583. iob = qeth_wait_for_buffer(&card->write);
  1584. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1585. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1586. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1587. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1588. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1589. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1590. qeth_cm_enable_cb, NULL);
  1591. return rc;
  1592. }
  1593. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1594. unsigned long data)
  1595. {
  1596. struct qeth_cmd_buffer *iob;
  1597. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1598. iob = (struct qeth_cmd_buffer *) data;
  1599. memcpy(&card->token.cm_connection_r,
  1600. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1601. QETH_MPC_TOKEN_LENGTH);
  1602. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1603. return 0;
  1604. }
  1605. static int qeth_cm_setup(struct qeth_card *card)
  1606. {
  1607. int rc;
  1608. struct qeth_cmd_buffer *iob;
  1609. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1610. iob = qeth_wait_for_buffer(&card->write);
  1611. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1612. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1613. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1614. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1615. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1616. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1617. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1618. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1619. qeth_cm_setup_cb, NULL);
  1620. return rc;
  1621. }
  1622. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1623. {
  1624. switch (card->info.type) {
  1625. case QETH_CARD_TYPE_UNKNOWN:
  1626. return 1500;
  1627. case QETH_CARD_TYPE_IQD:
  1628. return card->info.max_mtu;
  1629. case QETH_CARD_TYPE_OSD:
  1630. switch (card->info.link_type) {
  1631. case QETH_LINK_TYPE_HSTR:
  1632. case QETH_LINK_TYPE_LANE_TR:
  1633. return 2000;
  1634. default:
  1635. return 1492;
  1636. }
  1637. case QETH_CARD_TYPE_OSM:
  1638. case QETH_CARD_TYPE_OSX:
  1639. return 1492;
  1640. default:
  1641. return 1500;
  1642. }
  1643. }
  1644. static inline int qeth_get_max_mtu_for_card(int cardtype)
  1645. {
  1646. switch (cardtype) {
  1647. case QETH_CARD_TYPE_UNKNOWN:
  1648. case QETH_CARD_TYPE_OSD:
  1649. case QETH_CARD_TYPE_OSN:
  1650. case QETH_CARD_TYPE_OSM:
  1651. case QETH_CARD_TYPE_OSX:
  1652. return 61440;
  1653. case QETH_CARD_TYPE_IQD:
  1654. return 57344;
  1655. default:
  1656. return 1500;
  1657. }
  1658. }
  1659. static inline int qeth_get_mtu_out_of_mpc(int cardtype)
  1660. {
  1661. switch (cardtype) {
  1662. case QETH_CARD_TYPE_IQD:
  1663. return 1;
  1664. default:
  1665. return 0;
  1666. }
  1667. }
  1668. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1669. {
  1670. switch (framesize) {
  1671. case 0x4000:
  1672. return 8192;
  1673. case 0x6000:
  1674. return 16384;
  1675. case 0xa000:
  1676. return 32768;
  1677. case 0xffff:
  1678. return 57344;
  1679. default:
  1680. return 0;
  1681. }
  1682. }
  1683. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1684. {
  1685. switch (card->info.type) {
  1686. case QETH_CARD_TYPE_OSD:
  1687. case QETH_CARD_TYPE_OSM:
  1688. case QETH_CARD_TYPE_OSX:
  1689. return ((mtu >= 576) && (mtu <= 61440));
  1690. case QETH_CARD_TYPE_IQD:
  1691. return ((mtu >= 576) &&
  1692. (mtu <= card->info.max_mtu + 4096 - 32));
  1693. case QETH_CARD_TYPE_OSN:
  1694. case QETH_CARD_TYPE_UNKNOWN:
  1695. default:
  1696. return 1;
  1697. }
  1698. }
  1699. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1700. unsigned long data)
  1701. {
  1702. __u16 mtu, framesize;
  1703. __u16 len;
  1704. __u8 link_type;
  1705. struct qeth_cmd_buffer *iob;
  1706. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  1707. iob = (struct qeth_cmd_buffer *) data;
  1708. memcpy(&card->token.ulp_filter_r,
  1709. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1710. QETH_MPC_TOKEN_LENGTH);
  1711. if (qeth_get_mtu_out_of_mpc(card->info.type)) {
  1712. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  1713. mtu = qeth_get_mtu_outof_framesize(framesize);
  1714. if (!mtu) {
  1715. iob->rc = -EINVAL;
  1716. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1717. return 0;
  1718. }
  1719. card->info.max_mtu = mtu;
  1720. card->info.initial_mtu = mtu;
  1721. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  1722. } else {
  1723. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  1724. card->info.max_mtu = qeth_get_max_mtu_for_card(card->info.type);
  1725. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1726. }
  1727. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  1728. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  1729. memcpy(&link_type,
  1730. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  1731. card->info.link_type = link_type;
  1732. } else
  1733. card->info.link_type = 0;
  1734. QETH_DBF_TEXT_(SETUP, 2, "link%d", link_type);
  1735. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1736. return 0;
  1737. }
  1738. static int qeth_ulp_enable(struct qeth_card *card)
  1739. {
  1740. int rc;
  1741. char prot_type;
  1742. struct qeth_cmd_buffer *iob;
  1743. /*FIXME: trace view callbacks*/
  1744. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  1745. iob = qeth_wait_for_buffer(&card->write);
  1746. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  1747. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  1748. (__u8) card->info.portno;
  1749. if (card->options.layer2)
  1750. if (card->info.type == QETH_CARD_TYPE_OSN)
  1751. prot_type = QETH_PROT_OSN2;
  1752. else
  1753. prot_type = QETH_PROT_LAYER2;
  1754. else
  1755. prot_type = QETH_PROT_TCPIP;
  1756. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  1757. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  1758. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1759. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  1760. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  1761. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  1762. card->info.portname, 9);
  1763. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  1764. qeth_ulp_enable_cb, NULL);
  1765. return rc;
  1766. }
  1767. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1768. unsigned long data)
  1769. {
  1770. struct qeth_cmd_buffer *iob;
  1771. int rc = 0;
  1772. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  1773. iob = (struct qeth_cmd_buffer *) data;
  1774. memcpy(&card->token.ulp_connection_r,
  1775. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1776. QETH_MPC_TOKEN_LENGTH);
  1777. if (!strncmp("00S", QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1778. 3)) {
  1779. QETH_DBF_TEXT(SETUP, 2, "olmlimit");
  1780. dev_err(&card->gdev->dev, "A connection could not be "
  1781. "established because of an OLM limit\n");
  1782. rc = -EMLINK;
  1783. }
  1784. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1785. return rc;
  1786. }
  1787. static int qeth_ulp_setup(struct qeth_card *card)
  1788. {
  1789. int rc;
  1790. __u16 temp;
  1791. struct qeth_cmd_buffer *iob;
  1792. struct ccw_dev_id dev_id;
  1793. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  1794. iob = qeth_wait_for_buffer(&card->write);
  1795. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  1796. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  1797. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1798. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  1799. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  1800. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  1801. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  1802. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  1803. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  1804. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1805. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  1806. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  1807. qeth_ulp_setup_cb, NULL);
  1808. return rc;
  1809. }
  1810. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  1811. {
  1812. int i, j;
  1813. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  1814. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  1815. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  1816. return 0;
  1817. card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
  1818. GFP_KERNEL);
  1819. if (!card->qdio.in_q)
  1820. goto out_nomem;
  1821. QETH_DBF_TEXT(SETUP, 2, "inq");
  1822. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  1823. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  1824. /* give inbound qeth_qdio_buffers their qdio_buffers */
  1825. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  1826. card->qdio.in_q->bufs[i].buffer =
  1827. &card->qdio.in_q->qdio_bufs[i];
  1828. /* inbound buffer pool */
  1829. if (qeth_alloc_buffer_pool(card))
  1830. goto out_freeinq;
  1831. /* outbound */
  1832. card->qdio.out_qs =
  1833. kmalloc(card->qdio.no_out_queues *
  1834. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  1835. if (!card->qdio.out_qs)
  1836. goto out_freepool;
  1837. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1838. card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
  1839. GFP_KERNEL);
  1840. if (!card->qdio.out_qs[i])
  1841. goto out_freeoutq;
  1842. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  1843. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  1844. memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
  1845. card->qdio.out_qs[i]->queue_no = i;
  1846. /* give outbound qeth_qdio_buffers their qdio_buffers */
  1847. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1848. card->qdio.out_qs[i]->bufs[j].buffer =
  1849. &card->qdio.out_qs[i]->qdio_bufs[j];
  1850. skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
  1851. skb_list);
  1852. lockdep_set_class(
  1853. &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
  1854. &qdio_out_skb_queue_key);
  1855. INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
  1856. }
  1857. }
  1858. return 0;
  1859. out_freeoutq:
  1860. while (i > 0)
  1861. kfree(card->qdio.out_qs[--i]);
  1862. kfree(card->qdio.out_qs);
  1863. card->qdio.out_qs = NULL;
  1864. out_freepool:
  1865. qeth_free_buffer_pool(card);
  1866. out_freeinq:
  1867. kfree(card->qdio.in_q);
  1868. card->qdio.in_q = NULL;
  1869. out_nomem:
  1870. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1871. return -ENOMEM;
  1872. }
  1873. static void qeth_create_qib_param_field(struct qeth_card *card,
  1874. char *param_field)
  1875. {
  1876. param_field[0] = _ascebc['P'];
  1877. param_field[1] = _ascebc['C'];
  1878. param_field[2] = _ascebc['I'];
  1879. param_field[3] = _ascebc['T'];
  1880. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  1881. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  1882. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  1883. }
  1884. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  1885. char *param_field)
  1886. {
  1887. param_field[16] = _ascebc['B'];
  1888. param_field[17] = _ascebc['L'];
  1889. param_field[18] = _ascebc['K'];
  1890. param_field[19] = _ascebc['T'];
  1891. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  1892. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  1893. *((unsigned int *) (&param_field[28])) =
  1894. card->info.blkt.inter_packet_jumbo;
  1895. }
  1896. static int qeth_qdio_activate(struct qeth_card *card)
  1897. {
  1898. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  1899. return qdio_activate(CARD_DDEV(card));
  1900. }
  1901. static int qeth_dm_act(struct qeth_card *card)
  1902. {
  1903. int rc;
  1904. struct qeth_cmd_buffer *iob;
  1905. QETH_DBF_TEXT(SETUP, 2, "dmact");
  1906. iob = qeth_wait_for_buffer(&card->write);
  1907. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  1908. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  1909. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1910. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  1911. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  1912. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  1913. return rc;
  1914. }
  1915. static int qeth_mpc_initialize(struct qeth_card *card)
  1916. {
  1917. int rc;
  1918. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  1919. rc = qeth_issue_next_read(card);
  1920. if (rc) {
  1921. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1922. return rc;
  1923. }
  1924. rc = qeth_cm_enable(card);
  1925. if (rc) {
  1926. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1927. goto out_qdio;
  1928. }
  1929. rc = qeth_cm_setup(card);
  1930. if (rc) {
  1931. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1932. goto out_qdio;
  1933. }
  1934. rc = qeth_ulp_enable(card);
  1935. if (rc) {
  1936. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  1937. goto out_qdio;
  1938. }
  1939. rc = qeth_ulp_setup(card);
  1940. if (rc) {
  1941. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1942. goto out_qdio;
  1943. }
  1944. rc = qeth_alloc_qdio_buffers(card);
  1945. if (rc) {
  1946. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1947. goto out_qdio;
  1948. }
  1949. rc = qeth_qdio_establish(card);
  1950. if (rc) {
  1951. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  1952. qeth_free_qdio_buffers(card);
  1953. goto out_qdio;
  1954. }
  1955. rc = qeth_qdio_activate(card);
  1956. if (rc) {
  1957. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  1958. goto out_qdio;
  1959. }
  1960. rc = qeth_dm_act(card);
  1961. if (rc) {
  1962. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  1963. goto out_qdio;
  1964. }
  1965. return 0;
  1966. out_qdio:
  1967. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  1968. return rc;
  1969. }
  1970. static void qeth_print_status_with_portname(struct qeth_card *card)
  1971. {
  1972. char dbf_text[15];
  1973. int i;
  1974. sprintf(dbf_text, "%s", card->info.portname + 1);
  1975. for (i = 0; i < 8; i++)
  1976. dbf_text[i] =
  1977. (char) _ebcasc[(__u8) dbf_text[i]];
  1978. dbf_text[8] = 0;
  1979. dev_info(&card->gdev->dev, "Device is a%s card%s%s%s\n"
  1980. "with link type %s (portname: %s)\n",
  1981. qeth_get_cardname(card),
  1982. (card->info.mcl_level[0]) ? " (level: " : "",
  1983. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1984. (card->info.mcl_level[0]) ? ")" : "",
  1985. qeth_get_cardname_short(card),
  1986. dbf_text);
  1987. }
  1988. static void qeth_print_status_no_portname(struct qeth_card *card)
  1989. {
  1990. if (card->info.portname[0])
  1991. dev_info(&card->gdev->dev, "Device is a%s "
  1992. "card%s%s%s\nwith link type %s "
  1993. "(no portname needed by interface).\n",
  1994. qeth_get_cardname(card),
  1995. (card->info.mcl_level[0]) ? " (level: " : "",
  1996. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1997. (card->info.mcl_level[0]) ? ")" : "",
  1998. qeth_get_cardname_short(card));
  1999. else
  2000. dev_info(&card->gdev->dev, "Device is a%s "
  2001. "card%s%s%s\nwith link type %s.\n",
  2002. qeth_get_cardname(card),
  2003. (card->info.mcl_level[0]) ? " (level: " : "",
  2004. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2005. (card->info.mcl_level[0]) ? ")" : "",
  2006. qeth_get_cardname_short(card));
  2007. }
  2008. void qeth_print_status_message(struct qeth_card *card)
  2009. {
  2010. switch (card->info.type) {
  2011. case QETH_CARD_TYPE_OSD:
  2012. case QETH_CARD_TYPE_OSM:
  2013. case QETH_CARD_TYPE_OSX:
  2014. /* VM will use a non-zero first character
  2015. * to indicate a HiperSockets like reporting
  2016. * of the level OSA sets the first character to zero
  2017. * */
  2018. if (!card->info.mcl_level[0]) {
  2019. sprintf(card->info.mcl_level, "%02x%02x",
  2020. card->info.mcl_level[2],
  2021. card->info.mcl_level[3]);
  2022. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2023. break;
  2024. }
  2025. /* fallthrough */
  2026. case QETH_CARD_TYPE_IQD:
  2027. if ((card->info.guestlan) ||
  2028. (card->info.mcl_level[0] & 0x80)) {
  2029. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2030. card->info.mcl_level[0]];
  2031. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2032. card->info.mcl_level[1]];
  2033. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2034. card->info.mcl_level[2]];
  2035. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2036. card->info.mcl_level[3]];
  2037. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2038. }
  2039. break;
  2040. default:
  2041. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2042. }
  2043. if (card->info.portname_required)
  2044. qeth_print_status_with_portname(card);
  2045. else
  2046. qeth_print_status_no_portname(card);
  2047. }
  2048. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2049. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2050. {
  2051. struct qeth_buffer_pool_entry *entry;
  2052. QETH_CARD_TEXT(card, 5, "inwrklst");
  2053. list_for_each_entry(entry,
  2054. &card->qdio.init_pool.entry_list, init_list) {
  2055. qeth_put_buffer_pool_entry(card, entry);
  2056. }
  2057. }
  2058. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2059. struct qeth_card *card)
  2060. {
  2061. struct list_head *plh;
  2062. struct qeth_buffer_pool_entry *entry;
  2063. int i, free;
  2064. struct page *page;
  2065. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2066. return NULL;
  2067. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2068. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2069. free = 1;
  2070. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2071. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2072. free = 0;
  2073. break;
  2074. }
  2075. }
  2076. if (free) {
  2077. list_del_init(&entry->list);
  2078. return entry;
  2079. }
  2080. }
  2081. /* no free buffer in pool so take first one and swap pages */
  2082. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2083. struct qeth_buffer_pool_entry, list);
  2084. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2085. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2086. page = alloc_page(GFP_ATOMIC);
  2087. if (!page) {
  2088. return NULL;
  2089. } else {
  2090. free_page((unsigned long)entry->elements[i]);
  2091. entry->elements[i] = page_address(page);
  2092. if (card->options.performance_stats)
  2093. card->perf_stats.sg_alloc_page_rx++;
  2094. }
  2095. }
  2096. }
  2097. list_del_init(&entry->list);
  2098. return entry;
  2099. }
  2100. static int qeth_init_input_buffer(struct qeth_card *card,
  2101. struct qeth_qdio_buffer *buf)
  2102. {
  2103. struct qeth_buffer_pool_entry *pool_entry;
  2104. int i;
  2105. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2106. if (!pool_entry)
  2107. return 1;
  2108. /*
  2109. * since the buffer is accessed only from the input_tasklet
  2110. * there shouldn't be a need to synchronize; also, since we use
  2111. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2112. * buffers
  2113. */
  2114. buf->pool_entry = pool_entry;
  2115. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2116. buf->buffer->element[i].length = PAGE_SIZE;
  2117. buf->buffer->element[i].addr = pool_entry->elements[i];
  2118. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2119. buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY;
  2120. else
  2121. buf->buffer->element[i].flags = 0;
  2122. }
  2123. return 0;
  2124. }
  2125. int qeth_init_qdio_queues(struct qeth_card *card)
  2126. {
  2127. int i, j;
  2128. int rc;
  2129. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2130. /* inbound queue */
  2131. memset(card->qdio.in_q->qdio_bufs, 0,
  2132. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2133. qeth_initialize_working_pool_list(card);
  2134. /*give only as many buffers to hardware as we have buffer pool entries*/
  2135. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2136. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2137. card->qdio.in_q->next_buf_to_init =
  2138. card->qdio.in_buf_pool.buf_count - 1;
  2139. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2140. card->qdio.in_buf_pool.buf_count - 1);
  2141. if (rc) {
  2142. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2143. return rc;
  2144. }
  2145. /* outbound queue */
  2146. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2147. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2148. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2149. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2150. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2151. &card->qdio.out_qs[i]->bufs[j]);
  2152. }
  2153. card->qdio.out_qs[i]->card = card;
  2154. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2155. card->qdio.out_qs[i]->do_pack = 0;
  2156. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2157. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2158. atomic_set(&card->qdio.out_qs[i]->state,
  2159. QETH_OUT_Q_UNLOCKED);
  2160. }
  2161. return 0;
  2162. }
  2163. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2164. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2165. {
  2166. switch (link_type) {
  2167. case QETH_LINK_TYPE_HSTR:
  2168. return 2;
  2169. default:
  2170. return 1;
  2171. }
  2172. }
  2173. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2174. struct qeth_ipa_cmd *cmd, __u8 command,
  2175. enum qeth_prot_versions prot)
  2176. {
  2177. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2178. cmd->hdr.command = command;
  2179. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2180. cmd->hdr.seqno = card->seqno.ipa;
  2181. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2182. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2183. if (card->options.layer2)
  2184. cmd->hdr.prim_version_no = 2;
  2185. else
  2186. cmd->hdr.prim_version_no = 1;
  2187. cmd->hdr.param_count = 1;
  2188. cmd->hdr.prot_version = prot;
  2189. cmd->hdr.ipa_supported = 0;
  2190. cmd->hdr.ipa_enabled = 0;
  2191. }
  2192. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2193. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2194. {
  2195. struct qeth_cmd_buffer *iob;
  2196. struct qeth_ipa_cmd *cmd;
  2197. iob = qeth_wait_for_buffer(&card->write);
  2198. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2199. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2200. return iob;
  2201. }
  2202. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2203. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2204. char prot_type)
  2205. {
  2206. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2207. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2208. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2209. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2210. }
  2211. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2212. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2213. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2214. unsigned long),
  2215. void *reply_param)
  2216. {
  2217. int rc;
  2218. char prot_type;
  2219. QETH_CARD_TEXT(card, 4, "sendipa");
  2220. if (card->options.layer2)
  2221. if (card->info.type == QETH_CARD_TYPE_OSN)
  2222. prot_type = QETH_PROT_OSN2;
  2223. else
  2224. prot_type = QETH_PROT_LAYER2;
  2225. else
  2226. prot_type = QETH_PROT_TCPIP;
  2227. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2228. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2229. iob, reply_cb, reply_param);
  2230. return rc;
  2231. }
  2232. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2233. static int qeth_send_startstoplan(struct qeth_card *card,
  2234. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2235. {
  2236. int rc;
  2237. struct qeth_cmd_buffer *iob;
  2238. iob = qeth_get_ipacmd_buffer(card, ipacmd, prot);
  2239. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2240. return rc;
  2241. }
  2242. int qeth_send_startlan(struct qeth_card *card)
  2243. {
  2244. int rc;
  2245. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2246. rc = qeth_send_startstoplan(card, IPA_CMD_STARTLAN, 0);
  2247. return rc;
  2248. }
  2249. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2250. int qeth_send_stoplan(struct qeth_card *card)
  2251. {
  2252. int rc = 0;
  2253. /*
  2254. * TODO: according to the IPA format document page 14,
  2255. * TCP/IP (we!) never issue a STOPLAN
  2256. * is this right ?!?
  2257. */
  2258. QETH_DBF_TEXT(SETUP, 2, "stoplan");
  2259. rc = qeth_send_startstoplan(card, IPA_CMD_STOPLAN, 0);
  2260. return rc;
  2261. }
  2262. EXPORT_SYMBOL_GPL(qeth_send_stoplan);
  2263. int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2264. struct qeth_reply *reply, unsigned long data)
  2265. {
  2266. struct qeth_ipa_cmd *cmd;
  2267. QETH_CARD_TEXT(card, 4, "defadpcb");
  2268. cmd = (struct qeth_ipa_cmd *) data;
  2269. if (cmd->hdr.return_code == 0)
  2270. cmd->hdr.return_code =
  2271. cmd->data.setadapterparms.hdr.return_code;
  2272. return 0;
  2273. }
  2274. EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
  2275. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2276. struct qeth_reply *reply, unsigned long data)
  2277. {
  2278. struct qeth_ipa_cmd *cmd;
  2279. QETH_CARD_TEXT(card, 3, "quyadpcb");
  2280. cmd = (struct qeth_ipa_cmd *) data;
  2281. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f) {
  2282. card->info.link_type =
  2283. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2284. QETH_DBF_TEXT_(SETUP, 2, "lnk %d", card->info.link_type);
  2285. }
  2286. card->options.adp.supported_funcs =
  2287. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2288. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2289. }
  2290. struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2291. __u32 command, __u32 cmdlen)
  2292. {
  2293. struct qeth_cmd_buffer *iob;
  2294. struct qeth_ipa_cmd *cmd;
  2295. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2296. QETH_PROT_IPV4);
  2297. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2298. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2299. cmd->data.setadapterparms.hdr.command_code = command;
  2300. cmd->data.setadapterparms.hdr.used_total = 1;
  2301. cmd->data.setadapterparms.hdr.seq_no = 1;
  2302. return iob;
  2303. }
  2304. EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
  2305. int qeth_query_setadapterparms(struct qeth_card *card)
  2306. {
  2307. int rc;
  2308. struct qeth_cmd_buffer *iob;
  2309. QETH_CARD_TEXT(card, 3, "queryadp");
  2310. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2311. sizeof(struct qeth_ipacmd_setadpparms));
  2312. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2313. return rc;
  2314. }
  2315. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2316. int qeth_check_qdio_errors(struct qeth_card *card, struct qdio_buffer *buf,
  2317. unsigned int qdio_error, const char *dbftext)
  2318. {
  2319. if (qdio_error) {
  2320. QETH_CARD_TEXT(card, 2, dbftext);
  2321. QETH_CARD_TEXT_(card, 2, " F15=%02X",
  2322. buf->element[15].flags & 0xff);
  2323. QETH_CARD_TEXT_(card, 2, " F14=%02X",
  2324. buf->element[14].flags & 0xff);
  2325. QETH_CARD_TEXT_(card, 2, " qerr=%X", qdio_error);
  2326. if ((buf->element[15].flags & 0xff) == 0x12) {
  2327. card->stats.rx_dropped++;
  2328. return 0;
  2329. } else
  2330. return 1;
  2331. }
  2332. return 0;
  2333. }
  2334. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2335. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2336. {
  2337. struct qeth_qdio_q *queue = card->qdio.in_q;
  2338. int count;
  2339. int i;
  2340. int rc;
  2341. int newcount = 0;
  2342. count = (index < queue->next_buf_to_init)?
  2343. card->qdio.in_buf_pool.buf_count -
  2344. (queue->next_buf_to_init - index) :
  2345. card->qdio.in_buf_pool.buf_count -
  2346. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2347. /* only requeue at a certain threshold to avoid SIGAs */
  2348. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2349. for (i = queue->next_buf_to_init;
  2350. i < queue->next_buf_to_init + count; ++i) {
  2351. if (qeth_init_input_buffer(card,
  2352. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2353. break;
  2354. } else {
  2355. newcount++;
  2356. }
  2357. }
  2358. if (newcount < count) {
  2359. /* we are in memory shortage so we switch back to
  2360. traditional skb allocation and drop packages */
  2361. atomic_set(&card->force_alloc_skb, 3);
  2362. count = newcount;
  2363. } else {
  2364. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2365. }
  2366. /*
  2367. * according to old code it should be avoided to requeue all
  2368. * 128 buffers in order to benefit from PCI avoidance.
  2369. * this function keeps at least one buffer (the buffer at
  2370. * 'index') un-requeued -> this buffer is the first buffer that
  2371. * will be requeued the next time
  2372. */
  2373. if (card->options.performance_stats) {
  2374. card->perf_stats.inbound_do_qdio_cnt++;
  2375. card->perf_stats.inbound_do_qdio_start_time =
  2376. qeth_get_micros();
  2377. }
  2378. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
  2379. queue->next_buf_to_init, count);
  2380. if (card->options.performance_stats)
  2381. card->perf_stats.inbound_do_qdio_time +=
  2382. qeth_get_micros() -
  2383. card->perf_stats.inbound_do_qdio_start_time;
  2384. if (rc) {
  2385. dev_warn(&card->gdev->dev,
  2386. "QDIO reported an error, rc=%i\n", rc);
  2387. QETH_CARD_TEXT(card, 2, "qinberr");
  2388. }
  2389. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2390. QDIO_MAX_BUFFERS_PER_Q;
  2391. }
  2392. }
  2393. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2394. static int qeth_handle_send_error(struct qeth_card *card,
  2395. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
  2396. {
  2397. int sbalf15 = buffer->buffer->element[15].flags & 0xff;
  2398. QETH_CARD_TEXT(card, 6, "hdsnderr");
  2399. if (card->info.type == QETH_CARD_TYPE_IQD) {
  2400. if (sbalf15 == 0) {
  2401. qdio_err = 0;
  2402. } else {
  2403. qdio_err = 1;
  2404. }
  2405. }
  2406. qeth_check_qdio_errors(card, buffer->buffer, qdio_err, "qouterr");
  2407. if (!qdio_err)
  2408. return QETH_SEND_ERROR_NONE;
  2409. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2410. return QETH_SEND_ERROR_RETRY;
  2411. QETH_CARD_TEXT(card, 1, "lnkfail");
  2412. QETH_CARD_TEXT_(card, 1, "%04x %02x",
  2413. (u16)qdio_err, (u8)sbalf15);
  2414. return QETH_SEND_ERROR_LINK_FAILURE;
  2415. }
  2416. /*
  2417. * Switched to packing state if the number of used buffers on a queue
  2418. * reaches a certain limit.
  2419. */
  2420. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2421. {
  2422. if (!queue->do_pack) {
  2423. if (atomic_read(&queue->used_buffers)
  2424. >= QETH_HIGH_WATERMARK_PACK){
  2425. /* switch non-PACKING -> PACKING */
  2426. QETH_CARD_TEXT(queue->card, 6, "np->pack");
  2427. if (queue->card->options.performance_stats)
  2428. queue->card->perf_stats.sc_dp_p++;
  2429. queue->do_pack = 1;
  2430. }
  2431. }
  2432. }
  2433. /*
  2434. * Switches from packing to non-packing mode. If there is a packing
  2435. * buffer on the queue this buffer will be prepared to be flushed.
  2436. * In that case 1 is returned to inform the caller. If no buffer
  2437. * has to be flushed, zero is returned.
  2438. */
  2439. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2440. {
  2441. struct qeth_qdio_out_buffer *buffer;
  2442. int flush_count = 0;
  2443. if (queue->do_pack) {
  2444. if (atomic_read(&queue->used_buffers)
  2445. <= QETH_LOW_WATERMARK_PACK) {
  2446. /* switch PACKING -> non-PACKING */
  2447. QETH_CARD_TEXT(queue->card, 6, "pack->np");
  2448. if (queue->card->options.performance_stats)
  2449. queue->card->perf_stats.sc_p_dp++;
  2450. queue->do_pack = 0;
  2451. /* flush packing buffers */
  2452. buffer = &queue->bufs[queue->next_buf_to_fill];
  2453. if ((atomic_read(&buffer->state) ==
  2454. QETH_QDIO_BUF_EMPTY) &&
  2455. (buffer->next_element_to_fill > 0)) {
  2456. atomic_set(&buffer->state,
  2457. QETH_QDIO_BUF_PRIMED);
  2458. flush_count++;
  2459. queue->next_buf_to_fill =
  2460. (queue->next_buf_to_fill + 1) %
  2461. QDIO_MAX_BUFFERS_PER_Q;
  2462. }
  2463. }
  2464. }
  2465. return flush_count;
  2466. }
  2467. /*
  2468. * Called to flush a packing buffer if no more pci flags are on the queue.
  2469. * Checks if there is a packing buffer and prepares it to be flushed.
  2470. * In that case returns 1, otherwise zero.
  2471. */
  2472. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2473. {
  2474. struct qeth_qdio_out_buffer *buffer;
  2475. buffer = &queue->bufs[queue->next_buf_to_fill];
  2476. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2477. (buffer->next_element_to_fill > 0)) {
  2478. /* it's a packing buffer */
  2479. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2480. queue->next_buf_to_fill =
  2481. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2482. return 1;
  2483. }
  2484. return 0;
  2485. }
  2486. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
  2487. int count)
  2488. {
  2489. struct qeth_qdio_out_buffer *buf;
  2490. int rc;
  2491. int i;
  2492. unsigned int qdio_flags;
  2493. for (i = index; i < index + count; ++i) {
  2494. buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2495. buf->buffer->element[buf->next_element_to_fill - 1].flags |=
  2496. SBAL_FLAGS_LAST_ENTRY;
  2497. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2498. continue;
  2499. if (!queue->do_pack) {
  2500. if ((atomic_read(&queue->used_buffers) >=
  2501. (QETH_HIGH_WATERMARK_PACK -
  2502. QETH_WATERMARK_PACK_FUZZ)) &&
  2503. !atomic_read(&queue->set_pci_flags_count)) {
  2504. /* it's likely that we'll go to packing
  2505. * mode soon */
  2506. atomic_inc(&queue->set_pci_flags_count);
  2507. buf->buffer->element[0].flags |= 0x40;
  2508. }
  2509. } else {
  2510. if (!atomic_read(&queue->set_pci_flags_count)) {
  2511. /*
  2512. * there's no outstanding PCI any more, so we
  2513. * have to request a PCI to be sure the the PCI
  2514. * will wake at some time in the future then we
  2515. * can flush packed buffers that might still be
  2516. * hanging around, which can happen if no
  2517. * further send was requested by the stack
  2518. */
  2519. atomic_inc(&queue->set_pci_flags_count);
  2520. buf->buffer->element[0].flags |= 0x40;
  2521. }
  2522. }
  2523. }
  2524. queue->sync_iqdio_error = 0;
  2525. queue->card->dev->trans_start = jiffies;
  2526. if (queue->card->options.performance_stats) {
  2527. queue->card->perf_stats.outbound_do_qdio_cnt++;
  2528. queue->card->perf_stats.outbound_do_qdio_start_time =
  2529. qeth_get_micros();
  2530. }
  2531. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  2532. if (atomic_read(&queue->set_pci_flags_count))
  2533. qdio_flags |= QDIO_FLAG_PCI_OUT;
  2534. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  2535. queue->queue_no, index, count);
  2536. if (queue->card->options.performance_stats)
  2537. queue->card->perf_stats.outbound_do_qdio_time +=
  2538. qeth_get_micros() -
  2539. queue->card->perf_stats.outbound_do_qdio_start_time;
  2540. if (rc > 0) {
  2541. if (!(rc & QDIO_ERROR_SIGA_BUSY))
  2542. queue->sync_iqdio_error = rc & 3;
  2543. }
  2544. if (rc) {
  2545. queue->card->stats.tx_errors += count;
  2546. /* ignore temporary SIGA errors without busy condition */
  2547. if (rc == QDIO_ERROR_SIGA_TARGET)
  2548. return;
  2549. QETH_CARD_TEXT(queue->card, 2, "flushbuf");
  2550. QETH_CARD_TEXT_(queue->card, 2, " err%d", rc);
  2551. /* this must not happen under normal circumstances. if it
  2552. * happens something is really wrong -> recover */
  2553. qeth_schedule_recovery(queue->card);
  2554. return;
  2555. }
  2556. atomic_add(count, &queue->used_buffers);
  2557. if (queue->card->options.performance_stats)
  2558. queue->card->perf_stats.bufs_sent += count;
  2559. }
  2560. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  2561. {
  2562. int index;
  2563. int flush_cnt = 0;
  2564. int q_was_packing = 0;
  2565. /*
  2566. * check if weed have to switch to non-packing mode or if
  2567. * we have to get a pci flag out on the queue
  2568. */
  2569. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  2570. !atomic_read(&queue->set_pci_flags_count)) {
  2571. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  2572. QETH_OUT_Q_UNLOCKED) {
  2573. /*
  2574. * If we get in here, there was no action in
  2575. * do_send_packet. So, we check if there is a
  2576. * packing buffer to be flushed here.
  2577. */
  2578. netif_stop_queue(queue->card->dev);
  2579. index = queue->next_buf_to_fill;
  2580. q_was_packing = queue->do_pack;
  2581. /* queue->do_pack may change */
  2582. barrier();
  2583. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  2584. if (!flush_cnt &&
  2585. !atomic_read(&queue->set_pci_flags_count))
  2586. flush_cnt +=
  2587. qeth_flush_buffers_on_no_pci(queue);
  2588. if (queue->card->options.performance_stats &&
  2589. q_was_packing)
  2590. queue->card->perf_stats.bufs_sent_pack +=
  2591. flush_cnt;
  2592. if (flush_cnt)
  2593. qeth_flush_buffers(queue, index, flush_cnt);
  2594. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2595. }
  2596. }
  2597. }
  2598. void qeth_qdio_output_handler(struct ccw_device *ccwdev,
  2599. unsigned int qdio_error, int __queue, int first_element,
  2600. int count, unsigned long card_ptr)
  2601. {
  2602. struct qeth_card *card = (struct qeth_card *) card_ptr;
  2603. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  2604. struct qeth_qdio_out_buffer *buffer;
  2605. int i;
  2606. unsigned qeth_send_err;
  2607. QETH_CARD_TEXT(card, 6, "qdouhdl");
  2608. if (qdio_error & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) {
  2609. QETH_CARD_TEXT(card, 2, "achkcond");
  2610. netif_stop_queue(card->dev);
  2611. qeth_schedule_recovery(card);
  2612. return;
  2613. }
  2614. if (card->options.performance_stats) {
  2615. card->perf_stats.outbound_handler_cnt++;
  2616. card->perf_stats.outbound_handler_start_time =
  2617. qeth_get_micros();
  2618. }
  2619. for (i = first_element; i < (first_element + count); ++i) {
  2620. buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2621. qeth_send_err = qeth_handle_send_error(card, buffer, qdio_error);
  2622. __qeth_clear_output_buffer(queue, buffer,
  2623. (qeth_send_err == QETH_SEND_ERROR_RETRY) ? 1 : 0);
  2624. }
  2625. atomic_sub(count, &queue->used_buffers);
  2626. /* check if we need to do something on this outbound queue */
  2627. if (card->info.type != QETH_CARD_TYPE_IQD)
  2628. qeth_check_outbound_queue(queue);
  2629. netif_wake_queue(queue->card->dev);
  2630. if (card->options.performance_stats)
  2631. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  2632. card->perf_stats.outbound_handler_start_time;
  2633. }
  2634. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  2635. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  2636. int ipv, int cast_type)
  2637. {
  2638. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSD ||
  2639. card->info.type == QETH_CARD_TYPE_OSX))
  2640. return card->qdio.default_out_queue;
  2641. switch (card->qdio.no_out_queues) {
  2642. case 4:
  2643. if (cast_type && card->info.is_multicast_different)
  2644. return card->info.is_multicast_different &
  2645. (card->qdio.no_out_queues - 1);
  2646. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  2647. const u8 tos = ip_hdr(skb)->tos;
  2648. if (card->qdio.do_prio_queueing ==
  2649. QETH_PRIO_Q_ING_TOS) {
  2650. if (tos & IP_TOS_NOTIMPORTANT)
  2651. return 3;
  2652. if (tos & IP_TOS_HIGHRELIABILITY)
  2653. return 2;
  2654. if (tos & IP_TOS_HIGHTHROUGHPUT)
  2655. return 1;
  2656. if (tos & IP_TOS_LOWDELAY)
  2657. return 0;
  2658. }
  2659. if (card->qdio.do_prio_queueing ==
  2660. QETH_PRIO_Q_ING_PREC)
  2661. return 3 - (tos >> 6);
  2662. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  2663. /* TODO: IPv6!!! */
  2664. }
  2665. return card->qdio.default_out_queue;
  2666. case 1: /* fallthrough for single-out-queue 1920-device */
  2667. default:
  2668. return card->qdio.default_out_queue;
  2669. }
  2670. }
  2671. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  2672. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  2673. struct sk_buff *skb, int elems)
  2674. {
  2675. int dlen = skb->len - skb->data_len;
  2676. int elements_needed = PFN_UP((unsigned long)skb->data + dlen - 1) -
  2677. PFN_DOWN((unsigned long)skb->data);
  2678. elements_needed += skb_shinfo(skb)->nr_frags;
  2679. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  2680. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  2681. "(Number=%d / Length=%d). Discarded.\n",
  2682. (elements_needed+elems), skb->len);
  2683. return 0;
  2684. }
  2685. return elements_needed;
  2686. }
  2687. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  2688. int qeth_hdr_chk_and_bounce(struct sk_buff *skb, int len)
  2689. {
  2690. int hroom, inpage, rest;
  2691. if (((unsigned long)skb->data & PAGE_MASK) !=
  2692. (((unsigned long)skb->data + len - 1) & PAGE_MASK)) {
  2693. hroom = skb_headroom(skb);
  2694. inpage = PAGE_SIZE - ((unsigned long) skb->data % PAGE_SIZE);
  2695. rest = len - inpage;
  2696. if (rest > hroom)
  2697. return 1;
  2698. memmove(skb->data - rest, skb->data, skb->len - skb->data_len);
  2699. skb->data -= rest;
  2700. QETH_DBF_MESSAGE(2, "skb bounce len: %d rest: %d\n", len, rest);
  2701. }
  2702. return 0;
  2703. }
  2704. EXPORT_SYMBOL_GPL(qeth_hdr_chk_and_bounce);
  2705. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  2706. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
  2707. int offset)
  2708. {
  2709. int length = skb->len - skb->data_len;
  2710. int length_here;
  2711. int element;
  2712. char *data;
  2713. int first_lap, cnt;
  2714. struct skb_frag_struct *frag;
  2715. element = *next_element_to_fill;
  2716. data = skb->data;
  2717. first_lap = (is_tso == 0 ? 1 : 0);
  2718. if (offset >= 0) {
  2719. data = skb->data + offset;
  2720. length -= offset;
  2721. first_lap = 0;
  2722. }
  2723. while (length > 0) {
  2724. /* length_here is the remaining amount of data in this page */
  2725. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  2726. if (length < length_here)
  2727. length_here = length;
  2728. buffer->element[element].addr = data;
  2729. buffer->element[element].length = length_here;
  2730. length -= length_here;
  2731. if (!length) {
  2732. if (first_lap)
  2733. if (skb_shinfo(skb)->nr_frags)
  2734. buffer->element[element].flags =
  2735. SBAL_FLAGS_FIRST_FRAG;
  2736. else
  2737. buffer->element[element].flags = 0;
  2738. else
  2739. buffer->element[element].flags =
  2740. SBAL_FLAGS_MIDDLE_FRAG;
  2741. } else {
  2742. if (first_lap)
  2743. buffer->element[element].flags =
  2744. SBAL_FLAGS_FIRST_FRAG;
  2745. else
  2746. buffer->element[element].flags =
  2747. SBAL_FLAGS_MIDDLE_FRAG;
  2748. }
  2749. data += length_here;
  2750. element++;
  2751. first_lap = 0;
  2752. }
  2753. for (cnt = 0; cnt < skb_shinfo(skb)->nr_frags; cnt++) {
  2754. frag = &skb_shinfo(skb)->frags[cnt];
  2755. buffer->element[element].addr = (char *)page_to_phys(frag->page)
  2756. + frag->page_offset;
  2757. buffer->element[element].length = frag->size;
  2758. buffer->element[element].flags = SBAL_FLAGS_MIDDLE_FRAG;
  2759. element++;
  2760. }
  2761. if (buffer->element[element - 1].flags)
  2762. buffer->element[element - 1].flags = SBAL_FLAGS_LAST_FRAG;
  2763. *next_element_to_fill = element;
  2764. }
  2765. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  2766. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
  2767. struct qeth_hdr *hdr, int offset, int hd_len)
  2768. {
  2769. struct qdio_buffer *buffer;
  2770. int flush_cnt = 0, hdr_len, large_send = 0;
  2771. buffer = buf->buffer;
  2772. atomic_inc(&skb->users);
  2773. skb_queue_tail(&buf->skb_list, skb);
  2774. /*check first on TSO ....*/
  2775. if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  2776. int element = buf->next_element_to_fill;
  2777. hdr_len = sizeof(struct qeth_hdr_tso) +
  2778. ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
  2779. /*fill first buffer entry only with header information */
  2780. buffer->element[element].addr = skb->data;
  2781. buffer->element[element].length = hdr_len;
  2782. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2783. buf->next_element_to_fill++;
  2784. skb->data += hdr_len;
  2785. skb->len -= hdr_len;
  2786. large_send = 1;
  2787. }
  2788. if (offset >= 0) {
  2789. int element = buf->next_element_to_fill;
  2790. buffer->element[element].addr = hdr;
  2791. buffer->element[element].length = sizeof(struct qeth_hdr) +
  2792. hd_len;
  2793. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2794. buf->is_header[element] = 1;
  2795. buf->next_element_to_fill++;
  2796. }
  2797. __qeth_fill_buffer(skb, buffer, large_send,
  2798. (int *)&buf->next_element_to_fill, offset);
  2799. if (!queue->do_pack) {
  2800. QETH_CARD_TEXT(queue->card, 6, "fillbfnp");
  2801. /* set state to PRIMED -> will be flushed */
  2802. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2803. flush_cnt = 1;
  2804. } else {
  2805. QETH_CARD_TEXT(queue->card, 6, "fillbfpa");
  2806. if (queue->card->options.performance_stats)
  2807. queue->card->perf_stats.skbs_sent_pack++;
  2808. if (buf->next_element_to_fill >=
  2809. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  2810. /*
  2811. * packed buffer if full -> set state PRIMED
  2812. * -> will be flushed
  2813. */
  2814. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2815. flush_cnt = 1;
  2816. }
  2817. }
  2818. return flush_cnt;
  2819. }
  2820. int qeth_do_send_packet_fast(struct qeth_card *card,
  2821. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  2822. struct qeth_hdr *hdr, int elements_needed,
  2823. int offset, int hd_len)
  2824. {
  2825. struct qeth_qdio_out_buffer *buffer;
  2826. struct sk_buff *skb1;
  2827. struct qeth_skb_data *retry_ctrl;
  2828. int index;
  2829. int rc;
  2830. /* spin until we get the queue ... */
  2831. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2832. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2833. /* ... now we've got the queue */
  2834. index = queue->next_buf_to_fill;
  2835. buffer = &queue->bufs[queue->next_buf_to_fill];
  2836. /*
  2837. * check if buffer is empty to make sure that we do not 'overtake'
  2838. * ourselves and try to fill a buffer that is already primed
  2839. */
  2840. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  2841. goto out;
  2842. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  2843. QDIO_MAX_BUFFERS_PER_Q;
  2844. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2845. qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
  2846. qeth_flush_buffers(queue, index, 1);
  2847. if (queue->sync_iqdio_error == 2) {
  2848. skb1 = skb_dequeue(&buffer->skb_list);
  2849. while (skb1) {
  2850. atomic_dec(&skb1->users);
  2851. skb1 = skb_dequeue(&buffer->skb_list);
  2852. }
  2853. retry_ctrl = (struct qeth_skb_data *) &skb->cb[16];
  2854. if (retry_ctrl->magic != QETH_SKB_MAGIC) {
  2855. retry_ctrl->magic = QETH_SKB_MAGIC;
  2856. retry_ctrl->count = 0;
  2857. }
  2858. if (retry_ctrl->count < QETH_SIGA_CC2_RETRIES) {
  2859. retry_ctrl->count++;
  2860. rc = dev_queue_xmit(skb);
  2861. } else {
  2862. dev_kfree_skb_any(skb);
  2863. QETH_CARD_TEXT(card, 2, "qrdrop");
  2864. }
  2865. }
  2866. return 0;
  2867. out:
  2868. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2869. return -EBUSY;
  2870. }
  2871. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  2872. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  2873. struct sk_buff *skb, struct qeth_hdr *hdr,
  2874. int elements_needed)
  2875. {
  2876. struct qeth_qdio_out_buffer *buffer;
  2877. int start_index;
  2878. int flush_count = 0;
  2879. int do_pack = 0;
  2880. int tmp;
  2881. int rc = 0;
  2882. /* spin until we get the queue ... */
  2883. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2884. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2885. start_index = queue->next_buf_to_fill;
  2886. buffer = &queue->bufs[queue->next_buf_to_fill];
  2887. /*
  2888. * check if buffer is empty to make sure that we do not 'overtake'
  2889. * ourselves and try to fill a buffer that is already primed
  2890. */
  2891. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  2892. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2893. return -EBUSY;
  2894. }
  2895. /* check if we need to switch packing state of this queue */
  2896. qeth_switch_to_packing_if_needed(queue);
  2897. if (queue->do_pack) {
  2898. do_pack = 1;
  2899. /* does packet fit in current buffer? */
  2900. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  2901. buffer->next_element_to_fill) < elements_needed) {
  2902. /* ... no -> set state PRIMED */
  2903. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2904. flush_count++;
  2905. queue->next_buf_to_fill =
  2906. (queue->next_buf_to_fill + 1) %
  2907. QDIO_MAX_BUFFERS_PER_Q;
  2908. buffer = &queue->bufs[queue->next_buf_to_fill];
  2909. /* we did a step forward, so check buffer state
  2910. * again */
  2911. if (atomic_read(&buffer->state) !=
  2912. QETH_QDIO_BUF_EMPTY) {
  2913. qeth_flush_buffers(queue, start_index,
  2914. flush_count);
  2915. atomic_set(&queue->state,
  2916. QETH_OUT_Q_UNLOCKED);
  2917. return -EBUSY;
  2918. }
  2919. }
  2920. }
  2921. tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
  2922. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  2923. QDIO_MAX_BUFFERS_PER_Q;
  2924. flush_count += tmp;
  2925. if (flush_count)
  2926. qeth_flush_buffers(queue, start_index, flush_count);
  2927. else if (!atomic_read(&queue->set_pci_flags_count))
  2928. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  2929. /*
  2930. * queue->state will go from LOCKED -> UNLOCKED or from
  2931. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  2932. * (switch packing state or flush buffer to get another pci flag out).
  2933. * In that case we will enter this loop
  2934. */
  2935. while (atomic_dec_return(&queue->state)) {
  2936. flush_count = 0;
  2937. start_index = queue->next_buf_to_fill;
  2938. /* check if we can go back to non-packing state */
  2939. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  2940. /*
  2941. * check if we need to flush a packing buffer to get a pci
  2942. * flag out on the queue
  2943. */
  2944. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  2945. flush_count += qeth_flush_buffers_on_no_pci(queue);
  2946. if (flush_count)
  2947. qeth_flush_buffers(queue, start_index, flush_count);
  2948. }
  2949. /* at this point the queue is UNLOCKED again */
  2950. if (queue->card->options.performance_stats && do_pack)
  2951. queue->card->perf_stats.bufs_sent_pack += flush_count;
  2952. return rc;
  2953. }
  2954. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  2955. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  2956. struct qeth_reply *reply, unsigned long data)
  2957. {
  2958. struct qeth_ipa_cmd *cmd;
  2959. struct qeth_ipacmd_setadpparms *setparms;
  2960. QETH_CARD_TEXT(card, 4, "prmadpcb");
  2961. cmd = (struct qeth_ipa_cmd *) data;
  2962. setparms = &(cmd->data.setadapterparms);
  2963. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2964. if (cmd->hdr.return_code) {
  2965. QETH_CARD_TEXT_(card, 4, "prmrc%2.2x", cmd->hdr.return_code);
  2966. setparms->data.mode = SET_PROMISC_MODE_OFF;
  2967. }
  2968. card->info.promisc_mode = setparms->data.mode;
  2969. return 0;
  2970. }
  2971. void qeth_setadp_promisc_mode(struct qeth_card *card)
  2972. {
  2973. enum qeth_ipa_promisc_modes mode;
  2974. struct net_device *dev = card->dev;
  2975. struct qeth_cmd_buffer *iob;
  2976. struct qeth_ipa_cmd *cmd;
  2977. QETH_CARD_TEXT(card, 4, "setprom");
  2978. if (((dev->flags & IFF_PROMISC) &&
  2979. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  2980. (!(dev->flags & IFF_PROMISC) &&
  2981. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  2982. return;
  2983. mode = SET_PROMISC_MODE_OFF;
  2984. if (dev->flags & IFF_PROMISC)
  2985. mode = SET_PROMISC_MODE_ON;
  2986. QETH_CARD_TEXT_(card, 4, "mode:%x", mode);
  2987. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  2988. sizeof(struct qeth_ipacmd_setadpparms));
  2989. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  2990. cmd->data.setadapterparms.data.mode = mode;
  2991. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  2992. }
  2993. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  2994. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  2995. {
  2996. struct qeth_card *card;
  2997. char dbf_text[15];
  2998. card = dev->ml_priv;
  2999. QETH_CARD_TEXT(card, 4, "chgmtu");
  3000. sprintf(dbf_text, "%8x", new_mtu);
  3001. QETH_CARD_TEXT(card, 4, dbf_text);
  3002. if (new_mtu < 64)
  3003. return -EINVAL;
  3004. if (new_mtu > 65535)
  3005. return -EINVAL;
  3006. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  3007. (!qeth_mtu_is_valid(card, new_mtu)))
  3008. return -EINVAL;
  3009. dev->mtu = new_mtu;
  3010. return 0;
  3011. }
  3012. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  3013. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  3014. {
  3015. struct qeth_card *card;
  3016. card = dev->ml_priv;
  3017. QETH_CARD_TEXT(card, 5, "getstat");
  3018. return &card->stats;
  3019. }
  3020. EXPORT_SYMBOL_GPL(qeth_get_stats);
  3021. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  3022. struct qeth_reply *reply, unsigned long data)
  3023. {
  3024. struct qeth_ipa_cmd *cmd;
  3025. QETH_CARD_TEXT(card, 4, "chgmaccb");
  3026. cmd = (struct qeth_ipa_cmd *) data;
  3027. if (!card->options.layer2 ||
  3028. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  3029. memcpy(card->dev->dev_addr,
  3030. &cmd->data.setadapterparms.data.change_addr.addr,
  3031. OSA_ADDR_LEN);
  3032. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3033. }
  3034. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3035. return 0;
  3036. }
  3037. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3038. {
  3039. int rc;
  3040. struct qeth_cmd_buffer *iob;
  3041. struct qeth_ipa_cmd *cmd;
  3042. QETH_CARD_TEXT(card, 4, "chgmac");
  3043. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3044. sizeof(struct qeth_ipacmd_setadpparms));
  3045. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3046. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3047. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3048. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3049. card->dev->dev_addr, OSA_ADDR_LEN);
  3050. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3051. NULL);
  3052. return rc;
  3053. }
  3054. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3055. static int qeth_setadpparms_set_access_ctrl_cb(struct qeth_card *card,
  3056. struct qeth_reply *reply, unsigned long data)
  3057. {
  3058. struct qeth_ipa_cmd *cmd;
  3059. struct qeth_set_access_ctrl *access_ctrl_req;
  3060. int rc;
  3061. QETH_CARD_TEXT(card, 4, "setaccb");
  3062. cmd = (struct qeth_ipa_cmd *) data;
  3063. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3064. QETH_DBF_TEXT_(SETUP, 2, "setaccb");
  3065. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3066. QETH_DBF_TEXT_(SETUP, 2, "rc=%d",
  3067. cmd->data.setadapterparms.hdr.return_code);
  3068. switch (cmd->data.setadapterparms.hdr.return_code) {
  3069. case SET_ACCESS_CTRL_RC_SUCCESS:
  3070. case SET_ACCESS_CTRL_RC_ALREADY_NOT_ISOLATED:
  3071. case SET_ACCESS_CTRL_RC_ALREADY_ISOLATED:
  3072. {
  3073. card->options.isolation = access_ctrl_req->subcmd_code;
  3074. if (card->options.isolation == ISOLATION_MODE_NONE) {
  3075. dev_info(&card->gdev->dev,
  3076. "QDIO data connection isolation is deactivated\n");
  3077. } else {
  3078. dev_info(&card->gdev->dev,
  3079. "QDIO data connection isolation is activated\n");
  3080. }
  3081. QETH_DBF_MESSAGE(3, "OK:SET_ACCESS_CTRL(%s, %d)==%d\n",
  3082. card->gdev->dev.kobj.name,
  3083. access_ctrl_req->subcmd_code,
  3084. cmd->data.setadapterparms.hdr.return_code);
  3085. rc = 0;
  3086. break;
  3087. }
  3088. case SET_ACCESS_CTRL_RC_NOT_SUPPORTED:
  3089. {
  3090. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_CTRL(%s,%d)==%d\n",
  3091. card->gdev->dev.kobj.name,
  3092. access_ctrl_req->subcmd_code,
  3093. cmd->data.setadapterparms.hdr.return_code);
  3094. dev_err(&card->gdev->dev, "Adapter does not "
  3095. "support QDIO data connection isolation\n");
  3096. /* ensure isolation mode is "none" */
  3097. card->options.isolation = ISOLATION_MODE_NONE;
  3098. rc = -EOPNOTSUPP;
  3099. break;
  3100. }
  3101. case SET_ACCESS_CTRL_RC_NONE_SHARED_ADAPTER:
  3102. {
  3103. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3104. card->gdev->dev.kobj.name,
  3105. access_ctrl_req->subcmd_code,
  3106. cmd->data.setadapterparms.hdr.return_code);
  3107. dev_err(&card->gdev->dev,
  3108. "Adapter is dedicated. "
  3109. "QDIO data connection isolation not supported\n");
  3110. /* ensure isolation mode is "none" */
  3111. card->options.isolation = ISOLATION_MODE_NONE;
  3112. rc = -EOPNOTSUPP;
  3113. break;
  3114. }
  3115. case SET_ACCESS_CTRL_RC_ACTIVE_CHECKSUM_OFF:
  3116. {
  3117. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3118. card->gdev->dev.kobj.name,
  3119. access_ctrl_req->subcmd_code,
  3120. cmd->data.setadapterparms.hdr.return_code);
  3121. dev_err(&card->gdev->dev,
  3122. "TSO does not permit QDIO data connection isolation\n");
  3123. /* ensure isolation mode is "none" */
  3124. card->options.isolation = ISOLATION_MODE_NONE;
  3125. rc = -EPERM;
  3126. break;
  3127. }
  3128. default:
  3129. {
  3130. /* this should never happen */
  3131. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d"
  3132. "==UNKNOWN\n",
  3133. card->gdev->dev.kobj.name,
  3134. access_ctrl_req->subcmd_code,
  3135. cmd->data.setadapterparms.hdr.return_code);
  3136. /* ensure isolation mode is "none" */
  3137. card->options.isolation = ISOLATION_MODE_NONE;
  3138. rc = 0;
  3139. break;
  3140. }
  3141. }
  3142. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3143. return rc;
  3144. }
  3145. static int qeth_setadpparms_set_access_ctrl(struct qeth_card *card,
  3146. enum qeth_ipa_isolation_modes isolation)
  3147. {
  3148. int rc;
  3149. struct qeth_cmd_buffer *iob;
  3150. struct qeth_ipa_cmd *cmd;
  3151. struct qeth_set_access_ctrl *access_ctrl_req;
  3152. QETH_CARD_TEXT(card, 4, "setacctl");
  3153. QETH_DBF_TEXT_(SETUP, 2, "setacctl");
  3154. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3155. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_ACCESS_CONTROL,
  3156. sizeof(struct qeth_ipacmd_setadpparms_hdr) +
  3157. sizeof(struct qeth_set_access_ctrl));
  3158. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3159. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3160. access_ctrl_req->subcmd_code = isolation;
  3161. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_set_access_ctrl_cb,
  3162. NULL);
  3163. QETH_DBF_TEXT_(SETUP, 2, "rc=%d", rc);
  3164. return rc;
  3165. }
  3166. int qeth_set_access_ctrl_online(struct qeth_card *card)
  3167. {
  3168. int rc = 0;
  3169. QETH_CARD_TEXT(card, 4, "setactlo");
  3170. if ((card->info.type == QETH_CARD_TYPE_OSD ||
  3171. card->info.type == QETH_CARD_TYPE_OSX) &&
  3172. qeth_adp_supported(card, IPA_SETADP_SET_ACCESS_CONTROL)) {
  3173. rc = qeth_setadpparms_set_access_ctrl(card,
  3174. card->options.isolation);
  3175. if (rc) {
  3176. QETH_DBF_MESSAGE(3,
  3177. "IPA(SET_ACCESS_CTRL,%s,%d) sent failed\n",
  3178. card->gdev->dev.kobj.name,
  3179. rc);
  3180. }
  3181. } else if (card->options.isolation != ISOLATION_MODE_NONE) {
  3182. card->options.isolation = ISOLATION_MODE_NONE;
  3183. dev_err(&card->gdev->dev, "Adapter does not "
  3184. "support QDIO data connection isolation\n");
  3185. rc = -EOPNOTSUPP;
  3186. }
  3187. return rc;
  3188. }
  3189. EXPORT_SYMBOL_GPL(qeth_set_access_ctrl_online);
  3190. void qeth_tx_timeout(struct net_device *dev)
  3191. {
  3192. struct qeth_card *card;
  3193. card = dev->ml_priv;
  3194. QETH_CARD_TEXT(card, 4, "txtimeo");
  3195. card->stats.tx_errors++;
  3196. qeth_schedule_recovery(card);
  3197. }
  3198. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3199. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3200. {
  3201. struct qeth_card *card = dev->ml_priv;
  3202. int rc = 0;
  3203. switch (regnum) {
  3204. case MII_BMCR: /* Basic mode control register */
  3205. rc = BMCR_FULLDPLX;
  3206. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3207. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3208. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3209. rc |= BMCR_SPEED100;
  3210. break;
  3211. case MII_BMSR: /* Basic mode status register */
  3212. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3213. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3214. BMSR_100BASE4;
  3215. break;
  3216. case MII_PHYSID1: /* PHYS ID 1 */
  3217. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3218. dev->dev_addr[2];
  3219. rc = (rc >> 5) & 0xFFFF;
  3220. break;
  3221. case MII_PHYSID2: /* PHYS ID 2 */
  3222. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3223. break;
  3224. case MII_ADVERTISE: /* Advertisement control reg */
  3225. rc = ADVERTISE_ALL;
  3226. break;
  3227. case MII_LPA: /* Link partner ability reg */
  3228. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3229. LPA_100BASE4 | LPA_LPACK;
  3230. break;
  3231. case MII_EXPANSION: /* Expansion register */
  3232. break;
  3233. case MII_DCOUNTER: /* disconnect counter */
  3234. break;
  3235. case MII_FCSCOUNTER: /* false carrier counter */
  3236. break;
  3237. case MII_NWAYTEST: /* N-way auto-neg test register */
  3238. break;
  3239. case MII_RERRCOUNTER: /* rx error counter */
  3240. rc = card->stats.rx_errors;
  3241. break;
  3242. case MII_SREVISION: /* silicon revision */
  3243. break;
  3244. case MII_RESV1: /* reserved 1 */
  3245. break;
  3246. case MII_LBRERROR: /* loopback, rx, bypass error */
  3247. break;
  3248. case MII_PHYADDR: /* physical address */
  3249. break;
  3250. case MII_RESV2: /* reserved 2 */
  3251. break;
  3252. case MII_TPISTATUS: /* TPI status for 10mbps */
  3253. break;
  3254. case MII_NCONFIG: /* network interface config */
  3255. break;
  3256. default:
  3257. break;
  3258. }
  3259. return rc;
  3260. }
  3261. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3262. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3263. struct qeth_cmd_buffer *iob, int len,
  3264. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3265. unsigned long),
  3266. void *reply_param)
  3267. {
  3268. u16 s1, s2;
  3269. QETH_CARD_TEXT(card, 4, "sendsnmp");
  3270. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3271. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3272. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3273. /* adjust PDU length fields in IPA_PDU_HEADER */
  3274. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3275. s2 = (u32) len;
  3276. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3277. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3278. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3279. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3280. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3281. reply_cb, reply_param);
  3282. }
  3283. static int qeth_snmp_command_cb(struct qeth_card *card,
  3284. struct qeth_reply *reply, unsigned long sdata)
  3285. {
  3286. struct qeth_ipa_cmd *cmd;
  3287. struct qeth_arp_query_info *qinfo;
  3288. struct qeth_snmp_cmd *snmp;
  3289. unsigned char *data;
  3290. __u16 data_len;
  3291. QETH_CARD_TEXT(card, 3, "snpcmdcb");
  3292. cmd = (struct qeth_ipa_cmd *) sdata;
  3293. data = (unsigned char *)((char *)cmd - reply->offset);
  3294. qinfo = (struct qeth_arp_query_info *) reply->param;
  3295. snmp = &cmd->data.setadapterparms.data.snmp;
  3296. if (cmd->hdr.return_code) {
  3297. QETH_CARD_TEXT_(card, 4, "scer1%i", cmd->hdr.return_code);
  3298. return 0;
  3299. }
  3300. if (cmd->data.setadapterparms.hdr.return_code) {
  3301. cmd->hdr.return_code =
  3302. cmd->data.setadapterparms.hdr.return_code;
  3303. QETH_CARD_TEXT_(card, 4, "scer2%i", cmd->hdr.return_code);
  3304. return 0;
  3305. }
  3306. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3307. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3308. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3309. else
  3310. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3311. /* check if there is enough room in userspace */
  3312. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3313. QETH_CARD_TEXT_(card, 4, "scer3%i", -ENOMEM);
  3314. cmd->hdr.return_code = -ENOMEM;
  3315. return 0;
  3316. }
  3317. QETH_CARD_TEXT_(card, 4, "snore%i",
  3318. cmd->data.setadapterparms.hdr.used_total);
  3319. QETH_CARD_TEXT_(card, 4, "sseqn%i",
  3320. cmd->data.setadapterparms.hdr.seq_no);
  3321. /*copy entries to user buffer*/
  3322. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3323. memcpy(qinfo->udata + qinfo->udata_offset,
  3324. (char *)snmp,
  3325. data_len + offsetof(struct qeth_snmp_cmd, data));
  3326. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3327. } else {
  3328. memcpy(qinfo->udata + qinfo->udata_offset,
  3329. (char *)&snmp->request, data_len);
  3330. }
  3331. qinfo->udata_offset += data_len;
  3332. /* check if all replies received ... */
  3333. QETH_CARD_TEXT_(card, 4, "srtot%i",
  3334. cmd->data.setadapterparms.hdr.used_total);
  3335. QETH_CARD_TEXT_(card, 4, "srseq%i",
  3336. cmd->data.setadapterparms.hdr.seq_no);
  3337. if (cmd->data.setadapterparms.hdr.seq_no <
  3338. cmd->data.setadapterparms.hdr.used_total)
  3339. return 1;
  3340. return 0;
  3341. }
  3342. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3343. {
  3344. struct qeth_cmd_buffer *iob;
  3345. struct qeth_ipa_cmd *cmd;
  3346. struct qeth_snmp_ureq *ureq;
  3347. int req_len;
  3348. struct qeth_arp_query_info qinfo = {0, };
  3349. int rc = 0;
  3350. QETH_CARD_TEXT(card, 3, "snmpcmd");
  3351. if (card->info.guestlan)
  3352. return -EOPNOTSUPP;
  3353. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3354. (!card->options.layer2)) {
  3355. return -EOPNOTSUPP;
  3356. }
  3357. /* skip 4 bytes (data_len struct member) to get req_len */
  3358. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3359. return -EFAULT;
  3360. ureq = kmalloc(req_len+sizeof(struct qeth_snmp_ureq_hdr), GFP_KERNEL);
  3361. if (!ureq) {
  3362. QETH_CARD_TEXT(card, 2, "snmpnome");
  3363. return -ENOMEM;
  3364. }
  3365. if (copy_from_user(ureq, udata,
  3366. req_len + sizeof(struct qeth_snmp_ureq_hdr))) {
  3367. kfree(ureq);
  3368. return -EFAULT;
  3369. }
  3370. qinfo.udata_len = ureq->hdr.data_len;
  3371. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3372. if (!qinfo.udata) {
  3373. kfree(ureq);
  3374. return -ENOMEM;
  3375. }
  3376. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3377. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3378. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3379. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3380. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3381. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3382. qeth_snmp_command_cb, (void *)&qinfo);
  3383. if (rc)
  3384. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  3385. QETH_CARD_IFNAME(card), rc);
  3386. else {
  3387. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3388. rc = -EFAULT;
  3389. }
  3390. kfree(ureq);
  3391. kfree(qinfo.udata);
  3392. return rc;
  3393. }
  3394. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3395. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  3396. {
  3397. switch (card->info.type) {
  3398. case QETH_CARD_TYPE_IQD:
  3399. return 2;
  3400. default:
  3401. return 0;
  3402. }
  3403. }
  3404. static int qeth_qdio_establish(struct qeth_card *card)
  3405. {
  3406. struct qdio_initialize init_data;
  3407. char *qib_param_field;
  3408. struct qdio_buffer **in_sbal_ptrs;
  3409. struct qdio_buffer **out_sbal_ptrs;
  3410. int i, j, k;
  3411. int rc = 0;
  3412. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  3413. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  3414. GFP_KERNEL);
  3415. if (!qib_param_field)
  3416. return -ENOMEM;
  3417. qeth_create_qib_param_field(card, qib_param_field);
  3418. qeth_create_qib_param_field_blkt(card, qib_param_field);
  3419. in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  3420. GFP_KERNEL);
  3421. if (!in_sbal_ptrs) {
  3422. kfree(qib_param_field);
  3423. return -ENOMEM;
  3424. }
  3425. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  3426. in_sbal_ptrs[i] = (struct qdio_buffer *)
  3427. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  3428. out_sbal_ptrs =
  3429. kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  3430. sizeof(void *), GFP_KERNEL);
  3431. if (!out_sbal_ptrs) {
  3432. kfree(in_sbal_ptrs);
  3433. kfree(qib_param_field);
  3434. return -ENOMEM;
  3435. }
  3436. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  3437. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  3438. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  3439. card->qdio.out_qs[i]->bufs[j].buffer);
  3440. }
  3441. memset(&init_data, 0, sizeof(struct qdio_initialize));
  3442. init_data.cdev = CARD_DDEV(card);
  3443. init_data.q_format = qeth_get_qdio_q_format(card);
  3444. init_data.qib_param_field_format = 0;
  3445. init_data.qib_param_field = qib_param_field;
  3446. init_data.no_input_qs = 1;
  3447. init_data.no_output_qs = card->qdio.no_out_queues;
  3448. init_data.input_handler = card->discipline.input_handler;
  3449. init_data.output_handler = card->discipline.output_handler;
  3450. init_data.int_parm = (unsigned long) card;
  3451. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  3452. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  3453. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  3454. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  3455. rc = qdio_allocate(&init_data);
  3456. if (rc) {
  3457. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3458. goto out;
  3459. }
  3460. rc = qdio_establish(&init_data);
  3461. if (rc) {
  3462. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3463. qdio_free(CARD_DDEV(card));
  3464. }
  3465. }
  3466. out:
  3467. kfree(out_sbal_ptrs);
  3468. kfree(in_sbal_ptrs);
  3469. kfree(qib_param_field);
  3470. return rc;
  3471. }
  3472. static void qeth_core_free_card(struct qeth_card *card)
  3473. {
  3474. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  3475. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  3476. qeth_clean_channel(&card->read);
  3477. qeth_clean_channel(&card->write);
  3478. if (card->dev)
  3479. free_netdev(card->dev);
  3480. kfree(card->ip_tbd_list);
  3481. qeth_free_qdio_buffers(card);
  3482. unregister_service_level(&card->qeth_service_level);
  3483. kfree(card);
  3484. }
  3485. static struct ccw_device_id qeth_ids[] = {
  3486. {CCW_DEVICE_DEVTYPE(0x1731, 0x01, 0x1732, 0x01),
  3487. .driver_info = QETH_CARD_TYPE_OSD},
  3488. {CCW_DEVICE_DEVTYPE(0x1731, 0x05, 0x1732, 0x05),
  3489. .driver_info = QETH_CARD_TYPE_IQD},
  3490. {CCW_DEVICE_DEVTYPE(0x1731, 0x06, 0x1732, 0x06),
  3491. .driver_info = QETH_CARD_TYPE_OSN},
  3492. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x03),
  3493. .driver_info = QETH_CARD_TYPE_OSM},
  3494. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x02),
  3495. .driver_info = QETH_CARD_TYPE_OSX},
  3496. {},
  3497. };
  3498. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  3499. static struct ccw_driver qeth_ccw_driver = {
  3500. .name = "qeth",
  3501. .ids = qeth_ids,
  3502. .probe = ccwgroup_probe_ccwdev,
  3503. .remove = ccwgroup_remove_ccwdev,
  3504. };
  3505. static int qeth_core_driver_group(const char *buf, struct device *root_dev,
  3506. unsigned long driver_id)
  3507. {
  3508. return ccwgroup_create_from_string(root_dev, driver_id,
  3509. &qeth_ccw_driver, 3, buf);
  3510. }
  3511. int qeth_core_hardsetup_card(struct qeth_card *card)
  3512. {
  3513. int retries = 0;
  3514. int rc;
  3515. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  3516. atomic_set(&card->force_alloc_skb, 0);
  3517. retry:
  3518. if (retries)
  3519. QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n",
  3520. dev_name(&card->gdev->dev));
  3521. ccw_device_set_offline(CARD_DDEV(card));
  3522. ccw_device_set_offline(CARD_WDEV(card));
  3523. ccw_device_set_offline(CARD_RDEV(card));
  3524. rc = ccw_device_set_online(CARD_RDEV(card));
  3525. if (rc)
  3526. goto retriable;
  3527. rc = ccw_device_set_online(CARD_WDEV(card));
  3528. if (rc)
  3529. goto retriable;
  3530. rc = ccw_device_set_online(CARD_DDEV(card));
  3531. if (rc)
  3532. goto retriable;
  3533. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  3534. retriable:
  3535. if (rc == -ERESTARTSYS) {
  3536. QETH_DBF_TEXT(SETUP, 2, "break1");
  3537. return rc;
  3538. } else if (rc) {
  3539. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  3540. if (++retries > 3)
  3541. goto out;
  3542. else
  3543. goto retry;
  3544. }
  3545. qeth_init_tokens(card);
  3546. qeth_init_func_level(card);
  3547. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  3548. if (rc == -ERESTARTSYS) {
  3549. QETH_DBF_TEXT(SETUP, 2, "break2");
  3550. return rc;
  3551. } else if (rc) {
  3552. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3553. if (--retries < 0)
  3554. goto out;
  3555. else
  3556. goto retry;
  3557. }
  3558. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  3559. if (rc == -ERESTARTSYS) {
  3560. QETH_DBF_TEXT(SETUP, 2, "break3");
  3561. return rc;
  3562. } else if (rc) {
  3563. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  3564. if (--retries < 0)
  3565. goto out;
  3566. else
  3567. goto retry;
  3568. }
  3569. rc = qeth_mpc_initialize(card);
  3570. if (rc) {
  3571. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3572. goto out;
  3573. }
  3574. return 0;
  3575. out:
  3576. dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "
  3577. "an error on the device\n");
  3578. QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n",
  3579. dev_name(&card->gdev->dev), rc);
  3580. return rc;
  3581. }
  3582. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  3583. static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
  3584. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  3585. {
  3586. struct page *page = virt_to_page(element->addr);
  3587. if (*pskb == NULL) {
  3588. /* the upper protocol layers assume that there is data in the
  3589. * skb itself. Copy a small amount (64 bytes) to make them
  3590. * happy. */
  3591. *pskb = dev_alloc_skb(64 + ETH_HLEN);
  3592. if (!(*pskb))
  3593. return -ENOMEM;
  3594. skb_reserve(*pskb, ETH_HLEN);
  3595. if (data_len <= 64) {
  3596. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  3597. data_len);
  3598. } else {
  3599. get_page(page);
  3600. memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
  3601. skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
  3602. data_len - 64);
  3603. (*pskb)->data_len += data_len - 64;
  3604. (*pskb)->len += data_len - 64;
  3605. (*pskb)->truesize += data_len - 64;
  3606. (*pfrag)++;
  3607. }
  3608. } else {
  3609. get_page(page);
  3610. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  3611. (*pskb)->data_len += data_len;
  3612. (*pskb)->len += data_len;
  3613. (*pskb)->truesize += data_len;
  3614. (*pfrag)++;
  3615. }
  3616. return 0;
  3617. }
  3618. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  3619. struct qdio_buffer *buffer,
  3620. struct qdio_buffer_element **__element, int *__offset,
  3621. struct qeth_hdr **hdr)
  3622. {
  3623. struct qdio_buffer_element *element = *__element;
  3624. int offset = *__offset;
  3625. struct sk_buff *skb = NULL;
  3626. int skb_len = 0;
  3627. void *data_ptr;
  3628. int data_len;
  3629. int headroom = 0;
  3630. int use_rx_sg = 0;
  3631. int frag = 0;
  3632. /* qeth_hdr must not cross element boundaries */
  3633. if (element->length < offset + sizeof(struct qeth_hdr)) {
  3634. if (qeth_is_last_sbale(element))
  3635. return NULL;
  3636. element++;
  3637. offset = 0;
  3638. if (element->length < sizeof(struct qeth_hdr))
  3639. return NULL;
  3640. }
  3641. *hdr = element->addr + offset;
  3642. offset += sizeof(struct qeth_hdr);
  3643. switch ((*hdr)->hdr.l2.id) {
  3644. case QETH_HEADER_TYPE_LAYER2:
  3645. skb_len = (*hdr)->hdr.l2.pkt_length;
  3646. break;
  3647. case QETH_HEADER_TYPE_LAYER3:
  3648. skb_len = (*hdr)->hdr.l3.length;
  3649. if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
  3650. (card->info.link_type == QETH_LINK_TYPE_HSTR))
  3651. headroom = TR_HLEN;
  3652. else
  3653. headroom = ETH_HLEN;
  3654. break;
  3655. case QETH_HEADER_TYPE_OSN:
  3656. skb_len = (*hdr)->hdr.osn.pdu_length;
  3657. headroom = sizeof(struct qeth_hdr);
  3658. break;
  3659. default:
  3660. break;
  3661. }
  3662. if (!skb_len)
  3663. return NULL;
  3664. if ((skb_len >= card->options.rx_sg_cb) &&
  3665. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  3666. (!atomic_read(&card->force_alloc_skb))) {
  3667. use_rx_sg = 1;
  3668. } else {
  3669. skb = dev_alloc_skb(skb_len + headroom);
  3670. if (!skb)
  3671. goto no_mem;
  3672. if (headroom)
  3673. skb_reserve(skb, headroom);
  3674. }
  3675. data_ptr = element->addr + offset;
  3676. while (skb_len) {
  3677. data_len = min(skb_len, (int)(element->length - offset));
  3678. if (data_len) {
  3679. if (use_rx_sg) {
  3680. if (qeth_create_skb_frag(element, &skb, offset,
  3681. &frag, data_len))
  3682. goto no_mem;
  3683. } else {
  3684. memcpy(skb_put(skb, data_len), data_ptr,
  3685. data_len);
  3686. }
  3687. }
  3688. skb_len -= data_len;
  3689. if (skb_len) {
  3690. if (qeth_is_last_sbale(element)) {
  3691. QETH_CARD_TEXT(card, 4, "unexeob");
  3692. QETH_CARD_HEX(card, 2, buffer, sizeof(void *));
  3693. dev_kfree_skb_any(skb);
  3694. card->stats.rx_errors++;
  3695. return NULL;
  3696. }
  3697. element++;
  3698. offset = 0;
  3699. data_ptr = element->addr;
  3700. } else {
  3701. offset += data_len;
  3702. }
  3703. }
  3704. *__element = element;
  3705. *__offset = offset;
  3706. if (use_rx_sg && card->options.performance_stats) {
  3707. card->perf_stats.sg_skbs_rx++;
  3708. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  3709. }
  3710. return skb;
  3711. no_mem:
  3712. if (net_ratelimit()) {
  3713. QETH_CARD_TEXT(card, 2, "noskbmem");
  3714. }
  3715. card->stats.rx_dropped++;
  3716. return NULL;
  3717. }
  3718. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  3719. static void qeth_unregister_dbf_views(void)
  3720. {
  3721. int x;
  3722. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3723. debug_unregister(qeth_dbf[x].id);
  3724. qeth_dbf[x].id = NULL;
  3725. }
  3726. }
  3727. void qeth_dbf_longtext(debug_info_t *id, int level, char *fmt, ...)
  3728. {
  3729. char dbf_txt_buf[32];
  3730. va_list args;
  3731. if (level > id->level)
  3732. return;
  3733. va_start(args, fmt);
  3734. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  3735. va_end(args);
  3736. debug_text_event(id, level, dbf_txt_buf);
  3737. }
  3738. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  3739. static int qeth_register_dbf_views(void)
  3740. {
  3741. int ret;
  3742. int x;
  3743. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3744. /* register the areas */
  3745. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  3746. qeth_dbf[x].pages,
  3747. qeth_dbf[x].areas,
  3748. qeth_dbf[x].len);
  3749. if (qeth_dbf[x].id == NULL) {
  3750. qeth_unregister_dbf_views();
  3751. return -ENOMEM;
  3752. }
  3753. /* register a view */
  3754. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  3755. if (ret) {
  3756. qeth_unregister_dbf_views();
  3757. return ret;
  3758. }
  3759. /* set a passing level */
  3760. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  3761. }
  3762. return 0;
  3763. }
  3764. int qeth_core_load_discipline(struct qeth_card *card,
  3765. enum qeth_discipline_id discipline)
  3766. {
  3767. int rc = 0;
  3768. switch (discipline) {
  3769. case QETH_DISCIPLINE_LAYER3:
  3770. card->discipline.ccwgdriver = try_then_request_module(
  3771. symbol_get(qeth_l3_ccwgroup_driver),
  3772. "qeth_l3");
  3773. break;
  3774. case QETH_DISCIPLINE_LAYER2:
  3775. card->discipline.ccwgdriver = try_then_request_module(
  3776. symbol_get(qeth_l2_ccwgroup_driver),
  3777. "qeth_l2");
  3778. break;
  3779. }
  3780. if (!card->discipline.ccwgdriver) {
  3781. dev_err(&card->gdev->dev, "There is no kernel module to "
  3782. "support discipline %d\n", discipline);
  3783. rc = -EINVAL;
  3784. }
  3785. return rc;
  3786. }
  3787. void qeth_core_free_discipline(struct qeth_card *card)
  3788. {
  3789. if (card->options.layer2)
  3790. symbol_put(qeth_l2_ccwgroup_driver);
  3791. else
  3792. symbol_put(qeth_l3_ccwgroup_driver);
  3793. card->discipline.ccwgdriver = NULL;
  3794. }
  3795. static void qeth_determine_capabilities(struct qeth_card *card)
  3796. {
  3797. int rc;
  3798. int length;
  3799. char *prcd;
  3800. QETH_DBF_TEXT(SETUP, 2, "detcapab");
  3801. rc = ccw_device_set_online(CARD_DDEV(card));
  3802. if (rc) {
  3803. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3804. goto out;
  3805. }
  3806. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  3807. if (rc) {
  3808. QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n",
  3809. dev_name(&card->gdev->dev), rc);
  3810. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3811. goto out_offline;
  3812. }
  3813. qeth_configure_unitaddr(card, prcd);
  3814. qeth_configure_blkt_default(card, prcd);
  3815. kfree(prcd);
  3816. rc = qdio_get_ssqd_desc(CARD_DDEV(card), &card->ssqd);
  3817. if (rc)
  3818. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  3819. out_offline:
  3820. ccw_device_set_offline(CARD_DDEV(card));
  3821. out:
  3822. return;
  3823. }
  3824. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  3825. {
  3826. struct qeth_card *card;
  3827. struct device *dev;
  3828. int rc;
  3829. unsigned long flags;
  3830. char dbf_name[20];
  3831. QETH_DBF_TEXT(SETUP, 2, "probedev");
  3832. dev = &gdev->dev;
  3833. if (!get_device(dev))
  3834. return -ENODEV;
  3835. QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
  3836. card = qeth_alloc_card();
  3837. if (!card) {
  3838. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  3839. rc = -ENOMEM;
  3840. goto err_dev;
  3841. }
  3842. snprintf(dbf_name, sizeof(dbf_name), "qeth_card_%s",
  3843. dev_name(&gdev->dev));
  3844. card->debug = debug_register(dbf_name, 2, 1, 8);
  3845. if (!card->debug) {
  3846. QETH_DBF_TEXT_(SETUP, 2, "%s", "qcdbf");
  3847. rc = -ENOMEM;
  3848. goto err_card;
  3849. }
  3850. debug_register_view(card->debug, &debug_hex_ascii_view);
  3851. card->read.ccwdev = gdev->cdev[0];
  3852. card->write.ccwdev = gdev->cdev[1];
  3853. card->data.ccwdev = gdev->cdev[2];
  3854. dev_set_drvdata(&gdev->dev, card);
  3855. card->gdev = gdev;
  3856. gdev->cdev[0]->handler = qeth_irq;
  3857. gdev->cdev[1]->handler = qeth_irq;
  3858. gdev->cdev[2]->handler = qeth_irq;
  3859. rc = qeth_determine_card_type(card);
  3860. if (rc) {
  3861. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3862. goto err_dbf;
  3863. }
  3864. rc = qeth_setup_card(card);
  3865. if (rc) {
  3866. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3867. goto err_dbf;
  3868. }
  3869. if (card->info.type == QETH_CARD_TYPE_OSN)
  3870. rc = qeth_core_create_osn_attributes(dev);
  3871. else
  3872. rc = qeth_core_create_device_attributes(dev);
  3873. if (rc)
  3874. goto err_dbf;
  3875. switch (card->info.type) {
  3876. case QETH_CARD_TYPE_OSN:
  3877. case QETH_CARD_TYPE_OSM:
  3878. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  3879. if (rc)
  3880. goto err_attr;
  3881. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3882. if (rc)
  3883. goto err_disc;
  3884. case QETH_CARD_TYPE_OSD:
  3885. case QETH_CARD_TYPE_OSX:
  3886. default:
  3887. break;
  3888. }
  3889. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3890. list_add_tail(&card->list, &qeth_core_card_list.list);
  3891. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3892. qeth_determine_capabilities(card);
  3893. return 0;
  3894. err_disc:
  3895. qeth_core_free_discipline(card);
  3896. err_attr:
  3897. if (card->info.type == QETH_CARD_TYPE_OSN)
  3898. qeth_core_remove_osn_attributes(dev);
  3899. else
  3900. qeth_core_remove_device_attributes(dev);
  3901. err_dbf:
  3902. debug_unregister(card->debug);
  3903. err_card:
  3904. qeth_core_free_card(card);
  3905. err_dev:
  3906. put_device(dev);
  3907. return rc;
  3908. }
  3909. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  3910. {
  3911. unsigned long flags;
  3912. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3913. QETH_DBF_TEXT(SETUP, 2, "removedv");
  3914. if (card->discipline.ccwgdriver) {
  3915. card->discipline.ccwgdriver->remove(gdev);
  3916. qeth_core_free_discipline(card);
  3917. }
  3918. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3919. qeth_core_remove_osn_attributes(&gdev->dev);
  3920. } else {
  3921. qeth_core_remove_device_attributes(&gdev->dev);
  3922. }
  3923. debug_unregister(card->debug);
  3924. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3925. list_del(&card->list);
  3926. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3927. qeth_core_free_card(card);
  3928. dev_set_drvdata(&gdev->dev, NULL);
  3929. put_device(&gdev->dev);
  3930. return;
  3931. }
  3932. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  3933. {
  3934. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3935. int rc = 0;
  3936. int def_discipline;
  3937. if (!card->discipline.ccwgdriver) {
  3938. if (card->info.type == QETH_CARD_TYPE_IQD)
  3939. def_discipline = QETH_DISCIPLINE_LAYER3;
  3940. else
  3941. def_discipline = QETH_DISCIPLINE_LAYER2;
  3942. rc = qeth_core_load_discipline(card, def_discipline);
  3943. if (rc)
  3944. goto err;
  3945. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3946. if (rc)
  3947. goto err;
  3948. }
  3949. rc = card->discipline.ccwgdriver->set_online(gdev);
  3950. err:
  3951. return rc;
  3952. }
  3953. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  3954. {
  3955. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3956. return card->discipline.ccwgdriver->set_offline(gdev);
  3957. }
  3958. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  3959. {
  3960. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3961. if (card->discipline.ccwgdriver &&
  3962. card->discipline.ccwgdriver->shutdown)
  3963. card->discipline.ccwgdriver->shutdown(gdev);
  3964. }
  3965. static int qeth_core_prepare(struct ccwgroup_device *gdev)
  3966. {
  3967. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3968. if (card->discipline.ccwgdriver &&
  3969. card->discipline.ccwgdriver->prepare)
  3970. return card->discipline.ccwgdriver->prepare(gdev);
  3971. return 0;
  3972. }
  3973. static void qeth_core_complete(struct ccwgroup_device *gdev)
  3974. {
  3975. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3976. if (card->discipline.ccwgdriver &&
  3977. card->discipline.ccwgdriver->complete)
  3978. card->discipline.ccwgdriver->complete(gdev);
  3979. }
  3980. static int qeth_core_freeze(struct ccwgroup_device *gdev)
  3981. {
  3982. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3983. if (card->discipline.ccwgdriver &&
  3984. card->discipline.ccwgdriver->freeze)
  3985. return card->discipline.ccwgdriver->freeze(gdev);
  3986. return 0;
  3987. }
  3988. static int qeth_core_thaw(struct ccwgroup_device *gdev)
  3989. {
  3990. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3991. if (card->discipline.ccwgdriver &&
  3992. card->discipline.ccwgdriver->thaw)
  3993. return card->discipline.ccwgdriver->thaw(gdev);
  3994. return 0;
  3995. }
  3996. static int qeth_core_restore(struct ccwgroup_device *gdev)
  3997. {
  3998. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3999. if (card->discipline.ccwgdriver &&
  4000. card->discipline.ccwgdriver->restore)
  4001. return card->discipline.ccwgdriver->restore(gdev);
  4002. return 0;
  4003. }
  4004. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  4005. .owner = THIS_MODULE,
  4006. .name = "qeth",
  4007. .driver_id = 0xD8C5E3C8,
  4008. .probe = qeth_core_probe_device,
  4009. .remove = qeth_core_remove_device,
  4010. .set_online = qeth_core_set_online,
  4011. .set_offline = qeth_core_set_offline,
  4012. .shutdown = qeth_core_shutdown,
  4013. .prepare = qeth_core_prepare,
  4014. .complete = qeth_core_complete,
  4015. .freeze = qeth_core_freeze,
  4016. .thaw = qeth_core_thaw,
  4017. .restore = qeth_core_restore,
  4018. };
  4019. static ssize_t
  4020. qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
  4021. size_t count)
  4022. {
  4023. int err;
  4024. err = qeth_core_driver_group(buf, qeth_core_root_dev,
  4025. qeth_core_ccwgroup_driver.driver_id);
  4026. if (err)
  4027. return err;
  4028. else
  4029. return count;
  4030. }
  4031. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  4032. static struct {
  4033. const char str[ETH_GSTRING_LEN];
  4034. } qeth_ethtool_stats_keys[] = {
  4035. /* 0 */{"rx skbs"},
  4036. {"rx buffers"},
  4037. {"tx skbs"},
  4038. {"tx buffers"},
  4039. {"tx skbs no packing"},
  4040. {"tx buffers no packing"},
  4041. {"tx skbs packing"},
  4042. {"tx buffers packing"},
  4043. {"tx sg skbs"},
  4044. {"tx sg frags"},
  4045. /* 10 */{"rx sg skbs"},
  4046. {"rx sg frags"},
  4047. {"rx sg page allocs"},
  4048. {"tx large kbytes"},
  4049. {"tx large count"},
  4050. {"tx pk state ch n->p"},
  4051. {"tx pk state ch p->n"},
  4052. {"tx pk watermark low"},
  4053. {"tx pk watermark high"},
  4054. {"queue 0 buffer usage"},
  4055. /* 20 */{"queue 1 buffer usage"},
  4056. {"queue 2 buffer usage"},
  4057. {"queue 3 buffer usage"},
  4058. {"rx handler time"},
  4059. {"rx handler count"},
  4060. {"rx do_QDIO time"},
  4061. {"rx do_QDIO count"},
  4062. {"tx handler time"},
  4063. {"tx handler count"},
  4064. {"tx time"},
  4065. /* 30 */{"tx count"},
  4066. {"tx do_QDIO time"},
  4067. {"tx do_QDIO count"},
  4068. {"tx csum"},
  4069. {"tx lin"},
  4070. };
  4071. int qeth_core_get_sset_count(struct net_device *dev, int stringset)
  4072. {
  4073. switch (stringset) {
  4074. case ETH_SS_STATS:
  4075. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  4076. default:
  4077. return -EINVAL;
  4078. }
  4079. }
  4080. EXPORT_SYMBOL_GPL(qeth_core_get_sset_count);
  4081. void qeth_core_get_ethtool_stats(struct net_device *dev,
  4082. struct ethtool_stats *stats, u64 *data)
  4083. {
  4084. struct qeth_card *card = dev->ml_priv;
  4085. data[0] = card->stats.rx_packets -
  4086. card->perf_stats.initial_rx_packets;
  4087. data[1] = card->perf_stats.bufs_rec;
  4088. data[2] = card->stats.tx_packets -
  4089. card->perf_stats.initial_tx_packets;
  4090. data[3] = card->perf_stats.bufs_sent;
  4091. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  4092. - card->perf_stats.skbs_sent_pack;
  4093. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  4094. data[6] = card->perf_stats.skbs_sent_pack;
  4095. data[7] = card->perf_stats.bufs_sent_pack;
  4096. data[8] = card->perf_stats.sg_skbs_sent;
  4097. data[9] = card->perf_stats.sg_frags_sent;
  4098. data[10] = card->perf_stats.sg_skbs_rx;
  4099. data[11] = card->perf_stats.sg_frags_rx;
  4100. data[12] = card->perf_stats.sg_alloc_page_rx;
  4101. data[13] = (card->perf_stats.large_send_bytes >> 10);
  4102. data[14] = card->perf_stats.large_send_cnt;
  4103. data[15] = card->perf_stats.sc_dp_p;
  4104. data[16] = card->perf_stats.sc_p_dp;
  4105. data[17] = QETH_LOW_WATERMARK_PACK;
  4106. data[18] = QETH_HIGH_WATERMARK_PACK;
  4107. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  4108. data[20] = (card->qdio.no_out_queues > 1) ?
  4109. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  4110. data[21] = (card->qdio.no_out_queues > 2) ?
  4111. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  4112. data[22] = (card->qdio.no_out_queues > 3) ?
  4113. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  4114. data[23] = card->perf_stats.inbound_time;
  4115. data[24] = card->perf_stats.inbound_cnt;
  4116. data[25] = card->perf_stats.inbound_do_qdio_time;
  4117. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  4118. data[27] = card->perf_stats.outbound_handler_time;
  4119. data[28] = card->perf_stats.outbound_handler_cnt;
  4120. data[29] = card->perf_stats.outbound_time;
  4121. data[30] = card->perf_stats.outbound_cnt;
  4122. data[31] = card->perf_stats.outbound_do_qdio_time;
  4123. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  4124. data[33] = card->perf_stats.tx_csum;
  4125. data[34] = card->perf_stats.tx_lin;
  4126. }
  4127. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  4128. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  4129. {
  4130. switch (stringset) {
  4131. case ETH_SS_STATS:
  4132. memcpy(data, &qeth_ethtool_stats_keys,
  4133. sizeof(qeth_ethtool_stats_keys));
  4134. break;
  4135. default:
  4136. WARN_ON(1);
  4137. break;
  4138. }
  4139. }
  4140. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  4141. void qeth_core_get_drvinfo(struct net_device *dev,
  4142. struct ethtool_drvinfo *info)
  4143. {
  4144. struct qeth_card *card = dev->ml_priv;
  4145. if (card->options.layer2)
  4146. strcpy(info->driver, "qeth_l2");
  4147. else
  4148. strcpy(info->driver, "qeth_l3");
  4149. strcpy(info->version, "1.0");
  4150. strcpy(info->fw_version, card->info.mcl_level);
  4151. sprintf(info->bus_info, "%s/%s/%s",
  4152. CARD_RDEV_ID(card),
  4153. CARD_WDEV_ID(card),
  4154. CARD_DDEV_ID(card));
  4155. }
  4156. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  4157. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  4158. struct ethtool_cmd *ecmd)
  4159. {
  4160. struct qeth_card *card = netdev->ml_priv;
  4161. enum qeth_link_types link_type;
  4162. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  4163. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  4164. else
  4165. link_type = card->info.link_type;
  4166. ecmd->transceiver = XCVR_INTERNAL;
  4167. ecmd->supported = SUPPORTED_Autoneg;
  4168. ecmd->advertising = ADVERTISED_Autoneg;
  4169. ecmd->duplex = DUPLEX_FULL;
  4170. ecmd->autoneg = AUTONEG_ENABLE;
  4171. switch (link_type) {
  4172. case QETH_LINK_TYPE_FAST_ETH:
  4173. case QETH_LINK_TYPE_LANE_ETH100:
  4174. ecmd->supported |= SUPPORTED_10baseT_Half |
  4175. SUPPORTED_10baseT_Full |
  4176. SUPPORTED_100baseT_Half |
  4177. SUPPORTED_100baseT_Full |
  4178. SUPPORTED_TP;
  4179. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4180. ADVERTISED_10baseT_Full |
  4181. ADVERTISED_100baseT_Half |
  4182. ADVERTISED_100baseT_Full |
  4183. ADVERTISED_TP;
  4184. ecmd->speed = SPEED_100;
  4185. ecmd->port = PORT_TP;
  4186. break;
  4187. case QETH_LINK_TYPE_GBIT_ETH:
  4188. case QETH_LINK_TYPE_LANE_ETH1000:
  4189. ecmd->supported |= SUPPORTED_10baseT_Half |
  4190. SUPPORTED_10baseT_Full |
  4191. SUPPORTED_100baseT_Half |
  4192. SUPPORTED_100baseT_Full |
  4193. SUPPORTED_1000baseT_Half |
  4194. SUPPORTED_1000baseT_Full |
  4195. SUPPORTED_FIBRE;
  4196. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4197. ADVERTISED_10baseT_Full |
  4198. ADVERTISED_100baseT_Half |
  4199. ADVERTISED_100baseT_Full |
  4200. ADVERTISED_1000baseT_Half |
  4201. ADVERTISED_1000baseT_Full |
  4202. ADVERTISED_FIBRE;
  4203. ecmd->speed = SPEED_1000;
  4204. ecmd->port = PORT_FIBRE;
  4205. break;
  4206. case QETH_LINK_TYPE_10GBIT_ETH:
  4207. ecmd->supported |= SUPPORTED_10baseT_Half |
  4208. SUPPORTED_10baseT_Full |
  4209. SUPPORTED_100baseT_Half |
  4210. SUPPORTED_100baseT_Full |
  4211. SUPPORTED_1000baseT_Half |
  4212. SUPPORTED_1000baseT_Full |
  4213. SUPPORTED_10000baseT_Full |
  4214. SUPPORTED_FIBRE;
  4215. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4216. ADVERTISED_10baseT_Full |
  4217. ADVERTISED_100baseT_Half |
  4218. ADVERTISED_100baseT_Full |
  4219. ADVERTISED_1000baseT_Half |
  4220. ADVERTISED_1000baseT_Full |
  4221. ADVERTISED_10000baseT_Full |
  4222. ADVERTISED_FIBRE;
  4223. ecmd->speed = SPEED_10000;
  4224. ecmd->port = PORT_FIBRE;
  4225. break;
  4226. default:
  4227. ecmd->supported |= SUPPORTED_10baseT_Half |
  4228. SUPPORTED_10baseT_Full |
  4229. SUPPORTED_TP;
  4230. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4231. ADVERTISED_10baseT_Full |
  4232. ADVERTISED_TP;
  4233. ecmd->speed = SPEED_10;
  4234. ecmd->port = PORT_TP;
  4235. }
  4236. return 0;
  4237. }
  4238. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  4239. static int __init qeth_core_init(void)
  4240. {
  4241. int rc;
  4242. pr_info("loading core functions\n");
  4243. INIT_LIST_HEAD(&qeth_core_card_list.list);
  4244. rwlock_init(&qeth_core_card_list.rwlock);
  4245. rc = qeth_register_dbf_views();
  4246. if (rc)
  4247. goto out_err;
  4248. rc = ccw_driver_register(&qeth_ccw_driver);
  4249. if (rc)
  4250. goto ccw_err;
  4251. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  4252. if (rc)
  4253. goto ccwgroup_err;
  4254. rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
  4255. &driver_attr_group);
  4256. if (rc)
  4257. goto driver_err;
  4258. qeth_core_root_dev = root_device_register("qeth");
  4259. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  4260. if (rc)
  4261. goto register_err;
  4262. qeth_core_header_cache = kmem_cache_create("qeth_hdr",
  4263. sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
  4264. if (!qeth_core_header_cache) {
  4265. rc = -ENOMEM;
  4266. goto slab_err;
  4267. }
  4268. return 0;
  4269. slab_err:
  4270. root_device_unregister(qeth_core_root_dev);
  4271. register_err:
  4272. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4273. &driver_attr_group);
  4274. driver_err:
  4275. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4276. ccwgroup_err:
  4277. ccw_driver_unregister(&qeth_ccw_driver);
  4278. ccw_err:
  4279. QETH_DBF_MESSAGE(2, "Initialization failed with code %d\n", rc);
  4280. qeth_unregister_dbf_views();
  4281. out_err:
  4282. pr_err("Initializing the qeth device driver failed\n");
  4283. return rc;
  4284. }
  4285. static void __exit qeth_core_exit(void)
  4286. {
  4287. root_device_unregister(qeth_core_root_dev);
  4288. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4289. &driver_attr_group);
  4290. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4291. ccw_driver_unregister(&qeth_ccw_driver);
  4292. kmem_cache_destroy(qeth_core_header_cache);
  4293. qeth_unregister_dbf_views();
  4294. pr_info("core functions removed\n");
  4295. }
  4296. module_init(qeth_core_init);
  4297. module_exit(qeth_core_exit);
  4298. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  4299. MODULE_DESCRIPTION("qeth core functions");
  4300. MODULE_LICENSE("GPL");