init.c 32 KB

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  1. /*
  2. * Copyright (C) 1995 Linus Torvalds
  3. * Copyright 2010 Tilera Corporation. All Rights Reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation, version 2.
  8. *
  9. * This program is distributed in the hope that it will be useful, but
  10. * WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  12. * NON INFRINGEMENT. See the GNU General Public License for
  13. * more details.
  14. */
  15. #include <linux/module.h>
  16. #include <linux/signal.h>
  17. #include <linux/sched.h>
  18. #include <linux/kernel.h>
  19. #include <linux/errno.h>
  20. #include <linux/string.h>
  21. #include <linux/types.h>
  22. #include <linux/ptrace.h>
  23. #include <linux/mman.h>
  24. #include <linux/mm.h>
  25. #include <linux/hugetlb.h>
  26. #include <linux/swap.h>
  27. #include <linux/smp.h>
  28. #include <linux/init.h>
  29. #include <linux/highmem.h>
  30. #include <linux/pagemap.h>
  31. #include <linux/poison.h>
  32. #include <linux/bootmem.h>
  33. #include <linux/slab.h>
  34. #include <linux/proc_fs.h>
  35. #include <linux/efi.h>
  36. #include <linux/memory_hotplug.h>
  37. #include <linux/uaccess.h>
  38. #include <asm/mmu_context.h>
  39. #include <asm/processor.h>
  40. #include <asm/system.h>
  41. #include <asm/pgtable.h>
  42. #include <asm/pgalloc.h>
  43. #include <asm/dma.h>
  44. #include <asm/fixmap.h>
  45. #include <asm/tlb.h>
  46. #include <asm/tlbflush.h>
  47. #include <asm/sections.h>
  48. #include <asm/setup.h>
  49. #include <asm/homecache.h>
  50. #include <hv/hypervisor.h>
  51. #include <arch/chip.h>
  52. #include "migrate.h"
  53. /*
  54. * We could set FORCE_MAX_ZONEORDER to "(HPAGE_SHIFT - PAGE_SHIFT + 1)"
  55. * in the Tile Kconfig, but this generates configure warnings.
  56. * Do it here and force people to get it right to compile this file.
  57. * The problem is that with 4KB small pages and 16MB huge pages,
  58. * the default value doesn't allow us to group enough small pages
  59. * together to make up a huge page.
  60. */
  61. #if CONFIG_FORCE_MAX_ZONEORDER < HPAGE_SHIFT - PAGE_SHIFT + 1
  62. # error "Change FORCE_MAX_ZONEORDER in arch/tile/Kconfig to match page size"
  63. #endif
  64. #define clear_pgd(pmdptr) (*(pmdptr) = hv_pte(0))
  65. #ifndef __tilegx__
  66. unsigned long VMALLOC_RESERVE = CONFIG_VMALLOC_RESERVE;
  67. EXPORT_SYMBOL(VMALLOC_RESERVE);
  68. #endif
  69. DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
  70. /* Create an L2 page table */
  71. static pte_t * __init alloc_pte(void)
  72. {
  73. return __alloc_bootmem(L2_KERNEL_PGTABLE_SIZE, HV_PAGE_TABLE_ALIGN, 0);
  74. }
  75. /*
  76. * L2 page tables per controller. We allocate these all at once from
  77. * the bootmem allocator and store them here. This saves on kernel L2
  78. * page table memory, compared to allocating a full 64K page per L2
  79. * page table, and also means that in cases where we use huge pages,
  80. * we are guaranteed to later be able to shatter those huge pages and
  81. * switch to using these page tables instead, without requiring
  82. * further allocation. Each l2_ptes[] entry points to the first page
  83. * table for the first hugepage-size piece of memory on the
  84. * controller; other page tables are just indexed directly, i.e. the
  85. * L2 page tables are contiguous in memory for each controller.
  86. */
  87. static pte_t *l2_ptes[MAX_NUMNODES];
  88. static int num_l2_ptes[MAX_NUMNODES];
  89. static void init_prealloc_ptes(int node, int pages)
  90. {
  91. BUG_ON(pages & (HV_L2_ENTRIES-1));
  92. if (pages) {
  93. num_l2_ptes[node] = pages;
  94. l2_ptes[node] = __alloc_bootmem(pages * sizeof(pte_t),
  95. HV_PAGE_TABLE_ALIGN, 0);
  96. }
  97. }
  98. pte_t *get_prealloc_pte(unsigned long pfn)
  99. {
  100. int node = pfn_to_nid(pfn);
  101. pfn &= ~(-1UL << (NR_PA_HIGHBIT_SHIFT - PAGE_SHIFT));
  102. BUG_ON(node >= MAX_NUMNODES);
  103. BUG_ON(pfn >= num_l2_ptes[node]);
  104. return &l2_ptes[node][pfn];
  105. }
  106. /*
  107. * What caching do we expect pages from the heap to have when
  108. * they are allocated during bootup? (Once we've installed the
  109. * "real" swapper_pg_dir.)
  110. */
  111. static int initial_heap_home(void)
  112. {
  113. #if CHIP_HAS_CBOX_HOME_MAP()
  114. if (hash_default)
  115. return PAGE_HOME_HASH;
  116. #endif
  117. return smp_processor_id();
  118. }
  119. /*
  120. * Place a pointer to an L2 page table in a middle page
  121. * directory entry.
  122. */
  123. static void __init assign_pte(pmd_t *pmd, pte_t *page_table)
  124. {
  125. phys_addr_t pa = __pa(page_table);
  126. unsigned long l2_ptfn = pa >> HV_LOG2_PAGE_TABLE_ALIGN;
  127. pte_t pteval = hv_pte_set_ptfn(__pgprot(_PAGE_TABLE), l2_ptfn);
  128. BUG_ON((pa & (HV_PAGE_TABLE_ALIGN-1)) != 0);
  129. pteval = pte_set_home(pteval, initial_heap_home());
  130. *(pte_t *)pmd = pteval;
  131. if (page_table != (pte_t *)pmd_page_vaddr(*pmd))
  132. BUG();
  133. }
  134. #ifdef __tilegx__
  135. #if HV_L1_SIZE != HV_L2_SIZE
  136. # error Rework assumption that L1 and L2 page tables are same size.
  137. #endif
  138. /* Since pmd_t arrays and pte_t arrays are the same size, just use casts. */
  139. static inline pmd_t *alloc_pmd(void)
  140. {
  141. return (pmd_t *)alloc_pte();
  142. }
  143. static inline void assign_pmd(pud_t *pud, pmd_t *pmd)
  144. {
  145. assign_pte((pmd_t *)pud, (pte_t *)pmd);
  146. }
  147. #endif /* __tilegx__ */
  148. /* Replace the given pmd with a full PTE table. */
  149. void __init shatter_pmd(pmd_t *pmd)
  150. {
  151. pte_t *pte = get_prealloc_pte(pte_pfn(*(pte_t *)pmd));
  152. assign_pte(pmd, pte);
  153. }
  154. #ifdef CONFIG_HIGHMEM
  155. /*
  156. * This function initializes a certain range of kernel virtual memory
  157. * with new bootmem page tables, everywhere page tables are missing in
  158. * the given range.
  159. */
  160. /*
  161. * NOTE: The pagetables are allocated contiguous on the physical space
  162. * so we can cache the place of the first one and move around without
  163. * checking the pgd every time.
  164. */
  165. static void __init page_table_range_init(unsigned long start,
  166. unsigned long end, pgd_t *pgd_base)
  167. {
  168. pgd_t *pgd;
  169. int pgd_idx;
  170. unsigned long vaddr;
  171. vaddr = start;
  172. pgd_idx = pgd_index(vaddr);
  173. pgd = pgd_base + pgd_idx;
  174. for ( ; (pgd_idx < PTRS_PER_PGD) && (vaddr != end); pgd++, pgd_idx++) {
  175. pmd_t *pmd = pmd_offset(pud_offset(pgd, vaddr), vaddr);
  176. if (pmd_none(*pmd))
  177. assign_pte(pmd, alloc_pte());
  178. vaddr += PMD_SIZE;
  179. }
  180. }
  181. #endif /* CONFIG_HIGHMEM */
  182. #if CHIP_HAS_CBOX_HOME_MAP()
  183. static int __initdata ktext_hash = 1; /* .text pages */
  184. static int __initdata kdata_hash = 1; /* .data and .bss pages */
  185. int __write_once hash_default = 1; /* kernel allocator pages */
  186. EXPORT_SYMBOL(hash_default);
  187. int __write_once kstack_hash = 1; /* if no homecaching, use h4h */
  188. #endif /* CHIP_HAS_CBOX_HOME_MAP */
  189. /*
  190. * CPUs to use to for striping the pages of kernel data. If hash-for-home
  191. * is available, this is only relevant if kcache_hash sets up the
  192. * .data and .bss to be page-homed, and we don't want the default mode
  193. * of using the full set of kernel cpus for the striping.
  194. */
  195. static __initdata struct cpumask kdata_mask;
  196. static __initdata int kdata_arg_seen;
  197. int __write_once kdata_huge; /* if no homecaching, small pages */
  198. /* Combine a generic pgprot_t with cache home to get a cache-aware pgprot. */
  199. static pgprot_t __init construct_pgprot(pgprot_t prot, int home)
  200. {
  201. prot = pte_set_home(prot, home);
  202. #if CHIP_HAS_CBOX_HOME_MAP()
  203. if (home == PAGE_HOME_IMMUTABLE) {
  204. if (ktext_hash)
  205. prot = hv_pte_set_mode(prot, HV_PTE_MODE_CACHE_HASH_L3);
  206. else
  207. prot = hv_pte_set_mode(prot, HV_PTE_MODE_CACHE_NO_L3);
  208. }
  209. #endif
  210. return prot;
  211. }
  212. /*
  213. * For a given kernel data VA, how should it be cached?
  214. * We return the complete pgprot_t with caching bits set.
  215. */
  216. static pgprot_t __init init_pgprot(ulong address)
  217. {
  218. int cpu;
  219. unsigned long page;
  220. enum { CODE_DELTA = MEM_SV_INTRPT - PAGE_OFFSET };
  221. #if CHIP_HAS_CBOX_HOME_MAP()
  222. /* For kdata=huge, everything is just hash-for-home. */
  223. if (kdata_huge)
  224. return construct_pgprot(PAGE_KERNEL, PAGE_HOME_HASH);
  225. #endif
  226. /* We map the aliased pages of permanent text inaccessible. */
  227. if (address < (ulong) _sinittext - CODE_DELTA)
  228. return PAGE_NONE;
  229. /*
  230. * We map read-only data non-coherent for performance. We could
  231. * use neighborhood caching on TILE64, but it's not clear it's a win.
  232. */
  233. if ((address >= (ulong) __start_rodata &&
  234. address < (ulong) __end_rodata) ||
  235. address == (ulong) empty_zero_page) {
  236. return construct_pgprot(PAGE_KERNEL_RO, PAGE_HOME_IMMUTABLE);
  237. }
  238. /* As a performance optimization, keep the boot init stack here. */
  239. if (address >= (ulong)&init_thread_union &&
  240. address < (ulong)&init_thread_union + THREAD_SIZE)
  241. return construct_pgprot(PAGE_KERNEL, smp_processor_id());
  242. #ifndef __tilegx__
  243. #if !ATOMIC_LOCKS_FOUND_VIA_TABLE()
  244. /* Force the atomic_locks[] array page to be hash-for-home. */
  245. if (address == (ulong) atomic_locks)
  246. return construct_pgprot(PAGE_KERNEL, PAGE_HOME_HASH);
  247. #endif
  248. #endif
  249. /*
  250. * Everything else that isn't data or bss is heap, so mark it
  251. * with the initial heap home (hash-for-home, or this cpu). This
  252. * includes any addresses after the loaded image and any address before
  253. * _einitdata, since we already captured the case of text before
  254. * _sinittext, and __pa(einittext) is approximately __pa(sinitdata).
  255. *
  256. * All the LOWMEM pages that we mark this way will get their
  257. * struct page homecache properly marked later, in set_page_homes().
  258. * The HIGHMEM pages we leave with a default zero for their
  259. * homes, but with a zero free_time we don't have to actually
  260. * do a flush action the first time we use them, either.
  261. */
  262. if (address >= (ulong) _end || address < (ulong) _einitdata)
  263. return construct_pgprot(PAGE_KERNEL, initial_heap_home());
  264. #if CHIP_HAS_CBOX_HOME_MAP()
  265. /* Use hash-for-home if requested for data/bss. */
  266. if (kdata_hash)
  267. return construct_pgprot(PAGE_KERNEL, PAGE_HOME_HASH);
  268. #endif
  269. /*
  270. * Make the w1data homed like heap to start with, to avoid
  271. * making it part of the page-striped data area when we're just
  272. * going to convert it to read-only soon anyway.
  273. */
  274. if (address >= (ulong)__w1data_begin && address < (ulong)__w1data_end)
  275. return construct_pgprot(PAGE_KERNEL, initial_heap_home());
  276. /*
  277. * Otherwise we just hand out consecutive cpus. To avoid
  278. * requiring this function to hold state, we just walk forward from
  279. * _sdata by PAGE_SIZE, skipping the readonly and init data, to reach
  280. * the requested address, while walking cpu home around kdata_mask.
  281. * This is typically no more than a dozen or so iterations.
  282. */
  283. page = (((ulong)__w1data_end) + PAGE_SIZE - 1) & PAGE_MASK;
  284. BUG_ON(address < page || address >= (ulong)_end);
  285. cpu = cpumask_first(&kdata_mask);
  286. for (; page < address; page += PAGE_SIZE) {
  287. if (page >= (ulong)&init_thread_union &&
  288. page < (ulong)&init_thread_union + THREAD_SIZE)
  289. continue;
  290. if (page == (ulong)empty_zero_page)
  291. continue;
  292. #ifndef __tilegx__
  293. #if !ATOMIC_LOCKS_FOUND_VIA_TABLE()
  294. if (page == (ulong)atomic_locks)
  295. continue;
  296. #endif
  297. #endif
  298. cpu = cpumask_next(cpu, &kdata_mask);
  299. if (cpu == NR_CPUS)
  300. cpu = cpumask_first(&kdata_mask);
  301. }
  302. return construct_pgprot(PAGE_KERNEL, cpu);
  303. }
  304. /*
  305. * This function sets up how we cache the kernel text. If we have
  306. * hash-for-home support, normally that is used instead (see the
  307. * kcache_hash boot flag for more information). But if we end up
  308. * using a page-based caching technique, this option sets up the
  309. * details of that. In addition, the "ktext=nocache" option may
  310. * always be used to disable local caching of text pages, if desired.
  311. */
  312. static int __initdata ktext_arg_seen;
  313. static int __initdata ktext_small;
  314. static int __initdata ktext_local;
  315. static int __initdata ktext_all;
  316. static int __initdata ktext_nondataplane;
  317. static int __initdata ktext_nocache;
  318. static struct cpumask __initdata ktext_mask;
  319. static int __init setup_ktext(char *str)
  320. {
  321. if (str == NULL)
  322. return -EINVAL;
  323. /* If you have a leading "nocache", turn off ktext caching */
  324. if (strncmp(str, "nocache", 7) == 0) {
  325. ktext_nocache = 1;
  326. pr_info("ktext: disabling local caching of kernel text\n");
  327. str += 7;
  328. if (*str == ',')
  329. ++str;
  330. if (*str == '\0')
  331. return 0;
  332. }
  333. ktext_arg_seen = 1;
  334. /* Default setting on Tile64: use a huge page */
  335. if (strcmp(str, "huge") == 0)
  336. pr_info("ktext: using one huge locally cached page\n");
  337. /* Pay TLB cost but get no cache benefit: cache small pages locally */
  338. else if (strcmp(str, "local") == 0) {
  339. ktext_small = 1;
  340. ktext_local = 1;
  341. pr_info("ktext: using small pages with local caching\n");
  342. }
  343. /* Neighborhood cache ktext pages on all cpus. */
  344. else if (strcmp(str, "all") == 0) {
  345. ktext_small = 1;
  346. ktext_all = 1;
  347. pr_info("ktext: using maximal caching neighborhood\n");
  348. }
  349. /* Neighborhood ktext pages on specified mask */
  350. else if (cpulist_parse(str, &ktext_mask) == 0) {
  351. char buf[NR_CPUS * 5];
  352. cpulist_scnprintf(buf, sizeof(buf), &ktext_mask);
  353. if (cpumask_weight(&ktext_mask) > 1) {
  354. ktext_small = 1;
  355. pr_info("ktext: using caching neighborhood %s "
  356. "with small pages\n", buf);
  357. } else {
  358. pr_info("ktext: caching on cpu %s with one huge page\n",
  359. buf);
  360. }
  361. }
  362. else if (*str)
  363. return -EINVAL;
  364. return 0;
  365. }
  366. early_param("ktext", setup_ktext);
  367. static inline pgprot_t ktext_set_nocache(pgprot_t prot)
  368. {
  369. if (!ktext_nocache)
  370. prot = hv_pte_set_nc(prot);
  371. #if CHIP_HAS_NC_AND_NOALLOC_BITS()
  372. else
  373. prot = hv_pte_set_no_alloc_l2(prot);
  374. #endif
  375. return prot;
  376. }
  377. #ifndef __tilegx__
  378. static pmd_t *__init get_pmd(pgd_t pgtables[], unsigned long va)
  379. {
  380. return pmd_offset(pud_offset(&pgtables[pgd_index(va)], va), va);
  381. }
  382. #else
  383. static pmd_t *__init get_pmd(pgd_t pgtables[], unsigned long va)
  384. {
  385. pud_t *pud = pud_offset(&pgtables[pgd_index(va)], va);
  386. if (pud_none(*pud))
  387. assign_pmd(pud, alloc_pmd());
  388. return pmd_offset(pud, va);
  389. }
  390. #endif
  391. /* Temporary page table we use for staging. */
  392. static pgd_t pgtables[PTRS_PER_PGD]
  393. __attribute__((aligned(HV_PAGE_TABLE_ALIGN)));
  394. /*
  395. * This maps the physical memory to kernel virtual address space, a total
  396. * of max_low_pfn pages, by creating page tables starting from address
  397. * PAGE_OFFSET.
  398. *
  399. * This routine transitions us from using a set of compiled-in large
  400. * pages to using some more precise caching, including removing access
  401. * to code pages mapped at PAGE_OFFSET (executed only at MEM_SV_START)
  402. * marking read-only data as locally cacheable, striping the remaining
  403. * .data and .bss across all the available tiles, and removing access
  404. * to pages above the top of RAM (thus ensuring a page fault from a bad
  405. * virtual address rather than a hypervisor shoot down for accessing
  406. * memory outside the assigned limits).
  407. */
  408. static void __init kernel_physical_mapping_init(pgd_t *pgd_base)
  409. {
  410. unsigned long address, pfn;
  411. pmd_t *pmd;
  412. pte_t *pte;
  413. int pte_ofs;
  414. const struct cpumask *my_cpu_mask = cpumask_of(smp_processor_id());
  415. struct cpumask kstripe_mask;
  416. int rc, i;
  417. #if CHIP_HAS_CBOX_HOME_MAP()
  418. if (ktext_arg_seen && ktext_hash) {
  419. pr_warning("warning: \"ktext\" boot argument ignored"
  420. " if \"kcache_hash\" sets up text hash-for-home\n");
  421. ktext_small = 0;
  422. }
  423. if (kdata_arg_seen && kdata_hash) {
  424. pr_warning("warning: \"kdata\" boot argument ignored"
  425. " if \"kcache_hash\" sets up data hash-for-home\n");
  426. }
  427. if (kdata_huge && !hash_default) {
  428. pr_warning("warning: disabling \"kdata=huge\"; requires"
  429. " kcache_hash=all or =allbutstack\n");
  430. kdata_huge = 0;
  431. }
  432. #endif
  433. /*
  434. * Set up a mask for cpus to use for kernel striping.
  435. * This is normally all cpus, but minus dataplane cpus if any.
  436. * If the dataplane covers the whole chip, we stripe over
  437. * the whole chip too.
  438. */
  439. cpumask_copy(&kstripe_mask, cpu_possible_mask);
  440. if (!kdata_arg_seen)
  441. kdata_mask = kstripe_mask;
  442. /* Allocate and fill in L2 page tables */
  443. for (i = 0; i < MAX_NUMNODES; ++i) {
  444. #ifdef CONFIG_HIGHMEM
  445. unsigned long end_pfn = node_lowmem_end_pfn[i];
  446. #else
  447. unsigned long end_pfn = node_end_pfn[i];
  448. #endif
  449. unsigned long end_huge_pfn = 0;
  450. /* Pre-shatter the last huge page to allow per-cpu pages. */
  451. if (kdata_huge)
  452. end_huge_pfn = end_pfn - (HPAGE_SIZE >> PAGE_SHIFT);
  453. pfn = node_start_pfn[i];
  454. /* Allocate enough memory to hold L2 page tables for node. */
  455. init_prealloc_ptes(i, end_pfn - pfn);
  456. address = (unsigned long) pfn_to_kaddr(pfn);
  457. while (pfn < end_pfn) {
  458. BUG_ON(address & (HPAGE_SIZE-1));
  459. pmd = get_pmd(pgtables, address);
  460. pte = get_prealloc_pte(pfn);
  461. if (pfn < end_huge_pfn) {
  462. pgprot_t prot = init_pgprot(address);
  463. *(pte_t *)pmd = pte_mkhuge(pfn_pte(pfn, prot));
  464. for (pte_ofs = 0; pte_ofs < PTRS_PER_PTE;
  465. pfn++, pte_ofs++, address += PAGE_SIZE)
  466. pte[pte_ofs] = pfn_pte(pfn, prot);
  467. } else {
  468. if (kdata_huge)
  469. printk(KERN_DEBUG "pre-shattered huge"
  470. " page at %#lx\n", address);
  471. for (pte_ofs = 0; pte_ofs < PTRS_PER_PTE;
  472. pfn++, pte_ofs++, address += PAGE_SIZE) {
  473. pgprot_t prot = init_pgprot(address);
  474. pte[pte_ofs] = pfn_pte(pfn, prot);
  475. }
  476. assign_pte(pmd, pte);
  477. }
  478. }
  479. }
  480. /*
  481. * Set or check ktext_map now that we have cpu_possible_mask
  482. * and kstripe_mask to work with.
  483. */
  484. if (ktext_all)
  485. cpumask_copy(&ktext_mask, cpu_possible_mask);
  486. else if (ktext_nondataplane)
  487. ktext_mask = kstripe_mask;
  488. else if (!cpumask_empty(&ktext_mask)) {
  489. /* Sanity-check any mask that was requested */
  490. struct cpumask bad;
  491. cpumask_andnot(&bad, &ktext_mask, cpu_possible_mask);
  492. cpumask_and(&ktext_mask, &ktext_mask, cpu_possible_mask);
  493. if (!cpumask_empty(&bad)) {
  494. char buf[NR_CPUS * 5];
  495. cpulist_scnprintf(buf, sizeof(buf), &bad);
  496. pr_info("ktext: not using unavailable cpus %s\n", buf);
  497. }
  498. if (cpumask_empty(&ktext_mask)) {
  499. pr_warning("ktext: no valid cpus; caching on %d.\n",
  500. smp_processor_id());
  501. cpumask_copy(&ktext_mask,
  502. cpumask_of(smp_processor_id()));
  503. }
  504. }
  505. address = MEM_SV_INTRPT;
  506. pmd = get_pmd(pgtables, address);
  507. if (ktext_small) {
  508. /* Allocate an L2 PTE for the kernel text */
  509. int cpu = 0;
  510. pgprot_t prot = construct_pgprot(PAGE_KERNEL_EXEC,
  511. PAGE_HOME_IMMUTABLE);
  512. if (ktext_local) {
  513. if (ktext_nocache)
  514. prot = hv_pte_set_mode(prot,
  515. HV_PTE_MODE_UNCACHED);
  516. else
  517. prot = hv_pte_set_mode(prot,
  518. HV_PTE_MODE_CACHE_NO_L3);
  519. } else {
  520. prot = hv_pte_set_mode(prot,
  521. HV_PTE_MODE_CACHE_TILE_L3);
  522. cpu = cpumask_first(&ktext_mask);
  523. prot = ktext_set_nocache(prot);
  524. }
  525. BUG_ON(address != (unsigned long)_stext);
  526. pfn = 0; /* code starts at PA 0 */
  527. pte = alloc_pte();
  528. for (pte_ofs = 0; address < (unsigned long)_einittext;
  529. pfn++, pte_ofs++, address += PAGE_SIZE) {
  530. if (!ktext_local) {
  531. prot = set_remote_cache_cpu(prot, cpu);
  532. cpu = cpumask_next(cpu, &ktext_mask);
  533. if (cpu == NR_CPUS)
  534. cpu = cpumask_first(&ktext_mask);
  535. }
  536. pte[pte_ofs] = pfn_pte(pfn, prot);
  537. }
  538. assign_pte(pmd, pte);
  539. } else {
  540. pte_t pteval = pfn_pte(0, PAGE_KERNEL_EXEC);
  541. pteval = pte_mkhuge(pteval);
  542. #if CHIP_HAS_CBOX_HOME_MAP()
  543. if (ktext_hash) {
  544. pteval = hv_pte_set_mode(pteval,
  545. HV_PTE_MODE_CACHE_HASH_L3);
  546. pteval = ktext_set_nocache(pteval);
  547. } else
  548. #endif /* CHIP_HAS_CBOX_HOME_MAP() */
  549. if (cpumask_weight(&ktext_mask) == 1) {
  550. pteval = set_remote_cache_cpu(pteval,
  551. cpumask_first(&ktext_mask));
  552. pteval = hv_pte_set_mode(pteval,
  553. HV_PTE_MODE_CACHE_TILE_L3);
  554. pteval = ktext_set_nocache(pteval);
  555. } else if (ktext_nocache)
  556. pteval = hv_pte_set_mode(pteval,
  557. HV_PTE_MODE_UNCACHED);
  558. else
  559. pteval = hv_pte_set_mode(pteval,
  560. HV_PTE_MODE_CACHE_NO_L3);
  561. *(pte_t *)pmd = pteval;
  562. }
  563. /* Set swapper_pgprot here so it is flushed to memory right away. */
  564. swapper_pgprot = init_pgprot((unsigned long)swapper_pg_dir);
  565. /*
  566. * Since we may be changing the caching of the stack and page
  567. * table itself, we invoke an assembly helper to do the
  568. * following steps:
  569. *
  570. * - flush the cache so we start with an empty slate
  571. * - install pgtables[] as the real page table
  572. * - flush the TLB so the new page table takes effect
  573. */
  574. rc = flush_and_install_context(__pa(pgtables),
  575. init_pgprot((unsigned long)pgtables),
  576. __get_cpu_var(current_asid),
  577. cpumask_bits(my_cpu_mask));
  578. BUG_ON(rc != 0);
  579. /* Copy the page table back to the normal swapper_pg_dir. */
  580. memcpy(pgd_base, pgtables, sizeof(pgtables));
  581. __install_page_table(pgd_base, __get_cpu_var(current_asid),
  582. swapper_pgprot);
  583. /*
  584. * We just read swapper_pgprot and thus brought it into the cache,
  585. * with its new home & caching mode. When we start the other CPUs,
  586. * they're going to reference swapper_pgprot via their initial fake
  587. * VA-is-PA mappings, which cache everything locally. At that
  588. * time, if it's in our cache with a conflicting home, the
  589. * simulator's coherence checker will complain. So, flush it out
  590. * of our cache; we're not going to ever use it again anyway.
  591. */
  592. __insn_finv(&swapper_pgprot);
  593. }
  594. /*
  595. * devmem_is_allowed() checks to see if /dev/mem access to a certain address
  596. * is valid. The argument is a physical page number.
  597. *
  598. * On Tile, the only valid things for which we can just hand out unchecked
  599. * PTEs are the kernel code and data. Anything else might change its
  600. * homing with time, and we wouldn't know to adjust the /dev/mem PTEs.
  601. * Note that init_thread_union is released to heap soon after boot,
  602. * so we include it in the init data.
  603. *
  604. * For TILE-Gx, we might want to consider allowing access to PA
  605. * regions corresponding to PCI space, etc.
  606. */
  607. int devmem_is_allowed(unsigned long pagenr)
  608. {
  609. return pagenr < kaddr_to_pfn(_end) &&
  610. !(pagenr >= kaddr_to_pfn(&init_thread_union) ||
  611. pagenr < kaddr_to_pfn(_einitdata)) &&
  612. !(pagenr >= kaddr_to_pfn(_sinittext) ||
  613. pagenr <= kaddr_to_pfn(_einittext-1));
  614. }
  615. #ifdef CONFIG_HIGHMEM
  616. static void __init permanent_kmaps_init(pgd_t *pgd_base)
  617. {
  618. pgd_t *pgd;
  619. pud_t *pud;
  620. pmd_t *pmd;
  621. pte_t *pte;
  622. unsigned long vaddr;
  623. vaddr = PKMAP_BASE;
  624. page_table_range_init(vaddr, vaddr + PAGE_SIZE*LAST_PKMAP, pgd_base);
  625. pgd = swapper_pg_dir + pgd_index(vaddr);
  626. pud = pud_offset(pgd, vaddr);
  627. pmd = pmd_offset(pud, vaddr);
  628. pte = pte_offset_kernel(pmd, vaddr);
  629. pkmap_page_table = pte;
  630. }
  631. #endif /* CONFIG_HIGHMEM */
  632. static void __init init_free_pfn_range(unsigned long start, unsigned long end)
  633. {
  634. unsigned long pfn;
  635. struct page *page = pfn_to_page(start);
  636. for (pfn = start; pfn < end; ) {
  637. /* Optimize by freeing pages in large batches */
  638. int order = __ffs(pfn);
  639. int count, i;
  640. struct page *p;
  641. if (order >= MAX_ORDER)
  642. order = MAX_ORDER-1;
  643. count = 1 << order;
  644. while (pfn + count > end) {
  645. count >>= 1;
  646. --order;
  647. }
  648. for (p = page, i = 0; i < count; ++i, ++p) {
  649. __ClearPageReserved(p);
  650. /*
  651. * Hacky direct set to avoid unnecessary
  652. * lock take/release for EVERY page here.
  653. */
  654. p->_count.counter = 0;
  655. p->_mapcount.counter = -1;
  656. }
  657. init_page_count(page);
  658. __free_pages(page, order);
  659. totalram_pages += count;
  660. page += count;
  661. pfn += count;
  662. }
  663. }
  664. static void __init set_non_bootmem_pages_init(void)
  665. {
  666. struct zone *z;
  667. for_each_zone(z) {
  668. unsigned long start, end;
  669. int nid = z->zone_pgdat->node_id;
  670. int idx = zone_idx(z);
  671. start = z->zone_start_pfn;
  672. if (start == 0)
  673. continue; /* bootmem */
  674. end = start + z->spanned_pages;
  675. if (idx == ZONE_NORMAL) {
  676. BUG_ON(start != node_start_pfn[nid]);
  677. start = node_free_pfn[nid];
  678. }
  679. #ifdef CONFIG_HIGHMEM
  680. if (idx == ZONE_HIGHMEM)
  681. totalhigh_pages += z->spanned_pages;
  682. #endif
  683. if (kdata_huge) {
  684. unsigned long percpu_pfn = node_percpu_pfn[nid];
  685. if (start < percpu_pfn && end > percpu_pfn)
  686. end = percpu_pfn;
  687. }
  688. #ifdef CONFIG_PCI
  689. if (start <= pci_reserve_start_pfn &&
  690. end > pci_reserve_start_pfn) {
  691. if (end > pci_reserve_end_pfn)
  692. init_free_pfn_range(pci_reserve_end_pfn, end);
  693. end = pci_reserve_start_pfn;
  694. }
  695. #endif
  696. init_free_pfn_range(start, end);
  697. }
  698. }
  699. /*
  700. * paging_init() sets up the page tables - note that all of lowmem is
  701. * already mapped by head.S.
  702. */
  703. void __init paging_init(void)
  704. {
  705. #ifdef CONFIG_HIGHMEM
  706. unsigned long vaddr, end;
  707. #endif
  708. #ifdef __tilegx__
  709. pud_t *pud;
  710. #endif
  711. pgd_t *pgd_base = swapper_pg_dir;
  712. kernel_physical_mapping_init(pgd_base);
  713. #ifdef CONFIG_HIGHMEM
  714. /*
  715. * Fixed mappings, only the page table structure has to be
  716. * created - mappings will be set by set_fixmap():
  717. */
  718. vaddr = __fix_to_virt(__end_of_fixed_addresses - 1) & PMD_MASK;
  719. end = (FIXADDR_TOP + PMD_SIZE - 1) & PMD_MASK;
  720. page_table_range_init(vaddr, end, pgd_base);
  721. permanent_kmaps_init(pgd_base);
  722. #endif
  723. #ifdef __tilegx__
  724. /*
  725. * Since GX allocates just one pmd_t array worth of vmalloc space,
  726. * we go ahead and allocate it statically here, then share it
  727. * globally. As a result we don't have to worry about any task
  728. * changing init_mm once we get up and running, and there's no
  729. * need for e.g. vmalloc_sync_all().
  730. */
  731. BUILD_BUG_ON(pgd_index(VMALLOC_START) != pgd_index(VMALLOC_END));
  732. pud = pud_offset(pgd_base + pgd_index(VMALLOC_START), VMALLOC_START);
  733. assign_pmd(pud, alloc_pmd());
  734. #endif
  735. }
  736. /*
  737. * Walk the kernel page tables and derive the page_home() from
  738. * the PTEs, so that set_pte() can properly validate the caching
  739. * of all PTEs it sees.
  740. */
  741. void __init set_page_homes(void)
  742. {
  743. }
  744. static void __init set_max_mapnr_init(void)
  745. {
  746. #ifdef CONFIG_FLATMEM
  747. max_mapnr = max_low_pfn;
  748. #endif
  749. }
  750. void __init mem_init(void)
  751. {
  752. int codesize, datasize, initsize;
  753. int i;
  754. #ifndef __tilegx__
  755. void *last;
  756. #endif
  757. #ifdef CONFIG_FLATMEM
  758. if (!mem_map)
  759. BUG();
  760. #endif
  761. #ifdef CONFIG_HIGHMEM
  762. /* check that fixmap and pkmap do not overlap */
  763. if (PKMAP_ADDR(LAST_PKMAP-1) >= FIXADDR_START) {
  764. pr_err("fixmap and kmap areas overlap"
  765. " - this will crash\n");
  766. pr_err("pkstart: %lxh pkend: %lxh fixstart %lxh\n",
  767. PKMAP_BASE, PKMAP_ADDR(LAST_PKMAP-1),
  768. FIXADDR_START);
  769. BUG();
  770. }
  771. #endif
  772. set_max_mapnr_init();
  773. /* this will put all bootmem onto the freelists */
  774. totalram_pages += free_all_bootmem();
  775. /* count all remaining LOWMEM and give all HIGHMEM to page allocator */
  776. set_non_bootmem_pages_init();
  777. codesize = (unsigned long)&_etext - (unsigned long)&_text;
  778. datasize = (unsigned long)&_end - (unsigned long)&_sdata;
  779. initsize = (unsigned long)&_einittext - (unsigned long)&_sinittext;
  780. initsize += (unsigned long)&_einitdata - (unsigned long)&_sinitdata;
  781. pr_info("Memory: %luk/%luk available (%dk kernel code, %dk data, %dk init, %ldk highmem)\n",
  782. (unsigned long) nr_free_pages() << (PAGE_SHIFT-10),
  783. num_physpages << (PAGE_SHIFT-10),
  784. codesize >> 10,
  785. datasize >> 10,
  786. initsize >> 10,
  787. (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10))
  788. );
  789. /*
  790. * In debug mode, dump some interesting memory mappings.
  791. */
  792. #ifdef CONFIG_HIGHMEM
  793. printk(KERN_DEBUG " KMAP %#lx - %#lx\n",
  794. FIXADDR_START, FIXADDR_TOP + PAGE_SIZE - 1);
  795. printk(KERN_DEBUG " PKMAP %#lx - %#lx\n",
  796. PKMAP_BASE, PKMAP_ADDR(LAST_PKMAP) - 1);
  797. #endif
  798. #ifdef CONFIG_HUGEVMAP
  799. printk(KERN_DEBUG " HUGEMAP %#lx - %#lx\n",
  800. HUGE_VMAP_BASE, HUGE_VMAP_END - 1);
  801. #endif
  802. printk(KERN_DEBUG " VMALLOC %#lx - %#lx\n",
  803. _VMALLOC_START, _VMALLOC_END - 1);
  804. #ifdef __tilegx__
  805. for (i = MAX_NUMNODES-1; i >= 0; --i) {
  806. struct pglist_data *node = &node_data[i];
  807. if (node->node_present_pages) {
  808. unsigned long start = (unsigned long)
  809. pfn_to_kaddr(node->node_start_pfn);
  810. unsigned long end = start +
  811. (node->node_present_pages << PAGE_SHIFT);
  812. printk(KERN_DEBUG " MEM%d %#lx - %#lx\n",
  813. i, start, end - 1);
  814. }
  815. }
  816. #else
  817. last = high_memory;
  818. for (i = MAX_NUMNODES-1; i >= 0; --i) {
  819. if ((unsigned long)vbase_map[i] != -1UL) {
  820. printk(KERN_DEBUG " LOWMEM%d %#lx - %#lx\n",
  821. i, (unsigned long) (vbase_map[i]),
  822. (unsigned long) (last-1));
  823. last = vbase_map[i];
  824. }
  825. }
  826. #endif
  827. #ifndef __tilegx__
  828. /*
  829. * Convert from using one lock for all atomic operations to
  830. * one per cpu.
  831. */
  832. __init_atomic_per_cpu();
  833. #endif
  834. }
  835. /*
  836. * this is for the non-NUMA, single node SMP system case.
  837. * Specifically, in the case of x86, we will always add
  838. * memory to the highmem for now.
  839. */
  840. #ifndef CONFIG_NEED_MULTIPLE_NODES
  841. int arch_add_memory(u64 start, u64 size)
  842. {
  843. struct pglist_data *pgdata = &contig_page_data;
  844. struct zone *zone = pgdata->node_zones + MAX_NR_ZONES-1;
  845. unsigned long start_pfn = start >> PAGE_SHIFT;
  846. unsigned long nr_pages = size >> PAGE_SHIFT;
  847. return __add_pages(zone, start_pfn, nr_pages);
  848. }
  849. int remove_memory(u64 start, u64 size)
  850. {
  851. return -EINVAL;
  852. }
  853. #endif
  854. struct kmem_cache *pgd_cache;
  855. void __init pgtable_cache_init(void)
  856. {
  857. pgd_cache = kmem_cache_create("pgd",
  858. PTRS_PER_PGD*sizeof(pgd_t),
  859. PTRS_PER_PGD*sizeof(pgd_t),
  860. 0,
  861. NULL);
  862. if (!pgd_cache)
  863. panic("pgtable_cache_init(): Cannot create pgd cache");
  864. }
  865. #if !CHIP_HAS_COHERENT_LOCAL_CACHE()
  866. /*
  867. * The __w1data area holds data that is only written during initialization,
  868. * and is read-only and thus freely cacheable thereafter. Fix the page
  869. * table entries that cover that region accordingly.
  870. */
  871. static void mark_w1data_ro(void)
  872. {
  873. /* Loop over page table entries */
  874. unsigned long addr = (unsigned long)__w1data_begin;
  875. BUG_ON((addr & (PAGE_SIZE-1)) != 0);
  876. for (; addr <= (unsigned long)__w1data_end - 1; addr += PAGE_SIZE) {
  877. unsigned long pfn = kaddr_to_pfn((void *)addr);
  878. pte_t *ptep = virt_to_pte(NULL, addr);
  879. BUG_ON(pte_huge(*ptep)); /* not relevant for kdata_huge */
  880. set_pte_at(&init_mm, addr, ptep, pfn_pte(pfn, PAGE_KERNEL_RO));
  881. }
  882. }
  883. #endif
  884. #ifdef CONFIG_DEBUG_PAGEALLOC
  885. static long __write_once initfree;
  886. #else
  887. static long __write_once initfree = 1;
  888. #endif
  889. /* Select whether to free (1) or mark unusable (0) the __init pages. */
  890. static int __init set_initfree(char *str)
  891. {
  892. long val;
  893. if (strict_strtol(str, 0, &val) == 0) {
  894. initfree = val;
  895. pr_info("initfree: %s free init pages\n",
  896. initfree ? "will" : "won't");
  897. }
  898. return 1;
  899. }
  900. __setup("initfree=", set_initfree);
  901. static void free_init_pages(char *what, unsigned long begin, unsigned long end)
  902. {
  903. unsigned long addr = (unsigned long) begin;
  904. if (kdata_huge && !initfree) {
  905. pr_warning("Warning: ignoring initfree=0:"
  906. " incompatible with kdata=huge\n");
  907. initfree = 1;
  908. }
  909. end = (end + PAGE_SIZE - 1) & PAGE_MASK;
  910. local_flush_tlb_pages(NULL, begin, PAGE_SIZE, end - begin);
  911. for (addr = begin; addr < end; addr += PAGE_SIZE) {
  912. /*
  913. * Note we just reset the home here directly in the
  914. * page table. We know this is safe because our caller
  915. * just flushed the caches on all the other cpus,
  916. * and they won't be touching any of these pages.
  917. */
  918. int pfn = kaddr_to_pfn((void *)addr);
  919. struct page *page = pfn_to_page(pfn);
  920. pte_t *ptep = virt_to_pte(NULL, addr);
  921. if (!initfree) {
  922. /*
  923. * If debugging page accesses then do not free
  924. * this memory but mark them not present - any
  925. * buggy init-section access will create a
  926. * kernel page fault:
  927. */
  928. pte_clear(&init_mm, addr, ptep);
  929. continue;
  930. }
  931. __ClearPageReserved(page);
  932. init_page_count(page);
  933. if (pte_huge(*ptep))
  934. BUG_ON(!kdata_huge);
  935. else
  936. set_pte_at(&init_mm, addr, ptep,
  937. pfn_pte(pfn, PAGE_KERNEL));
  938. memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
  939. free_page(addr);
  940. totalram_pages++;
  941. }
  942. pr_info("Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
  943. }
  944. void free_initmem(void)
  945. {
  946. const unsigned long text_delta = MEM_SV_INTRPT - PAGE_OFFSET;
  947. /*
  948. * Evict the dirty initdata on the boot cpu, evict the w1data
  949. * wherever it's homed, and evict all the init code everywhere.
  950. * We are guaranteed that no one will touch the init pages any
  951. * more, and although other cpus may be touching the w1data,
  952. * we only actually change the caching on tile64, which won't
  953. * be keeping local copies in the other tiles' caches anyway.
  954. */
  955. homecache_evict(&cpu_cacheable_map);
  956. /* Free the data pages that we won't use again after init. */
  957. free_init_pages("unused kernel data",
  958. (unsigned long)_sinitdata,
  959. (unsigned long)_einitdata);
  960. /*
  961. * Free the pages mapped from 0xc0000000 that correspond to code
  962. * pages from MEM_SV_INTRPT that we won't use again after init.
  963. */
  964. free_init_pages("unused kernel text",
  965. (unsigned long)_sinittext - text_delta,
  966. (unsigned long)_einittext - text_delta);
  967. #if !CHIP_HAS_COHERENT_LOCAL_CACHE()
  968. /*
  969. * Upgrade the .w1data section to globally cached.
  970. * We don't do this on tilepro, since the cache architecture
  971. * pretty much makes it irrelevant, and in any case we end
  972. * up having racing issues with other tiles that may touch
  973. * the data after we flush the cache but before we update
  974. * the PTEs and flush the TLBs, causing sharer shootdowns
  975. * later. Even though this is to clean data, it seems like
  976. * an unnecessary complication.
  977. */
  978. mark_w1data_ro();
  979. #endif
  980. /* Do a global TLB flush so everyone sees the changes. */
  981. flush_tlb_all();
  982. }