omap2430.c 8.5 KB

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  1. /*
  2. * Copyright (C) 2005-2007 by Texas Instruments
  3. * Some code has been taken from tusb6010.c
  4. * Copyrights for that are attributable to:
  5. * Copyright (C) 2006 Nokia Corporation
  6. * Tony Lindgren <tony@atomide.com>
  7. *
  8. * This file is part of the Inventra Controller Driver for Linux.
  9. *
  10. * The Inventra Controller Driver for Linux is free software; you
  11. * can redistribute it and/or modify it under the terms of the GNU
  12. * General Public License version 2 as published by the Free Software
  13. * Foundation.
  14. *
  15. * The Inventra Controller Driver for Linux is distributed in
  16. * the hope that it will be useful, but WITHOUT ANY WARRANTY;
  17. * without even the implied warranty of MERCHANTABILITY or
  18. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  19. * License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with The Inventra Controller Driver for Linux ; if not,
  23. * write to the Free Software Foundation, Inc., 59 Temple Place,
  24. * Suite 330, Boston, MA 02111-1307 USA
  25. *
  26. */
  27. #include <linux/module.h>
  28. #include <linux/kernel.h>
  29. #include <linux/sched.h>
  30. #include <linux/init.h>
  31. #include <linux/list.h>
  32. #include <linux/clk.h>
  33. #include <linux/io.h>
  34. #include <asm/mach-types.h>
  35. #include <mach/hardware.h>
  36. #include <plat/mux.h>
  37. #include "musb_core.h"
  38. #include "omap2430.h"
  39. static struct timer_list musb_idle_timer;
  40. static void musb_do_idle(unsigned long _musb)
  41. {
  42. struct musb *musb = (void *)_musb;
  43. unsigned long flags;
  44. #ifdef CONFIG_USB_MUSB_HDRC_HCD
  45. u8 power;
  46. #endif
  47. u8 devctl;
  48. spin_lock_irqsave(&musb->lock, flags);
  49. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  50. switch (musb->xceiv->state) {
  51. case OTG_STATE_A_WAIT_BCON:
  52. devctl &= ~MUSB_DEVCTL_SESSION;
  53. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  54. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  55. if (devctl & MUSB_DEVCTL_BDEVICE) {
  56. musb->xceiv->state = OTG_STATE_B_IDLE;
  57. MUSB_DEV_MODE(musb);
  58. } else {
  59. musb->xceiv->state = OTG_STATE_A_IDLE;
  60. MUSB_HST_MODE(musb);
  61. }
  62. break;
  63. #ifdef CONFIG_USB_MUSB_HDRC_HCD
  64. case OTG_STATE_A_SUSPEND:
  65. /* finish RESUME signaling? */
  66. if (musb->port1_status & MUSB_PORT_STAT_RESUME) {
  67. power = musb_readb(musb->mregs, MUSB_POWER);
  68. power &= ~MUSB_POWER_RESUME;
  69. DBG(1, "root port resume stopped, power %02x\n", power);
  70. musb_writeb(musb->mregs, MUSB_POWER, power);
  71. musb->is_active = 1;
  72. musb->port1_status &= ~(USB_PORT_STAT_SUSPEND
  73. | MUSB_PORT_STAT_RESUME);
  74. musb->port1_status |= USB_PORT_STAT_C_SUSPEND << 16;
  75. usb_hcd_poll_rh_status(musb_to_hcd(musb));
  76. /* NOTE: it might really be A_WAIT_BCON ... */
  77. musb->xceiv->state = OTG_STATE_A_HOST;
  78. }
  79. break;
  80. #endif
  81. #ifdef CONFIG_USB_MUSB_HDRC_HCD
  82. case OTG_STATE_A_HOST:
  83. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  84. if (devctl & MUSB_DEVCTL_BDEVICE)
  85. musb->xceiv->state = OTG_STATE_B_IDLE;
  86. else
  87. musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
  88. #endif
  89. default:
  90. break;
  91. }
  92. spin_unlock_irqrestore(&musb->lock, flags);
  93. }
  94. void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
  95. {
  96. unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
  97. static unsigned long last_timer;
  98. if (timeout == 0)
  99. timeout = default_timeout;
  100. /* Never idle if active, or when VBUS timeout is not set as host */
  101. if (musb->is_active || ((musb->a_wait_bcon == 0)
  102. && (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
  103. DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
  104. del_timer(&musb_idle_timer);
  105. last_timer = jiffies;
  106. return;
  107. }
  108. if (time_after(last_timer, timeout)) {
  109. if (!timer_pending(&musb_idle_timer))
  110. last_timer = timeout;
  111. else {
  112. DBG(4, "Longer idle timer already pending, ignoring\n");
  113. return;
  114. }
  115. }
  116. last_timer = timeout;
  117. DBG(4, "%s inactive, for idle timer for %lu ms\n",
  118. otg_state_string(musb),
  119. (unsigned long)jiffies_to_msecs(timeout - jiffies));
  120. mod_timer(&musb_idle_timer, timeout);
  121. }
  122. void musb_platform_enable(struct musb *musb)
  123. {
  124. }
  125. void musb_platform_disable(struct musb *musb)
  126. {
  127. }
  128. static void omap_set_vbus(struct musb *musb, int is_on)
  129. {
  130. u8 devctl;
  131. /* HDRC controls CPEN, but beware current surges during device
  132. * connect. They can trigger transient overcurrent conditions
  133. * that must be ignored.
  134. */
  135. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  136. if (is_on) {
  137. musb->is_active = 1;
  138. musb->xceiv->default_a = 1;
  139. musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
  140. devctl |= MUSB_DEVCTL_SESSION;
  141. MUSB_HST_MODE(musb);
  142. } else {
  143. musb->is_active = 0;
  144. /* NOTE: we're skipping A_WAIT_VFALL -> A_IDLE and
  145. * jumping right to B_IDLE...
  146. */
  147. musb->xceiv->default_a = 0;
  148. musb->xceiv->state = OTG_STATE_B_IDLE;
  149. devctl &= ~MUSB_DEVCTL_SESSION;
  150. MUSB_DEV_MODE(musb);
  151. }
  152. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  153. DBG(1, "VBUS %s, devctl %02x "
  154. /* otg %3x conf %08x prcm %08x */ "\n",
  155. otg_state_string(musb),
  156. musb_readb(musb->mregs, MUSB_DEVCTL));
  157. }
  158. static int musb_platform_resume(struct musb *musb);
  159. int musb_platform_set_mode(struct musb *musb, u8 musb_mode)
  160. {
  161. u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  162. devctl |= MUSB_DEVCTL_SESSION;
  163. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  164. return 0;
  165. }
  166. int __init musb_platform_init(struct musb *musb, void *board_data)
  167. {
  168. u32 l;
  169. struct omap_musb_board_data *data = board_data;
  170. #if defined(CONFIG_ARCH_OMAP2430)
  171. omap_cfg_reg(AE5_2430_USB0HS_STP);
  172. #endif
  173. /* We require some kind of external transceiver, hooked
  174. * up through ULPI. TWL4030-family PMICs include one,
  175. * which needs a driver, drivers aren't always needed.
  176. */
  177. musb->xceiv = otg_get_transceiver();
  178. if (!musb->xceiv) {
  179. pr_err("HS USB OTG: no transceiver configured\n");
  180. return -ENODEV;
  181. }
  182. musb_platform_resume(musb);
  183. l = musb_readl(musb->mregs, OTG_SYSCONFIG);
  184. l &= ~ENABLEWAKEUP; /* disable wakeup */
  185. l &= ~NOSTDBY; /* remove possible nostdby */
  186. l |= SMARTSTDBY; /* enable smart standby */
  187. l &= ~AUTOIDLE; /* disable auto idle */
  188. l &= ~NOIDLE; /* remove possible noidle */
  189. l |= SMARTIDLE; /* enable smart idle */
  190. /*
  191. * MUSB AUTOIDLE don't work in 3430.
  192. * Workaround by Richard Woodruff/TI
  193. */
  194. if (!cpu_is_omap3430())
  195. l |= AUTOIDLE; /* enable auto idle */
  196. musb_writel(musb->mregs, OTG_SYSCONFIG, l);
  197. l = musb_readl(musb->mregs, OTG_INTERFSEL);
  198. if (data->interface_type == MUSB_INTERFACE_UTMI) {
  199. /* OMAP4 uses Internal PHY GS70 which uses UTMI interface */
  200. l &= ~ULPI_12PIN; /* Disable ULPI */
  201. l |= UTMI_8BIT; /* Enable UTMI */
  202. } else {
  203. l |= ULPI_12PIN;
  204. }
  205. musb_writel(musb->mregs, OTG_INTERFSEL, l);
  206. pr_debug("HS USB OTG: revision 0x%x, sysconfig 0x%02x, "
  207. "sysstatus 0x%x, intrfsel 0x%x, simenable 0x%x\n",
  208. musb_readl(musb->mregs, OTG_REVISION),
  209. musb_readl(musb->mregs, OTG_SYSCONFIG),
  210. musb_readl(musb->mregs, OTG_SYSSTATUS),
  211. musb_readl(musb->mregs, OTG_INTERFSEL),
  212. musb_readl(musb->mregs, OTG_SIMENABLE));
  213. if (is_host_enabled(musb))
  214. musb->board_set_vbus = omap_set_vbus;
  215. setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
  216. return 0;
  217. }
  218. #ifdef CONFIG_PM
  219. void musb_platform_save_context(struct musb *musb,
  220. struct musb_context_registers *musb_context)
  221. {
  222. musb_context->otg_sysconfig = musb_readl(musb->mregs, OTG_SYSCONFIG);
  223. musb_context->otg_forcestandby = musb_readl(musb->mregs, OTG_FORCESTDBY);
  224. }
  225. void musb_platform_restore_context(struct musb *musb,
  226. struct musb_context_registers *musb_context)
  227. {
  228. musb_writel(musb->mregs, OTG_SYSCONFIG, musb_context->otg_sysconfig);
  229. musb_writel(musb->mregs, OTG_FORCESTDBY, musb_context->otg_forcestandby);
  230. }
  231. #endif
  232. static int musb_platform_suspend(struct musb *musb)
  233. {
  234. u32 l;
  235. if (!musb->clock)
  236. return 0;
  237. /* in any role */
  238. l = musb_readl(musb->mregs, OTG_FORCESTDBY);
  239. l |= ENABLEFORCE; /* enable MSTANDBY */
  240. musb_writel(musb->mregs, OTG_FORCESTDBY, l);
  241. l = musb_readl(musb->mregs, OTG_SYSCONFIG);
  242. l |= ENABLEWAKEUP; /* enable wakeup */
  243. musb_writel(musb->mregs, OTG_SYSCONFIG, l);
  244. otg_set_suspend(musb->xceiv, 1);
  245. if (musb->set_clock)
  246. musb->set_clock(musb->clock, 0);
  247. else
  248. clk_disable(musb->clock);
  249. return 0;
  250. }
  251. static int musb_platform_resume(struct musb *musb)
  252. {
  253. u32 l;
  254. if (!musb->clock)
  255. return 0;
  256. otg_set_suspend(musb->xceiv, 0);
  257. if (musb->set_clock)
  258. musb->set_clock(musb->clock, 1);
  259. else
  260. clk_enable(musb->clock);
  261. l = musb_readl(musb->mregs, OTG_SYSCONFIG);
  262. l &= ~ENABLEWAKEUP; /* disable wakeup */
  263. musb_writel(musb->mregs, OTG_SYSCONFIG, l);
  264. l = musb_readl(musb->mregs, OTG_FORCESTDBY);
  265. l &= ~ENABLEFORCE; /* disable MSTANDBY */
  266. musb_writel(musb->mregs, OTG_FORCESTDBY, l);
  267. return 0;
  268. }
  269. int musb_platform_exit(struct musb *musb)
  270. {
  271. musb_platform_suspend(musb);
  272. return 0;
  273. }