dev-spi.c 4.0 KB

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  1. /* linux/arch/arm/plat-s3c64xx/dev-spi.c
  2. *
  3. * Copyright (C) 2009 Samsung Electronics Ltd.
  4. * Jaswinder Singh <jassi.brar@samsung.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/string.h>
  12. #include <linux/export.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/dma-mapping.h>
  15. #include <linux/gpio.h>
  16. #include <mach/dma.h>
  17. #include <mach/map.h>
  18. #include <mach/spi-clocks.h>
  19. #include <mach/irqs.h>
  20. #include <plat/s3c64xx-spi.h>
  21. #include <plat/gpio-cfg.h>
  22. #include <plat/devs.h>
  23. static char *spi_src_clks[] = {
  24. [S3C64XX_SPI_SRCCLK_PCLK] = "pclk",
  25. [S3C64XX_SPI_SRCCLK_SPIBUS] = "spi-bus",
  26. [S3C64XX_SPI_SRCCLK_48M] = "spi_48m",
  27. };
  28. /* SPI Controller platform_devices */
  29. /* Since we emulate multi-cs capability, we do not touch the GPC-3,7.
  30. * The emulated CS is toggled by board specific mechanism, as it can
  31. * be either some immediate GPIO or some signal out of some other
  32. * chip in between ... or some yet another way.
  33. * We simply do not assume anything about CS.
  34. */
  35. static int s3c64xx_spi_cfg_gpio(struct platform_device *pdev)
  36. {
  37. unsigned int base;
  38. switch (pdev->id) {
  39. case 0:
  40. base = S3C64XX_GPC(0);
  41. break;
  42. case 1:
  43. base = S3C64XX_GPC(4);
  44. break;
  45. default:
  46. dev_err(&pdev->dev, "Invalid SPI Controller number!");
  47. return -EINVAL;
  48. }
  49. s3c_gpio_cfgall_range(base, 3,
  50. S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
  51. return 0;
  52. }
  53. static struct resource s3c64xx_spi0_resource[] = {
  54. [0] = {
  55. .start = S3C64XX_PA_SPI0,
  56. .end = S3C64XX_PA_SPI0 + 0x100 - 1,
  57. .flags = IORESOURCE_MEM,
  58. },
  59. [1] = {
  60. .start = DMACH_SPI0_TX,
  61. .end = DMACH_SPI0_TX,
  62. .flags = IORESOURCE_DMA,
  63. },
  64. [2] = {
  65. .start = DMACH_SPI0_RX,
  66. .end = DMACH_SPI0_RX,
  67. .flags = IORESOURCE_DMA,
  68. },
  69. [3] = {
  70. .start = IRQ_SPI0,
  71. .end = IRQ_SPI0,
  72. .flags = IORESOURCE_IRQ,
  73. },
  74. };
  75. static struct s3c64xx_spi_info s3c64xx_spi0_pdata = {
  76. .cfg_gpio = s3c64xx_spi_cfg_gpio,
  77. .fifo_lvl_mask = 0x7f,
  78. .rx_lvl_offset = 13,
  79. .tx_st_done = 21,
  80. };
  81. static u64 spi_dmamask = DMA_BIT_MASK(32);
  82. struct platform_device s3c64xx_device_spi0 = {
  83. .name = "s3c64xx-spi",
  84. .id = 0,
  85. .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource),
  86. .resource = s3c64xx_spi0_resource,
  87. .dev = {
  88. .dma_mask = &spi_dmamask,
  89. .coherent_dma_mask = DMA_BIT_MASK(32),
  90. .platform_data = &s3c64xx_spi0_pdata,
  91. },
  92. };
  93. EXPORT_SYMBOL(s3c64xx_device_spi0);
  94. static struct resource s3c64xx_spi1_resource[] = {
  95. [0] = {
  96. .start = S3C64XX_PA_SPI1,
  97. .end = S3C64XX_PA_SPI1 + 0x100 - 1,
  98. .flags = IORESOURCE_MEM,
  99. },
  100. [1] = {
  101. .start = DMACH_SPI1_TX,
  102. .end = DMACH_SPI1_TX,
  103. .flags = IORESOURCE_DMA,
  104. },
  105. [2] = {
  106. .start = DMACH_SPI1_RX,
  107. .end = DMACH_SPI1_RX,
  108. .flags = IORESOURCE_DMA,
  109. },
  110. [3] = {
  111. .start = IRQ_SPI1,
  112. .end = IRQ_SPI1,
  113. .flags = IORESOURCE_IRQ,
  114. },
  115. };
  116. static struct s3c64xx_spi_info s3c64xx_spi1_pdata = {
  117. .cfg_gpio = s3c64xx_spi_cfg_gpio,
  118. .fifo_lvl_mask = 0x7f,
  119. .rx_lvl_offset = 13,
  120. .tx_st_done = 21,
  121. };
  122. struct platform_device s3c64xx_device_spi1 = {
  123. .name = "s3c64xx-spi",
  124. .id = 1,
  125. .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource),
  126. .resource = s3c64xx_spi1_resource,
  127. .dev = {
  128. .dma_mask = &spi_dmamask,
  129. .coherent_dma_mask = DMA_BIT_MASK(32),
  130. .platform_data = &s3c64xx_spi1_pdata,
  131. },
  132. };
  133. EXPORT_SYMBOL(s3c64xx_device_spi1);
  134. void __init s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
  135. {
  136. struct s3c64xx_spi_info *pd;
  137. /* Reject invalid configuration */
  138. if (!num_cs || src_clk_nr < 0
  139. || src_clk_nr > S3C64XX_SPI_SRCCLK_48M) {
  140. printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
  141. return;
  142. }
  143. switch (cntrlr) {
  144. case 0:
  145. pd = &s3c64xx_spi0_pdata;
  146. break;
  147. case 1:
  148. pd = &s3c64xx_spi1_pdata;
  149. break;
  150. default:
  151. printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
  152. __func__, cntrlr);
  153. return;
  154. }
  155. pd->num_cs = num_cs;
  156. pd->src_clk_nr = src_clk_nr;
  157. pd->src_clk_name = spi_src_clks[src_clk_nr];
  158. }