at91_adc.c 30 KB

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  1. /*
  2. * Driver for the ADC present in the Atmel AT91 evaluation boards.
  3. *
  4. * Copyright 2011 Free Electrons
  5. *
  6. * Licensed under the GPLv2 or later.
  7. */
  8. #include <linux/bitmap.h>
  9. #include <linux/bitops.h>
  10. #include <linux/clk.h>
  11. #include <linux/err.h>
  12. #include <linux/io.h>
  13. #include <linux/input.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/jiffies.h>
  16. #include <linux/kernel.h>
  17. #include <linux/module.h>
  18. #include <linux/of.h>
  19. #include <linux/of_device.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/sched.h>
  22. #include <linux/slab.h>
  23. #include <linux/wait.h>
  24. #include <linux/platform_data/at91_adc.h>
  25. #include <linux/iio/iio.h>
  26. #include <linux/iio/buffer.h>
  27. #include <linux/iio/trigger.h>
  28. #include <linux/iio/trigger_consumer.h>
  29. #include <linux/iio/triggered_buffer.h>
  30. #include <mach/at91_adc.h>
  31. #define AT91_ADC_CHAN(st, ch) \
  32. (st->registers->channel_base + (ch * 4))
  33. #define at91_adc_readl(st, reg) \
  34. (readl_relaxed(st->reg_base + reg))
  35. #define at91_adc_writel(st, reg, val) \
  36. (writel_relaxed(val, st->reg_base + reg))
  37. #define DRIVER_NAME "at91_adc"
  38. #define MAX_POS_BITS 12
  39. #define TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */
  40. #define TOUCH_PEN_DETECT_DEBOUNCE_US 200
  41. struct at91_adc_caps {
  42. bool has_ts; /* Support touch screen */
  43. bool has_tsmr; /* only at91sam9x5, sama5d3 have TSMR reg */
  44. /*
  45. * Numbers of sampling data will be averaged. Can be 0~3.
  46. * Hardware can average (2 ^ ts_filter_average) sample data.
  47. */
  48. u8 ts_filter_average;
  49. /* Pen Detection input pull-up resistor, can be 0~3 */
  50. u8 ts_pen_detect_sensitivity;
  51. /* startup time calculate function */
  52. u32 (*calc_startup_ticks)(u8 startup_time, u32 adc_clk_khz);
  53. u8 num_channels;
  54. struct at91_adc_reg_desc registers;
  55. };
  56. enum atmel_adc_ts_type {
  57. ATMEL_ADC_TOUCHSCREEN_NONE = 0,
  58. ATMEL_ADC_TOUCHSCREEN_4WIRE = 4,
  59. ATMEL_ADC_TOUCHSCREEN_5WIRE = 5,
  60. };
  61. struct at91_adc_state {
  62. struct clk *adc_clk;
  63. u16 *buffer;
  64. unsigned long channels_mask;
  65. struct clk *clk;
  66. bool done;
  67. int irq;
  68. u16 last_value;
  69. struct mutex lock;
  70. u8 num_channels;
  71. void __iomem *reg_base;
  72. struct at91_adc_reg_desc *registers;
  73. u8 startup_time;
  74. u8 sample_hold_time;
  75. bool sleep_mode;
  76. struct iio_trigger **trig;
  77. struct at91_adc_trigger *trigger_list;
  78. u32 trigger_number;
  79. bool use_external;
  80. u32 vref_mv;
  81. u32 res; /* resolution used for convertions */
  82. bool low_res; /* the resolution corresponds to the lowest one */
  83. wait_queue_head_t wq_data_avail;
  84. struct at91_adc_caps *caps;
  85. /*
  86. * Following ADC channels are shared by touchscreen:
  87. *
  88. * CH0 -- Touch screen XP/UL
  89. * CH1 -- Touch screen XM/UR
  90. * CH2 -- Touch screen YP/LL
  91. * CH3 -- Touch screen YM/Sense
  92. * CH4 -- Touch screen LR(5-wire only)
  93. *
  94. * The bitfields below represents the reserved channel in the
  95. * touchscreen mode.
  96. */
  97. #define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 0)
  98. #define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 0)
  99. enum atmel_adc_ts_type touchscreen_type;
  100. struct input_dev *ts_input;
  101. u16 ts_sample_period_val;
  102. u32 ts_pressure_threshold;
  103. };
  104. static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
  105. {
  106. struct iio_poll_func *pf = p;
  107. struct iio_dev *idev = pf->indio_dev;
  108. struct at91_adc_state *st = iio_priv(idev);
  109. int i, j = 0;
  110. for (i = 0; i < idev->masklength; i++) {
  111. if (!test_bit(i, idev->active_scan_mask))
  112. continue;
  113. st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, i));
  114. j++;
  115. }
  116. iio_push_to_buffers_with_timestamp(idev, st->buffer, pf->timestamp);
  117. iio_trigger_notify_done(idev->trig);
  118. /* Needed to ACK the DRDY interruption */
  119. at91_adc_readl(st, AT91_ADC_LCDR);
  120. enable_irq(st->irq);
  121. return IRQ_HANDLED;
  122. }
  123. /* Handler for classic adc channel eoc trigger */
  124. void handle_adc_eoc_trigger(int irq, struct iio_dev *idev)
  125. {
  126. struct at91_adc_state *st = iio_priv(idev);
  127. if (iio_buffer_enabled(idev)) {
  128. disable_irq_nosync(irq);
  129. iio_trigger_poll(idev->trig, iio_get_time_ns());
  130. } else {
  131. st->last_value = at91_adc_readl(st, AT91_ADC_LCDR);
  132. st->done = true;
  133. wake_up_interruptible(&st->wq_data_avail);
  134. }
  135. }
  136. static int at91_ts_sample(struct at91_adc_state *st)
  137. {
  138. unsigned int xscale, yscale, reg, z1, z2;
  139. unsigned int x, y, pres, xpos, ypos;
  140. unsigned int rxp = 1;
  141. unsigned int factor = 1000;
  142. struct iio_dev *idev = iio_priv_to_dev(st);
  143. unsigned int xyz_mask_bits = st->res;
  144. unsigned int xyz_mask = (1 << xyz_mask_bits) - 1;
  145. /* calculate position */
  146. /* x position = (x / xscale) * max, max = 2^MAX_POS_BITS - 1 */
  147. reg = at91_adc_readl(st, AT91_ADC_TSXPOSR);
  148. xpos = reg & xyz_mask;
  149. x = (xpos << MAX_POS_BITS) - xpos;
  150. xscale = (reg >> 16) & xyz_mask;
  151. if (xscale == 0) {
  152. dev_err(&idev->dev, "Error: xscale == 0!\n");
  153. return -1;
  154. }
  155. x /= xscale;
  156. /* y position = (y / yscale) * max, max = 2^MAX_POS_BITS - 1 */
  157. reg = at91_adc_readl(st, AT91_ADC_TSYPOSR);
  158. ypos = reg & xyz_mask;
  159. y = (ypos << MAX_POS_BITS) - ypos;
  160. yscale = (reg >> 16) & xyz_mask;
  161. if (yscale == 0) {
  162. dev_err(&idev->dev, "Error: yscale == 0!\n");
  163. return -1;
  164. }
  165. y /= yscale;
  166. /* calculate the pressure */
  167. reg = at91_adc_readl(st, AT91_ADC_TSPRESSR);
  168. z1 = reg & xyz_mask;
  169. z2 = (reg >> 16) & xyz_mask;
  170. if (z1 != 0)
  171. pres = rxp * (x * factor / 1024) * (z2 * factor / z1 - factor)
  172. / factor;
  173. else
  174. pres = st->ts_pressure_threshold; /* no pen contacted */
  175. dev_dbg(&idev->dev, "xpos = %d, xscale = %d, ypos = %d, yscale = %d, z1 = %d, z2 = %d, press = %d\n",
  176. xpos, xscale, ypos, yscale, z1, z2, pres);
  177. if (pres < st->ts_pressure_threshold) {
  178. dev_dbg(&idev->dev, "x = %d, y = %d, pressure = %d\n",
  179. x, y, pres / factor);
  180. input_report_abs(st->ts_input, ABS_X, x);
  181. input_report_abs(st->ts_input, ABS_Y, y);
  182. input_report_abs(st->ts_input, ABS_PRESSURE, pres);
  183. input_report_key(st->ts_input, BTN_TOUCH, 1);
  184. input_sync(st->ts_input);
  185. } else {
  186. dev_dbg(&idev->dev, "pressure too low: not reporting\n");
  187. }
  188. return 0;
  189. }
  190. static irqreturn_t at91_adc_interrupt(int irq, void *private)
  191. {
  192. struct iio_dev *idev = private;
  193. struct at91_adc_state *st = iio_priv(idev);
  194. u32 status = at91_adc_readl(st, st->registers->status_register);
  195. const uint32_t ts_data_irq_mask =
  196. AT91_ADC_IER_XRDY |
  197. AT91_ADC_IER_YRDY |
  198. AT91_ADC_IER_PRDY;
  199. if (status & st->registers->drdy_mask)
  200. handle_adc_eoc_trigger(irq, idev);
  201. if (status & AT91_ADC_IER_PEN) {
  202. at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
  203. at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_NOPEN |
  204. ts_data_irq_mask);
  205. /* Set up period trigger for sampling */
  206. at91_adc_writel(st, st->registers->trigger_register,
  207. AT91_ADC_TRGR_MOD_PERIOD_TRIG |
  208. AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
  209. } else if (status & AT91_ADC_IER_NOPEN) {
  210. at91_adc_writel(st, st->registers->trigger_register, 0);
  211. at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_NOPEN |
  212. ts_data_irq_mask);
  213. at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
  214. input_report_key(st->ts_input, BTN_TOUCH, 0);
  215. input_sync(st->ts_input);
  216. } else if ((status & ts_data_irq_mask) == ts_data_irq_mask) {
  217. /* Now all touchscreen data is ready */
  218. if (status & AT91_ADC_ISR_PENS) {
  219. /* validate data by pen contact */
  220. at91_ts_sample(st);
  221. } else {
  222. /* triggered by event that is no pen contact, just read
  223. * them to clean the interrupt and discard all.
  224. */
  225. at91_adc_readl(st, AT91_ADC_TSXPOSR);
  226. at91_adc_readl(st, AT91_ADC_TSYPOSR);
  227. at91_adc_readl(st, AT91_ADC_TSPRESSR);
  228. }
  229. }
  230. return IRQ_HANDLED;
  231. }
  232. static int at91_adc_channel_init(struct iio_dev *idev)
  233. {
  234. struct at91_adc_state *st = iio_priv(idev);
  235. struct iio_chan_spec *chan_array, *timestamp;
  236. int bit, idx = 0;
  237. unsigned long rsvd_mask = 0;
  238. /* If touchscreen is enable, then reserve the adc channels */
  239. if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
  240. rsvd_mask = CHAN_MASK_TOUCHSCREEN_4WIRE;
  241. else if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_5WIRE)
  242. rsvd_mask = CHAN_MASK_TOUCHSCREEN_5WIRE;
  243. /* set up the channel mask to reserve touchscreen channels */
  244. st->channels_mask &= ~rsvd_mask;
  245. idev->num_channels = bitmap_weight(&st->channels_mask,
  246. st->num_channels) + 1;
  247. chan_array = devm_kzalloc(&idev->dev,
  248. ((idev->num_channels + 1) *
  249. sizeof(struct iio_chan_spec)),
  250. GFP_KERNEL);
  251. if (!chan_array)
  252. return -ENOMEM;
  253. for_each_set_bit(bit, &st->channels_mask, st->num_channels) {
  254. struct iio_chan_spec *chan = chan_array + idx;
  255. chan->type = IIO_VOLTAGE;
  256. chan->indexed = 1;
  257. chan->channel = bit;
  258. chan->scan_index = idx;
  259. chan->scan_type.sign = 'u';
  260. chan->scan_type.realbits = st->res;
  261. chan->scan_type.storagebits = 16;
  262. chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
  263. chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
  264. idx++;
  265. }
  266. timestamp = chan_array + idx;
  267. timestamp->type = IIO_TIMESTAMP;
  268. timestamp->channel = -1;
  269. timestamp->scan_index = idx;
  270. timestamp->scan_type.sign = 's';
  271. timestamp->scan_type.realbits = 64;
  272. timestamp->scan_type.storagebits = 64;
  273. idev->channels = chan_array;
  274. return idev->num_channels;
  275. }
  276. static u8 at91_adc_get_trigger_value_by_name(struct iio_dev *idev,
  277. struct at91_adc_trigger *triggers,
  278. const char *trigger_name)
  279. {
  280. struct at91_adc_state *st = iio_priv(idev);
  281. u8 value = 0;
  282. int i;
  283. for (i = 0; i < st->trigger_number; i++) {
  284. char *name = kasprintf(GFP_KERNEL,
  285. "%s-dev%d-%s",
  286. idev->name,
  287. idev->id,
  288. triggers[i].name);
  289. if (!name)
  290. return -ENOMEM;
  291. if (strcmp(trigger_name, name) == 0) {
  292. value = triggers[i].value;
  293. kfree(name);
  294. break;
  295. }
  296. kfree(name);
  297. }
  298. return value;
  299. }
  300. static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
  301. {
  302. struct iio_dev *idev = iio_trigger_get_drvdata(trig);
  303. struct at91_adc_state *st = iio_priv(idev);
  304. struct iio_buffer *buffer = idev->buffer;
  305. struct at91_adc_reg_desc *reg = st->registers;
  306. u32 status = at91_adc_readl(st, reg->trigger_register);
  307. u8 value;
  308. u8 bit;
  309. value = at91_adc_get_trigger_value_by_name(idev,
  310. st->trigger_list,
  311. idev->trig->name);
  312. if (value == 0)
  313. return -EINVAL;
  314. if (state) {
  315. st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL);
  316. if (st->buffer == NULL)
  317. return -ENOMEM;
  318. at91_adc_writel(st, reg->trigger_register,
  319. status | value);
  320. for_each_set_bit(bit, buffer->scan_mask,
  321. st->num_channels) {
  322. struct iio_chan_spec const *chan = idev->channels + bit;
  323. at91_adc_writel(st, AT91_ADC_CHER,
  324. AT91_ADC_CH(chan->channel));
  325. }
  326. at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask);
  327. } else {
  328. at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask);
  329. at91_adc_writel(st, reg->trigger_register,
  330. status & ~value);
  331. for_each_set_bit(bit, buffer->scan_mask,
  332. st->num_channels) {
  333. struct iio_chan_spec const *chan = idev->channels + bit;
  334. at91_adc_writel(st, AT91_ADC_CHDR,
  335. AT91_ADC_CH(chan->channel));
  336. }
  337. kfree(st->buffer);
  338. }
  339. return 0;
  340. }
  341. static const struct iio_trigger_ops at91_adc_trigger_ops = {
  342. .owner = THIS_MODULE,
  343. .set_trigger_state = &at91_adc_configure_trigger,
  344. };
  345. static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev,
  346. struct at91_adc_trigger *trigger)
  347. {
  348. struct iio_trigger *trig;
  349. int ret;
  350. trig = iio_trigger_alloc("%s-dev%d-%s", idev->name,
  351. idev->id, trigger->name);
  352. if (trig == NULL)
  353. return NULL;
  354. trig->dev.parent = idev->dev.parent;
  355. iio_trigger_set_drvdata(trig, idev);
  356. trig->ops = &at91_adc_trigger_ops;
  357. ret = iio_trigger_register(trig);
  358. if (ret)
  359. return NULL;
  360. return trig;
  361. }
  362. static int at91_adc_trigger_init(struct iio_dev *idev)
  363. {
  364. struct at91_adc_state *st = iio_priv(idev);
  365. int i, ret;
  366. st->trig = devm_kzalloc(&idev->dev,
  367. st->trigger_number * sizeof(*st->trig),
  368. GFP_KERNEL);
  369. if (st->trig == NULL) {
  370. ret = -ENOMEM;
  371. goto error_ret;
  372. }
  373. for (i = 0; i < st->trigger_number; i++) {
  374. if (st->trigger_list[i].is_external && !(st->use_external))
  375. continue;
  376. st->trig[i] = at91_adc_allocate_trigger(idev,
  377. st->trigger_list + i);
  378. if (st->trig[i] == NULL) {
  379. dev_err(&idev->dev,
  380. "Could not allocate trigger %d\n", i);
  381. ret = -ENOMEM;
  382. goto error_trigger;
  383. }
  384. }
  385. return 0;
  386. error_trigger:
  387. for (i--; i >= 0; i--) {
  388. iio_trigger_unregister(st->trig[i]);
  389. iio_trigger_free(st->trig[i]);
  390. }
  391. error_ret:
  392. return ret;
  393. }
  394. static void at91_adc_trigger_remove(struct iio_dev *idev)
  395. {
  396. struct at91_adc_state *st = iio_priv(idev);
  397. int i;
  398. for (i = 0; i < st->trigger_number; i++) {
  399. iio_trigger_unregister(st->trig[i]);
  400. iio_trigger_free(st->trig[i]);
  401. }
  402. }
  403. static int at91_adc_buffer_init(struct iio_dev *idev)
  404. {
  405. return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time,
  406. &at91_adc_trigger_handler, NULL);
  407. }
  408. static void at91_adc_buffer_remove(struct iio_dev *idev)
  409. {
  410. iio_triggered_buffer_cleanup(idev);
  411. }
  412. static int at91_adc_read_raw(struct iio_dev *idev,
  413. struct iio_chan_spec const *chan,
  414. int *val, int *val2, long mask)
  415. {
  416. struct at91_adc_state *st = iio_priv(idev);
  417. int ret;
  418. switch (mask) {
  419. case IIO_CHAN_INFO_RAW:
  420. mutex_lock(&st->lock);
  421. at91_adc_writel(st, AT91_ADC_CHER,
  422. AT91_ADC_CH(chan->channel));
  423. at91_adc_writel(st, AT91_ADC_IER, st->registers->drdy_mask);
  424. at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START);
  425. ret = wait_event_interruptible_timeout(st->wq_data_avail,
  426. st->done,
  427. msecs_to_jiffies(1000));
  428. if (ret == 0)
  429. ret = -ETIMEDOUT;
  430. if (ret < 0) {
  431. mutex_unlock(&st->lock);
  432. return ret;
  433. }
  434. *val = st->last_value;
  435. at91_adc_writel(st, AT91_ADC_CHDR,
  436. AT91_ADC_CH(chan->channel));
  437. at91_adc_writel(st, AT91_ADC_IDR, st->registers->drdy_mask);
  438. st->last_value = 0;
  439. st->done = false;
  440. mutex_unlock(&st->lock);
  441. return IIO_VAL_INT;
  442. case IIO_CHAN_INFO_SCALE:
  443. *val = st->vref_mv;
  444. *val2 = chan->scan_type.realbits;
  445. return IIO_VAL_FRACTIONAL_LOG2;
  446. default:
  447. break;
  448. }
  449. return -EINVAL;
  450. }
  451. static int at91_adc_of_get_resolution(struct at91_adc_state *st,
  452. struct platform_device *pdev)
  453. {
  454. struct iio_dev *idev = iio_priv_to_dev(st);
  455. struct device_node *np = pdev->dev.of_node;
  456. int count, i, ret = 0;
  457. char *res_name, *s;
  458. u32 *resolutions;
  459. count = of_property_count_strings(np, "atmel,adc-res-names");
  460. if (count < 2) {
  461. dev_err(&idev->dev, "You must specified at least two resolution names for "
  462. "adc-res-names property in the DT\n");
  463. return count;
  464. }
  465. resolutions = kmalloc(count * sizeof(*resolutions), GFP_KERNEL);
  466. if (!resolutions)
  467. return -ENOMEM;
  468. if (of_property_read_u32_array(np, "atmel,adc-res", resolutions, count)) {
  469. dev_err(&idev->dev, "Missing adc-res property in the DT.\n");
  470. ret = -ENODEV;
  471. goto ret;
  472. }
  473. if (of_property_read_string(np, "atmel,adc-use-res", (const char **)&res_name))
  474. res_name = "highres";
  475. for (i = 0; i < count; i++) {
  476. if (of_property_read_string_index(np, "atmel,adc-res-names", i, (const char **)&s))
  477. continue;
  478. if (strcmp(res_name, s))
  479. continue;
  480. st->res = resolutions[i];
  481. if (!strcmp(res_name, "lowres"))
  482. st->low_res = true;
  483. else
  484. st->low_res = false;
  485. dev_info(&idev->dev, "Resolution used: %u bits\n", st->res);
  486. goto ret;
  487. }
  488. dev_err(&idev->dev, "There is no resolution for %s\n", res_name);
  489. ret:
  490. kfree(resolutions);
  491. return ret;
  492. }
  493. static u32 calc_startup_ticks_9260(u8 startup_time, u32 adc_clk_khz)
  494. {
  495. /*
  496. * Number of ticks needed to cover the startup time of the ADC
  497. * as defined in the electrical characteristics of the board,
  498. * divided by 8. The formula thus is :
  499. * Startup Time = (ticks + 1) * 8 / ADC Clock
  500. */
  501. return round_up((startup_time * adc_clk_khz / 1000) - 1, 8) / 8;
  502. }
  503. static u32 calc_startup_ticks_9x5(u8 startup_time, u32 adc_clk_khz)
  504. {
  505. /*
  506. * For sama5d3x and at91sam9x5, the formula changes to:
  507. * Startup Time = <lookup_table_value> / ADC Clock
  508. */
  509. const int startup_lookup[] = {
  510. 0 , 8 , 16 , 24 ,
  511. 64 , 80 , 96 , 112,
  512. 512, 576, 640, 704,
  513. 768, 832, 896, 960
  514. };
  515. int i, size = ARRAY_SIZE(startup_lookup);
  516. unsigned int ticks;
  517. ticks = startup_time * adc_clk_khz / 1000;
  518. for (i = 0; i < size; i++)
  519. if (ticks < startup_lookup[i])
  520. break;
  521. ticks = i;
  522. if (ticks == size)
  523. /* Reach the end of lookup table */
  524. ticks = size - 1;
  525. return ticks;
  526. }
  527. static const struct of_device_id at91_adc_dt_ids[];
  528. static int at91_adc_probe_dt_ts(struct device_node *node,
  529. struct at91_adc_state *st, struct device *dev)
  530. {
  531. int ret;
  532. u32 prop;
  533. ret = of_property_read_u32(node, "atmel,adc-ts-wires", &prop);
  534. if (ret) {
  535. dev_info(dev, "ADC Touch screen is disabled.\n");
  536. return 0;
  537. }
  538. switch (prop) {
  539. case 4:
  540. case 5:
  541. st->touchscreen_type = prop;
  542. break;
  543. default:
  544. dev_err(dev, "Unsupported number of touchscreen wires (%d). Should be 4 or 5.\n", prop);
  545. return -EINVAL;
  546. }
  547. prop = 0;
  548. of_property_read_u32(node, "atmel,adc-ts-pressure-threshold", &prop);
  549. st->ts_pressure_threshold = prop;
  550. if (st->ts_pressure_threshold) {
  551. return 0;
  552. } else {
  553. dev_err(dev, "Invalid pressure threshold for the touchscreen\n");
  554. return -EINVAL;
  555. }
  556. }
  557. static int at91_adc_probe_dt(struct at91_adc_state *st,
  558. struct platform_device *pdev)
  559. {
  560. struct iio_dev *idev = iio_priv_to_dev(st);
  561. struct device_node *node = pdev->dev.of_node;
  562. struct device_node *trig_node;
  563. int i = 0, ret;
  564. u32 prop;
  565. if (!node)
  566. return -EINVAL;
  567. st->caps = (struct at91_adc_caps *)
  568. of_match_device(at91_adc_dt_ids, &pdev->dev)->data;
  569. st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers");
  570. if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) {
  571. dev_err(&idev->dev, "Missing adc-channels-used property in the DT.\n");
  572. ret = -EINVAL;
  573. goto error_ret;
  574. }
  575. st->channels_mask = prop;
  576. st->sleep_mode = of_property_read_bool(node, "atmel,adc-sleep-mode");
  577. if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) {
  578. dev_err(&idev->dev, "Missing adc-startup-time property in the DT.\n");
  579. ret = -EINVAL;
  580. goto error_ret;
  581. }
  582. st->startup_time = prop;
  583. prop = 0;
  584. of_property_read_u32(node, "atmel,adc-sample-hold-time", &prop);
  585. st->sample_hold_time = prop;
  586. if (of_property_read_u32(node, "atmel,adc-vref", &prop)) {
  587. dev_err(&idev->dev, "Missing adc-vref property in the DT.\n");
  588. ret = -EINVAL;
  589. goto error_ret;
  590. }
  591. st->vref_mv = prop;
  592. ret = at91_adc_of_get_resolution(st, pdev);
  593. if (ret)
  594. goto error_ret;
  595. st->registers = &st->caps->registers;
  596. st->num_channels = st->caps->num_channels;
  597. st->trigger_number = of_get_child_count(node);
  598. st->trigger_list = devm_kzalloc(&idev->dev, st->trigger_number *
  599. sizeof(struct at91_adc_trigger),
  600. GFP_KERNEL);
  601. if (!st->trigger_list) {
  602. dev_err(&idev->dev, "Could not allocate trigger list memory.\n");
  603. ret = -ENOMEM;
  604. goto error_ret;
  605. }
  606. for_each_child_of_node(node, trig_node) {
  607. struct at91_adc_trigger *trig = st->trigger_list + i;
  608. const char *name;
  609. if (of_property_read_string(trig_node, "trigger-name", &name)) {
  610. dev_err(&idev->dev, "Missing trigger-name property in the DT.\n");
  611. ret = -EINVAL;
  612. goto error_ret;
  613. }
  614. trig->name = name;
  615. if (of_property_read_u32(trig_node, "trigger-value", &prop)) {
  616. dev_err(&idev->dev, "Missing trigger-value property in the DT.\n");
  617. ret = -EINVAL;
  618. goto error_ret;
  619. }
  620. trig->value = prop;
  621. trig->is_external = of_property_read_bool(trig_node, "trigger-external");
  622. i++;
  623. }
  624. /* Check if touchscreen is supported. */
  625. if (st->caps->has_ts)
  626. return at91_adc_probe_dt_ts(node, st, &idev->dev);
  627. else
  628. dev_info(&idev->dev, "not support touchscreen in the adc compatible string.\n");
  629. return 0;
  630. error_ret:
  631. return ret;
  632. }
  633. static int at91_adc_probe_pdata(struct at91_adc_state *st,
  634. struct platform_device *pdev)
  635. {
  636. struct at91_adc_data *pdata = pdev->dev.platform_data;
  637. if (!pdata)
  638. return -EINVAL;
  639. st->use_external = pdata->use_external_triggers;
  640. st->vref_mv = pdata->vref;
  641. st->channels_mask = pdata->channels_used;
  642. st->num_channels = pdata->num_channels;
  643. st->startup_time = pdata->startup_time;
  644. st->trigger_number = pdata->trigger_number;
  645. st->trigger_list = pdata->trigger_list;
  646. st->registers = pdata->registers;
  647. return 0;
  648. }
  649. static const struct iio_info at91_adc_info = {
  650. .driver_module = THIS_MODULE,
  651. .read_raw = &at91_adc_read_raw,
  652. };
  653. /* Touchscreen related functions */
  654. static int atmel_ts_open(struct input_dev *dev)
  655. {
  656. struct at91_adc_state *st = input_get_drvdata(dev);
  657. at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
  658. return 0;
  659. }
  660. static void atmel_ts_close(struct input_dev *dev)
  661. {
  662. struct at91_adc_state *st = input_get_drvdata(dev);
  663. at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
  664. }
  665. static int at91_ts_hw_init(struct at91_adc_state *st, u32 adc_clk_khz)
  666. {
  667. u32 reg = 0, pendbc;
  668. int i = 0;
  669. if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
  670. reg = AT91_ADC_TSMR_TSMODE_4WIRE_PRESS;
  671. else
  672. reg = AT91_ADC_TSMR_TSMODE_5WIRE;
  673. /* a Pen Detect Debounce Time is necessary for the ADC Touch to avoid
  674. * pen detect noise.
  675. * The formula is : Pen Detect Debounce Time = (2 ^ pendbc) / ADCClock
  676. */
  677. pendbc = round_up(TOUCH_PEN_DETECT_DEBOUNCE_US * adc_clk_khz / 1000, 1);
  678. while (pendbc >> ++i)
  679. ; /* Empty! Find the shift offset */
  680. if (abs(pendbc - (1 << i)) < abs(pendbc - (1 << (i - 1))))
  681. pendbc = i;
  682. else
  683. pendbc = i - 1;
  684. if (st->caps->has_tsmr) {
  685. reg |= AT91_ADC_TSMR_TSAV_(st->caps->ts_filter_average)
  686. & AT91_ADC_TSMR_TSAV;
  687. reg |= AT91_ADC_TSMR_PENDBC_(pendbc) & AT91_ADC_TSMR_PENDBC;
  688. reg |= AT91_ADC_TSMR_NOTSDMA;
  689. reg |= AT91_ADC_TSMR_PENDET_ENA;
  690. reg |= 0x03 << 8; /* TSFREQ, need bigger than TSAV */
  691. at91_adc_writel(st, AT91_ADC_TSMR, reg);
  692. } else {
  693. /* TODO: for 9g45 which has no TSMR */
  694. }
  695. /* Change adc internal resistor value for better pen detection,
  696. * default value is 100 kOhm.
  697. * 0 = 200 kOhm, 1 = 150 kOhm, 2 = 100 kOhm, 3 = 50 kOhm
  698. * option only available on ES2 and higher
  699. */
  700. at91_adc_writel(st, AT91_ADC_ACR, st->caps->ts_pen_detect_sensitivity
  701. & AT91_ADC_ACR_PENDETSENS);
  702. /* Sample Peroid Time = (TRGPER + 1) / ADCClock */
  703. st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US *
  704. adc_clk_khz / 1000) - 1, 1);
  705. return 0;
  706. }
  707. static int at91_ts_register(struct at91_adc_state *st,
  708. struct platform_device *pdev)
  709. {
  710. struct input_dev *input;
  711. struct iio_dev *idev = iio_priv_to_dev(st);
  712. int ret;
  713. input = input_allocate_device();
  714. if (!input) {
  715. dev_err(&idev->dev, "Failed to allocate TS device!\n");
  716. return -ENOMEM;
  717. }
  718. input->name = DRIVER_NAME;
  719. input->id.bustype = BUS_HOST;
  720. input->dev.parent = &pdev->dev;
  721. input->open = atmel_ts_open;
  722. input->close = atmel_ts_close;
  723. __set_bit(EV_ABS, input->evbit);
  724. __set_bit(EV_KEY, input->evbit);
  725. __set_bit(BTN_TOUCH, input->keybit);
  726. input_set_abs_params(input, ABS_X, 0, (1 << MAX_POS_BITS) - 1, 0, 0);
  727. input_set_abs_params(input, ABS_Y, 0, (1 << MAX_POS_BITS) - 1, 0, 0);
  728. input_set_abs_params(input, ABS_PRESSURE, 0, 0xffffff, 0, 0);
  729. st->ts_input = input;
  730. input_set_drvdata(input, st);
  731. ret = input_register_device(input);
  732. if (ret)
  733. input_free_device(st->ts_input);
  734. return ret;
  735. }
  736. static void at91_ts_unregister(struct at91_adc_state *st)
  737. {
  738. input_unregister_device(st->ts_input);
  739. }
  740. static int at91_adc_probe(struct platform_device *pdev)
  741. {
  742. unsigned int prsc, mstrclk, ticks, adc_clk, adc_clk_khz, shtim;
  743. int ret;
  744. struct iio_dev *idev;
  745. struct at91_adc_state *st;
  746. struct resource *res;
  747. u32 reg;
  748. idev = devm_iio_device_alloc(&pdev->dev, sizeof(struct at91_adc_state));
  749. if (!idev)
  750. return -ENOMEM;
  751. st = iio_priv(idev);
  752. if (pdev->dev.of_node)
  753. ret = at91_adc_probe_dt(st, pdev);
  754. else
  755. ret = at91_adc_probe_pdata(st, pdev);
  756. if (ret) {
  757. dev_err(&pdev->dev, "No platform data available.\n");
  758. return -EINVAL;
  759. }
  760. platform_set_drvdata(pdev, idev);
  761. idev->dev.parent = &pdev->dev;
  762. idev->name = dev_name(&pdev->dev);
  763. idev->modes = INDIO_DIRECT_MODE;
  764. idev->info = &at91_adc_info;
  765. st->irq = platform_get_irq(pdev, 0);
  766. if (st->irq < 0) {
  767. dev_err(&pdev->dev, "No IRQ ID is designated\n");
  768. return -ENODEV;
  769. }
  770. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  771. st->reg_base = devm_ioremap_resource(&pdev->dev, res);
  772. if (IS_ERR(st->reg_base)) {
  773. return PTR_ERR(st->reg_base);
  774. }
  775. /*
  776. * Disable all IRQs before setting up the handler
  777. */
  778. at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST);
  779. at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF);
  780. ret = request_irq(st->irq,
  781. at91_adc_interrupt,
  782. 0,
  783. pdev->dev.driver->name,
  784. idev);
  785. if (ret) {
  786. dev_err(&pdev->dev, "Failed to allocate IRQ.\n");
  787. return ret;
  788. }
  789. st->clk = devm_clk_get(&pdev->dev, "adc_clk");
  790. if (IS_ERR(st->clk)) {
  791. dev_err(&pdev->dev, "Failed to get the clock.\n");
  792. ret = PTR_ERR(st->clk);
  793. goto error_free_irq;
  794. }
  795. ret = clk_prepare_enable(st->clk);
  796. if (ret) {
  797. dev_err(&pdev->dev,
  798. "Could not prepare or enable the clock.\n");
  799. goto error_free_irq;
  800. }
  801. st->adc_clk = devm_clk_get(&pdev->dev, "adc_op_clk");
  802. if (IS_ERR(st->adc_clk)) {
  803. dev_err(&pdev->dev, "Failed to get the ADC clock.\n");
  804. ret = PTR_ERR(st->adc_clk);
  805. goto error_disable_clk;
  806. }
  807. ret = clk_prepare_enable(st->adc_clk);
  808. if (ret) {
  809. dev_err(&pdev->dev,
  810. "Could not prepare or enable the ADC clock.\n");
  811. goto error_disable_clk;
  812. }
  813. /*
  814. * Prescaler rate computation using the formula from the Atmel's
  815. * datasheet : ADC Clock = MCK / ((Prescaler + 1) * 2), ADC Clock being
  816. * specified by the electrical characteristics of the board.
  817. */
  818. mstrclk = clk_get_rate(st->clk);
  819. adc_clk = clk_get_rate(st->adc_clk);
  820. adc_clk_khz = adc_clk / 1000;
  821. dev_dbg(&pdev->dev, "Master clock is set as: %d Hz, adc_clk should set as: %d Hz\n",
  822. mstrclk, adc_clk);
  823. prsc = (mstrclk / (2 * adc_clk)) - 1;
  824. if (!st->startup_time) {
  825. dev_err(&pdev->dev, "No startup time available.\n");
  826. ret = -EINVAL;
  827. goto error_disable_adc_clk;
  828. }
  829. ticks = (*st->caps->calc_startup_ticks)(st->startup_time, adc_clk_khz);
  830. /*
  831. * a minimal Sample and Hold Time is necessary for the ADC to guarantee
  832. * the best converted final value between two channels selection
  833. * The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock
  834. */
  835. shtim = round_up((st->sample_hold_time * adc_clk_khz /
  836. 1000) - 1, 1);
  837. reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask;
  838. reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask;
  839. if (st->low_res)
  840. reg |= AT91_ADC_LOWRES;
  841. if (st->sleep_mode)
  842. reg |= AT91_ADC_SLEEP;
  843. reg |= AT91_ADC_SHTIM_(shtim) & AT91_ADC_SHTIM;
  844. at91_adc_writel(st, AT91_ADC_MR, reg);
  845. /* Setup the ADC channels available on the board */
  846. ret = at91_adc_channel_init(idev);
  847. if (ret < 0) {
  848. dev_err(&pdev->dev, "Couldn't initialize the channels.\n");
  849. goto error_disable_adc_clk;
  850. }
  851. init_waitqueue_head(&st->wq_data_avail);
  852. mutex_init(&st->lock);
  853. /*
  854. * Since touch screen will set trigger register as period trigger. So
  855. * when touch screen is enabled, then we have to disable hardware
  856. * trigger for classic adc.
  857. */
  858. if (!st->touchscreen_type) {
  859. ret = at91_adc_buffer_init(idev);
  860. if (ret < 0) {
  861. dev_err(&pdev->dev, "Couldn't initialize the buffer.\n");
  862. goto error_disable_adc_clk;
  863. }
  864. ret = at91_adc_trigger_init(idev);
  865. if (ret < 0) {
  866. dev_err(&pdev->dev, "Couldn't setup the triggers.\n");
  867. at91_adc_buffer_remove(idev);
  868. goto error_disable_adc_clk;
  869. }
  870. } else {
  871. if (!st->caps->has_tsmr) {
  872. dev_err(&pdev->dev, "We don't support non-TSMR adc\n");
  873. ret = -ENODEV;
  874. goto error_disable_adc_clk;
  875. }
  876. ret = at91_ts_register(st, pdev);
  877. if (ret)
  878. goto error_disable_adc_clk;
  879. at91_ts_hw_init(st, adc_clk_khz);
  880. }
  881. ret = iio_device_register(idev);
  882. if (ret < 0) {
  883. dev_err(&pdev->dev, "Couldn't register the device.\n");
  884. goto error_iio_device_register;
  885. }
  886. return 0;
  887. error_iio_device_register:
  888. if (!st->touchscreen_type) {
  889. at91_adc_trigger_remove(idev);
  890. at91_adc_buffer_remove(idev);
  891. } else {
  892. at91_ts_unregister(st);
  893. }
  894. error_disable_adc_clk:
  895. clk_disable_unprepare(st->adc_clk);
  896. error_disable_clk:
  897. clk_disable_unprepare(st->clk);
  898. error_free_irq:
  899. free_irq(st->irq, idev);
  900. return ret;
  901. }
  902. static int at91_adc_remove(struct platform_device *pdev)
  903. {
  904. struct iio_dev *idev = platform_get_drvdata(pdev);
  905. struct at91_adc_state *st = iio_priv(idev);
  906. iio_device_unregister(idev);
  907. if (!st->touchscreen_type) {
  908. at91_adc_trigger_remove(idev);
  909. at91_adc_buffer_remove(idev);
  910. } else {
  911. at91_ts_unregister(st);
  912. }
  913. clk_disable_unprepare(st->adc_clk);
  914. clk_disable_unprepare(st->clk);
  915. free_irq(st->irq, idev);
  916. return 0;
  917. }
  918. #ifdef CONFIG_OF
  919. static struct at91_adc_caps at91sam9260_caps = {
  920. .calc_startup_ticks = calc_startup_ticks_9260,
  921. .num_channels = 4,
  922. .registers = {
  923. .channel_base = AT91_ADC_CHR(0),
  924. .drdy_mask = AT91_ADC_DRDY,
  925. .status_register = AT91_ADC_SR,
  926. .trigger_register = AT91_ADC_TRGR_9260,
  927. .mr_prescal_mask = AT91_ADC_PRESCAL_9260,
  928. .mr_startup_mask = AT91_ADC_STARTUP_9260,
  929. },
  930. };
  931. static struct at91_adc_caps at91sam9g45_caps = {
  932. .has_ts = true,
  933. .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */
  934. .num_channels = 8,
  935. .registers = {
  936. .channel_base = AT91_ADC_CHR(0),
  937. .drdy_mask = AT91_ADC_DRDY,
  938. .status_register = AT91_ADC_SR,
  939. .trigger_register = AT91_ADC_TRGR_9G45,
  940. .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
  941. .mr_startup_mask = AT91_ADC_STARTUP_9G45,
  942. },
  943. };
  944. static struct at91_adc_caps at91sam9x5_caps = {
  945. .has_ts = true,
  946. .has_tsmr = true,
  947. .ts_filter_average = 3,
  948. .ts_pen_detect_sensitivity = 2,
  949. .calc_startup_ticks = calc_startup_ticks_9x5,
  950. .num_channels = 12,
  951. .registers = {
  952. .channel_base = AT91_ADC_CDR0_9X5,
  953. .drdy_mask = AT91_ADC_SR_DRDY_9X5,
  954. .status_register = AT91_ADC_SR_9X5,
  955. .trigger_register = AT91_ADC_TRGR_9X5,
  956. /* prescal mask is same as 9G45 */
  957. .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
  958. .mr_startup_mask = AT91_ADC_STARTUP_9X5,
  959. },
  960. };
  961. static const struct of_device_id at91_adc_dt_ids[] = {
  962. { .compatible = "atmel,at91sam9260-adc", .data = &at91sam9260_caps },
  963. { .compatible = "atmel,at91sam9g45-adc", .data = &at91sam9g45_caps },
  964. { .compatible = "atmel,at91sam9x5-adc", .data = &at91sam9x5_caps },
  965. {},
  966. };
  967. MODULE_DEVICE_TABLE(of, at91_adc_dt_ids);
  968. #endif
  969. static struct platform_driver at91_adc_driver = {
  970. .probe = at91_adc_probe,
  971. .remove = at91_adc_remove,
  972. .driver = {
  973. .name = DRIVER_NAME,
  974. .of_match_table = of_match_ptr(at91_adc_dt_ids),
  975. },
  976. };
  977. module_platform_driver(at91_adc_driver);
  978. MODULE_LICENSE("GPL");
  979. MODULE_DESCRIPTION("Atmel AT91 ADC Driver");
  980. MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");