iommu.c 19 KB

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  1. /* iommu.c: Generic sparc64 IOMMU support.
  2. *
  3. * Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net)
  4. * Copyright (C) 1999, 2000 Jakub Jelinek (jakub@redhat.com)
  5. */
  6. #include <linux/kernel.h>
  7. #include <linux/module.h>
  8. #include <linux/delay.h>
  9. #include <linux/device.h>
  10. #include <linux/dma-mapping.h>
  11. #include <linux/errno.h>
  12. #ifdef CONFIG_PCI
  13. #include <linux/pci.h>
  14. #endif
  15. #include <asm/iommu.h>
  16. #include "iommu_common.h"
  17. #define STC_CTXMATCH_ADDR(STC, CTX) \
  18. ((STC)->strbuf_ctxmatch_base + ((CTX) << 3))
  19. #define STC_FLUSHFLAG_INIT(STC) \
  20. (*((STC)->strbuf_flushflag) = 0UL)
  21. #define STC_FLUSHFLAG_SET(STC) \
  22. (*((STC)->strbuf_flushflag) != 0UL)
  23. #define iommu_read(__reg) \
  24. ({ u64 __ret; \
  25. __asm__ __volatile__("ldxa [%1] %2, %0" \
  26. : "=r" (__ret) \
  27. : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
  28. : "memory"); \
  29. __ret; \
  30. })
  31. #define iommu_write(__reg, __val) \
  32. __asm__ __volatile__("stxa %0, [%1] %2" \
  33. : /* no outputs */ \
  34. : "r" (__val), "r" (__reg), \
  35. "i" (ASI_PHYS_BYPASS_EC_E))
  36. /* Must be invoked under the IOMMU lock. */
  37. static void __iommu_flushall(struct iommu *iommu)
  38. {
  39. if (iommu->iommu_flushinv) {
  40. iommu_write(iommu->iommu_flushinv, ~(u64)0);
  41. } else {
  42. unsigned long tag;
  43. int entry;
  44. tag = iommu->iommu_tags;
  45. for (entry = 0; entry < 16; entry++) {
  46. iommu_write(tag, 0);
  47. tag += 8;
  48. }
  49. /* Ensure completion of previous PIO writes. */
  50. (void) iommu_read(iommu->write_complete_reg);
  51. }
  52. }
  53. #define IOPTE_CONSISTENT(CTX) \
  54. (IOPTE_VALID | IOPTE_CACHE | \
  55. (((CTX) << 47) & IOPTE_CONTEXT))
  56. #define IOPTE_STREAMING(CTX) \
  57. (IOPTE_CONSISTENT(CTX) | IOPTE_STBUF)
  58. /* Existing mappings are never marked invalid, instead they
  59. * are pointed to a dummy page.
  60. */
  61. #define IOPTE_IS_DUMMY(iommu, iopte) \
  62. ((iopte_val(*iopte) & IOPTE_PAGE) == (iommu)->dummy_page_pa)
  63. static inline void iopte_make_dummy(struct iommu *iommu, iopte_t *iopte)
  64. {
  65. unsigned long val = iopte_val(*iopte);
  66. val &= ~IOPTE_PAGE;
  67. val |= iommu->dummy_page_pa;
  68. iopte_val(*iopte) = val;
  69. }
  70. /* Based largely upon the ppc64 iommu allocator. */
  71. static long arena_alloc(struct iommu *iommu, unsigned long npages)
  72. {
  73. struct iommu_arena *arena = &iommu->arena;
  74. unsigned long n, i, start, end, limit;
  75. int pass;
  76. limit = arena->limit;
  77. start = arena->hint;
  78. pass = 0;
  79. again:
  80. n = find_next_zero_bit(arena->map, limit, start);
  81. end = n + npages;
  82. if (unlikely(end >= limit)) {
  83. if (likely(pass < 1)) {
  84. limit = start;
  85. start = 0;
  86. __iommu_flushall(iommu);
  87. pass++;
  88. goto again;
  89. } else {
  90. /* Scanned the whole thing, give up. */
  91. return -1;
  92. }
  93. }
  94. for (i = n; i < end; i++) {
  95. if (test_bit(i, arena->map)) {
  96. start = i + 1;
  97. goto again;
  98. }
  99. }
  100. for (i = n; i < end; i++)
  101. __set_bit(i, arena->map);
  102. arena->hint = end;
  103. return n;
  104. }
  105. static void arena_free(struct iommu_arena *arena, unsigned long base, unsigned long npages)
  106. {
  107. unsigned long i;
  108. for (i = base; i < (base + npages); i++)
  109. __clear_bit(i, arena->map);
  110. }
  111. int iommu_table_init(struct iommu *iommu, int tsbsize,
  112. u32 dma_offset, u32 dma_addr_mask)
  113. {
  114. unsigned long i, tsbbase, order, sz, num_tsb_entries;
  115. num_tsb_entries = tsbsize / sizeof(iopte_t);
  116. /* Setup initial software IOMMU state. */
  117. spin_lock_init(&iommu->lock);
  118. iommu->ctx_lowest_free = 1;
  119. iommu->page_table_map_base = dma_offset;
  120. iommu->dma_addr_mask = dma_addr_mask;
  121. /* Allocate and initialize the free area map. */
  122. sz = num_tsb_entries / 8;
  123. sz = (sz + 7UL) & ~7UL;
  124. iommu->arena.map = kzalloc(sz, GFP_KERNEL);
  125. if (!iommu->arena.map) {
  126. printk(KERN_ERR "IOMMU: Error, kmalloc(arena.map) failed.\n");
  127. return -ENOMEM;
  128. }
  129. iommu->arena.limit = num_tsb_entries;
  130. /* Allocate and initialize the dummy page which we
  131. * set inactive IO PTEs to point to.
  132. */
  133. iommu->dummy_page = __get_free_pages(GFP_KERNEL, 0);
  134. if (!iommu->dummy_page) {
  135. printk(KERN_ERR "IOMMU: Error, gfp(dummy_page) failed.\n");
  136. goto out_free_map;
  137. }
  138. memset((void *)iommu->dummy_page, 0, PAGE_SIZE);
  139. iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page);
  140. /* Now allocate and setup the IOMMU page table itself. */
  141. order = get_order(tsbsize);
  142. tsbbase = __get_free_pages(GFP_KERNEL, order);
  143. if (!tsbbase) {
  144. printk(KERN_ERR "IOMMU: Error, gfp(tsb) failed.\n");
  145. goto out_free_dummy_page;
  146. }
  147. iommu->page_table = (iopte_t *)tsbbase;
  148. for (i = 0; i < num_tsb_entries; i++)
  149. iopte_make_dummy(iommu, &iommu->page_table[i]);
  150. return 0;
  151. out_free_dummy_page:
  152. free_page(iommu->dummy_page);
  153. iommu->dummy_page = 0UL;
  154. out_free_map:
  155. kfree(iommu->arena.map);
  156. iommu->arena.map = NULL;
  157. return -ENOMEM;
  158. }
  159. static inline iopte_t *alloc_npages(struct iommu *iommu, unsigned long npages)
  160. {
  161. long entry;
  162. entry = arena_alloc(iommu, npages);
  163. if (unlikely(entry < 0))
  164. return NULL;
  165. return iommu->page_table + entry;
  166. }
  167. static inline void free_npages(struct iommu *iommu, dma_addr_t base, unsigned long npages)
  168. {
  169. arena_free(&iommu->arena, base >> IO_PAGE_SHIFT, npages);
  170. }
  171. static int iommu_alloc_ctx(struct iommu *iommu)
  172. {
  173. int lowest = iommu->ctx_lowest_free;
  174. int sz = IOMMU_NUM_CTXS - lowest;
  175. int n = find_next_zero_bit(iommu->ctx_bitmap, sz, lowest);
  176. if (unlikely(n == sz)) {
  177. n = find_next_zero_bit(iommu->ctx_bitmap, lowest, 1);
  178. if (unlikely(n == lowest)) {
  179. printk(KERN_WARNING "IOMMU: Ran out of contexts.\n");
  180. n = 0;
  181. }
  182. }
  183. if (n)
  184. __set_bit(n, iommu->ctx_bitmap);
  185. return n;
  186. }
  187. static inline void iommu_free_ctx(struct iommu *iommu, int ctx)
  188. {
  189. if (likely(ctx)) {
  190. __clear_bit(ctx, iommu->ctx_bitmap);
  191. if (ctx < iommu->ctx_lowest_free)
  192. iommu->ctx_lowest_free = ctx;
  193. }
  194. }
  195. static void *dma_4u_alloc_coherent(struct device *dev, size_t size,
  196. dma_addr_t *dma_addrp, gfp_t gfp)
  197. {
  198. struct iommu *iommu;
  199. iopte_t *iopte;
  200. unsigned long flags, order, first_page;
  201. void *ret;
  202. int npages;
  203. size = IO_PAGE_ALIGN(size);
  204. order = get_order(size);
  205. if (order >= 10)
  206. return NULL;
  207. first_page = __get_free_pages(gfp, order);
  208. if (first_page == 0UL)
  209. return NULL;
  210. memset((char *)first_page, 0, PAGE_SIZE << order);
  211. iommu = dev->archdata.iommu;
  212. spin_lock_irqsave(&iommu->lock, flags);
  213. iopte = alloc_npages(iommu, size >> IO_PAGE_SHIFT);
  214. spin_unlock_irqrestore(&iommu->lock, flags);
  215. if (unlikely(iopte == NULL)) {
  216. free_pages(first_page, order);
  217. return NULL;
  218. }
  219. *dma_addrp = (iommu->page_table_map_base +
  220. ((iopte - iommu->page_table) << IO_PAGE_SHIFT));
  221. ret = (void *) first_page;
  222. npages = size >> IO_PAGE_SHIFT;
  223. first_page = __pa(first_page);
  224. while (npages--) {
  225. iopte_val(*iopte) = (IOPTE_CONSISTENT(0UL) |
  226. IOPTE_WRITE |
  227. (first_page & IOPTE_PAGE));
  228. iopte++;
  229. first_page += IO_PAGE_SIZE;
  230. }
  231. return ret;
  232. }
  233. static void dma_4u_free_coherent(struct device *dev, size_t size,
  234. void *cpu, dma_addr_t dvma)
  235. {
  236. struct iommu *iommu;
  237. iopte_t *iopte;
  238. unsigned long flags, order, npages;
  239. npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
  240. iommu = dev->archdata.iommu;
  241. iopte = iommu->page_table +
  242. ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
  243. spin_lock_irqsave(&iommu->lock, flags);
  244. free_npages(iommu, dvma - iommu->page_table_map_base, npages);
  245. spin_unlock_irqrestore(&iommu->lock, flags);
  246. order = get_order(size);
  247. if (order < 10)
  248. free_pages((unsigned long)cpu, order);
  249. }
  250. static dma_addr_t dma_4u_map_single(struct device *dev, void *ptr, size_t sz,
  251. enum dma_data_direction direction)
  252. {
  253. struct iommu *iommu;
  254. struct strbuf *strbuf;
  255. iopte_t *base;
  256. unsigned long flags, npages, oaddr;
  257. unsigned long i, base_paddr, ctx;
  258. u32 bus_addr, ret;
  259. unsigned long iopte_protection;
  260. iommu = dev->archdata.iommu;
  261. strbuf = dev->archdata.stc;
  262. if (unlikely(direction == DMA_NONE))
  263. goto bad_no_ctx;
  264. oaddr = (unsigned long)ptr;
  265. npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
  266. npages >>= IO_PAGE_SHIFT;
  267. spin_lock_irqsave(&iommu->lock, flags);
  268. base = alloc_npages(iommu, npages);
  269. ctx = 0;
  270. if (iommu->iommu_ctxflush)
  271. ctx = iommu_alloc_ctx(iommu);
  272. spin_unlock_irqrestore(&iommu->lock, flags);
  273. if (unlikely(!base))
  274. goto bad;
  275. bus_addr = (iommu->page_table_map_base +
  276. ((base - iommu->page_table) << IO_PAGE_SHIFT));
  277. ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
  278. base_paddr = __pa(oaddr & IO_PAGE_MASK);
  279. if (strbuf->strbuf_enabled)
  280. iopte_protection = IOPTE_STREAMING(ctx);
  281. else
  282. iopte_protection = IOPTE_CONSISTENT(ctx);
  283. if (direction != DMA_TO_DEVICE)
  284. iopte_protection |= IOPTE_WRITE;
  285. for (i = 0; i < npages; i++, base++, base_paddr += IO_PAGE_SIZE)
  286. iopte_val(*base) = iopte_protection | base_paddr;
  287. return ret;
  288. bad:
  289. iommu_free_ctx(iommu, ctx);
  290. bad_no_ctx:
  291. if (printk_ratelimit())
  292. WARN_ON(1);
  293. return DMA_ERROR_CODE;
  294. }
  295. static void strbuf_flush(struct strbuf *strbuf, struct iommu *iommu,
  296. u32 vaddr, unsigned long ctx, unsigned long npages,
  297. enum dma_data_direction direction)
  298. {
  299. int limit;
  300. if (strbuf->strbuf_ctxflush &&
  301. iommu->iommu_ctxflush) {
  302. unsigned long matchreg, flushreg;
  303. u64 val;
  304. flushreg = strbuf->strbuf_ctxflush;
  305. matchreg = STC_CTXMATCH_ADDR(strbuf, ctx);
  306. iommu_write(flushreg, ctx);
  307. val = iommu_read(matchreg);
  308. val &= 0xffff;
  309. if (!val)
  310. goto do_flush_sync;
  311. while (val) {
  312. if (val & 0x1)
  313. iommu_write(flushreg, ctx);
  314. val >>= 1;
  315. }
  316. val = iommu_read(matchreg);
  317. if (unlikely(val)) {
  318. printk(KERN_WARNING "strbuf_flush: ctx flush "
  319. "timeout matchreg[%lx] ctx[%lx]\n",
  320. val, ctx);
  321. goto do_page_flush;
  322. }
  323. } else {
  324. unsigned long i;
  325. do_page_flush:
  326. for (i = 0; i < npages; i++, vaddr += IO_PAGE_SIZE)
  327. iommu_write(strbuf->strbuf_pflush, vaddr);
  328. }
  329. do_flush_sync:
  330. /* If the device could not have possibly put dirty data into
  331. * the streaming cache, no flush-flag synchronization needs
  332. * to be performed.
  333. */
  334. if (direction == DMA_TO_DEVICE)
  335. return;
  336. STC_FLUSHFLAG_INIT(strbuf);
  337. iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa);
  338. (void) iommu_read(iommu->write_complete_reg);
  339. limit = 100000;
  340. while (!STC_FLUSHFLAG_SET(strbuf)) {
  341. limit--;
  342. if (!limit)
  343. break;
  344. udelay(1);
  345. rmb();
  346. }
  347. if (!limit)
  348. printk(KERN_WARNING "strbuf_flush: flushflag timeout "
  349. "vaddr[%08x] ctx[%lx] npages[%ld]\n",
  350. vaddr, ctx, npages);
  351. }
  352. static void dma_4u_unmap_single(struct device *dev, dma_addr_t bus_addr,
  353. size_t sz, enum dma_data_direction direction)
  354. {
  355. struct iommu *iommu;
  356. struct strbuf *strbuf;
  357. iopte_t *base;
  358. unsigned long flags, npages, ctx, i;
  359. if (unlikely(direction == DMA_NONE)) {
  360. if (printk_ratelimit())
  361. WARN_ON(1);
  362. return;
  363. }
  364. iommu = dev->archdata.iommu;
  365. strbuf = dev->archdata.stc;
  366. npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
  367. npages >>= IO_PAGE_SHIFT;
  368. base = iommu->page_table +
  369. ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
  370. bus_addr &= IO_PAGE_MASK;
  371. spin_lock_irqsave(&iommu->lock, flags);
  372. /* Record the context, if any. */
  373. ctx = 0;
  374. if (iommu->iommu_ctxflush)
  375. ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
  376. /* Step 1: Kick data out of streaming buffers if necessary. */
  377. if (strbuf->strbuf_enabled)
  378. strbuf_flush(strbuf, iommu, bus_addr, ctx,
  379. npages, direction);
  380. /* Step 2: Clear out TSB entries. */
  381. for (i = 0; i < npages; i++)
  382. iopte_make_dummy(iommu, base + i);
  383. free_npages(iommu, bus_addr - iommu->page_table_map_base, npages);
  384. iommu_free_ctx(iommu, ctx);
  385. spin_unlock_irqrestore(&iommu->lock, flags);
  386. }
  387. #define SG_ENT_PHYS_ADDRESS(SG) (__pa(sg_virt((SG))))
  388. static void fill_sg(iopte_t *iopte, struct scatterlist *sg,
  389. int nused, int nelems,
  390. unsigned long iopte_protection)
  391. {
  392. struct scatterlist *dma_sg = sg;
  393. int i;
  394. for (i = 0; i < nused; i++) {
  395. unsigned long pteval = ~0UL;
  396. u32 dma_npages;
  397. dma_npages = ((dma_sg->dma_address & (IO_PAGE_SIZE - 1UL)) +
  398. dma_sg->dma_length +
  399. ((IO_PAGE_SIZE - 1UL))) >> IO_PAGE_SHIFT;
  400. do {
  401. unsigned long offset;
  402. signed int len;
  403. /* If we are here, we know we have at least one
  404. * more page to map. So walk forward until we
  405. * hit a page crossing, and begin creating new
  406. * mappings from that spot.
  407. */
  408. for (;;) {
  409. unsigned long tmp;
  410. tmp = SG_ENT_PHYS_ADDRESS(sg);
  411. len = sg->length;
  412. if (((tmp ^ pteval) >> IO_PAGE_SHIFT) != 0UL) {
  413. pteval = tmp & IO_PAGE_MASK;
  414. offset = tmp & (IO_PAGE_SIZE - 1UL);
  415. break;
  416. }
  417. if (((tmp ^ (tmp + len - 1UL)) >> IO_PAGE_SHIFT) != 0UL) {
  418. pteval = (tmp + IO_PAGE_SIZE) & IO_PAGE_MASK;
  419. offset = 0UL;
  420. len -= (IO_PAGE_SIZE - (tmp & (IO_PAGE_SIZE - 1UL)));
  421. break;
  422. }
  423. sg = sg_next(sg);
  424. nelems--;
  425. }
  426. pteval = iopte_protection | (pteval & IOPTE_PAGE);
  427. while (len > 0) {
  428. *iopte++ = __iopte(pteval);
  429. pteval += IO_PAGE_SIZE;
  430. len -= (IO_PAGE_SIZE - offset);
  431. offset = 0;
  432. dma_npages--;
  433. }
  434. pteval = (pteval & IOPTE_PAGE) + len;
  435. sg = sg_next(sg);
  436. nelems--;
  437. /* Skip over any tail mappings we've fully mapped,
  438. * adjusting pteval along the way. Stop when we
  439. * detect a page crossing event.
  440. */
  441. while (nelems &&
  442. (pteval << (64 - IO_PAGE_SHIFT)) != 0UL &&
  443. (pteval == SG_ENT_PHYS_ADDRESS(sg)) &&
  444. ((pteval ^
  445. (SG_ENT_PHYS_ADDRESS(sg) + sg->length - 1UL)) >> IO_PAGE_SHIFT) == 0UL) {
  446. pteval += sg->length;
  447. sg = sg_next(sg);
  448. nelems--;
  449. }
  450. if ((pteval << (64 - IO_PAGE_SHIFT)) == 0UL)
  451. pteval = ~0UL;
  452. } while (dma_npages != 0);
  453. dma_sg = sg_next(dma_sg);
  454. }
  455. }
  456. static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist,
  457. int nelems, enum dma_data_direction direction)
  458. {
  459. struct iommu *iommu;
  460. struct strbuf *strbuf;
  461. unsigned long flags, ctx, npages, iopte_protection;
  462. iopte_t *base;
  463. u32 dma_base;
  464. struct scatterlist *sgtmp;
  465. int used;
  466. /* Fast path single entry scatterlists. */
  467. if (nelems == 1) {
  468. sglist->dma_address =
  469. dma_4u_map_single(dev, sg_virt(sglist),
  470. sglist->length, direction);
  471. if (unlikely(sglist->dma_address == DMA_ERROR_CODE))
  472. return 0;
  473. sglist->dma_length = sglist->length;
  474. return 1;
  475. }
  476. iommu = dev->archdata.iommu;
  477. strbuf = dev->archdata.stc;
  478. if (unlikely(direction == DMA_NONE))
  479. goto bad_no_ctx;
  480. /* Step 1: Prepare scatter list. */
  481. npages = prepare_sg(sglist, nelems);
  482. /* Step 2: Allocate a cluster and context, if necessary. */
  483. spin_lock_irqsave(&iommu->lock, flags);
  484. base = alloc_npages(iommu, npages);
  485. ctx = 0;
  486. if (iommu->iommu_ctxflush)
  487. ctx = iommu_alloc_ctx(iommu);
  488. spin_unlock_irqrestore(&iommu->lock, flags);
  489. if (base == NULL)
  490. goto bad;
  491. dma_base = iommu->page_table_map_base +
  492. ((base - iommu->page_table) << IO_PAGE_SHIFT);
  493. /* Step 3: Normalize DMA addresses. */
  494. used = nelems;
  495. sgtmp = sglist;
  496. while (used && sgtmp->dma_length) {
  497. sgtmp->dma_address += dma_base;
  498. sgtmp = sg_next(sgtmp);
  499. used--;
  500. }
  501. used = nelems - used;
  502. /* Step 4: Create the mappings. */
  503. if (strbuf->strbuf_enabled)
  504. iopte_protection = IOPTE_STREAMING(ctx);
  505. else
  506. iopte_protection = IOPTE_CONSISTENT(ctx);
  507. if (direction != DMA_TO_DEVICE)
  508. iopte_protection |= IOPTE_WRITE;
  509. fill_sg(base, sglist, used, nelems, iopte_protection);
  510. #ifdef VERIFY_SG
  511. verify_sglist(sglist, nelems, base, npages);
  512. #endif
  513. return used;
  514. bad:
  515. iommu_free_ctx(iommu, ctx);
  516. bad_no_ctx:
  517. if (printk_ratelimit())
  518. WARN_ON(1);
  519. return 0;
  520. }
  521. static void dma_4u_unmap_sg(struct device *dev, struct scatterlist *sglist,
  522. int nelems, enum dma_data_direction direction)
  523. {
  524. struct iommu *iommu;
  525. struct strbuf *strbuf;
  526. iopte_t *base;
  527. unsigned long flags, ctx, i, npages;
  528. struct scatterlist *sg, *sgprv;
  529. u32 bus_addr;
  530. if (unlikely(direction == DMA_NONE)) {
  531. if (printk_ratelimit())
  532. WARN_ON(1);
  533. }
  534. iommu = dev->archdata.iommu;
  535. strbuf = dev->archdata.stc;
  536. bus_addr = sglist->dma_address & IO_PAGE_MASK;
  537. sgprv = NULL;
  538. for_each_sg(sglist, sg, nelems, i) {
  539. if (sg->dma_length == 0)
  540. break;
  541. sgprv = sg;
  542. }
  543. npages = (IO_PAGE_ALIGN(sgprv->dma_address + sgprv->dma_length) -
  544. bus_addr) >> IO_PAGE_SHIFT;
  545. base = iommu->page_table +
  546. ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
  547. spin_lock_irqsave(&iommu->lock, flags);
  548. /* Record the context, if any. */
  549. ctx = 0;
  550. if (iommu->iommu_ctxflush)
  551. ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
  552. /* Step 1: Kick data out of streaming buffers if necessary. */
  553. if (strbuf->strbuf_enabled)
  554. strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
  555. /* Step 2: Clear out the TSB entries. */
  556. for (i = 0; i < npages; i++)
  557. iopte_make_dummy(iommu, base + i);
  558. free_npages(iommu, bus_addr - iommu->page_table_map_base, npages);
  559. iommu_free_ctx(iommu, ctx);
  560. spin_unlock_irqrestore(&iommu->lock, flags);
  561. }
  562. static void dma_4u_sync_single_for_cpu(struct device *dev,
  563. dma_addr_t bus_addr, size_t sz,
  564. enum dma_data_direction direction)
  565. {
  566. struct iommu *iommu;
  567. struct strbuf *strbuf;
  568. unsigned long flags, ctx, npages;
  569. iommu = dev->archdata.iommu;
  570. strbuf = dev->archdata.stc;
  571. if (!strbuf->strbuf_enabled)
  572. return;
  573. spin_lock_irqsave(&iommu->lock, flags);
  574. npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
  575. npages >>= IO_PAGE_SHIFT;
  576. bus_addr &= IO_PAGE_MASK;
  577. /* Step 1: Record the context, if any. */
  578. ctx = 0;
  579. if (iommu->iommu_ctxflush &&
  580. strbuf->strbuf_ctxflush) {
  581. iopte_t *iopte;
  582. iopte = iommu->page_table +
  583. ((bus_addr - iommu->page_table_map_base)>>IO_PAGE_SHIFT);
  584. ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
  585. }
  586. /* Step 2: Kick data out of streaming buffers. */
  587. strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
  588. spin_unlock_irqrestore(&iommu->lock, flags);
  589. }
  590. static void dma_4u_sync_sg_for_cpu(struct device *dev,
  591. struct scatterlist *sglist, int nelems,
  592. enum dma_data_direction direction)
  593. {
  594. struct iommu *iommu;
  595. struct strbuf *strbuf;
  596. unsigned long flags, ctx, npages, i;
  597. struct scatterlist *sg, *sgprv;
  598. u32 bus_addr;
  599. iommu = dev->archdata.iommu;
  600. strbuf = dev->archdata.stc;
  601. if (!strbuf->strbuf_enabled)
  602. return;
  603. spin_lock_irqsave(&iommu->lock, flags);
  604. /* Step 1: Record the context, if any. */
  605. ctx = 0;
  606. if (iommu->iommu_ctxflush &&
  607. strbuf->strbuf_ctxflush) {
  608. iopte_t *iopte;
  609. iopte = iommu->page_table +
  610. ((sglist[0].dma_address - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
  611. ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
  612. }
  613. /* Step 2: Kick data out of streaming buffers. */
  614. bus_addr = sglist[0].dma_address & IO_PAGE_MASK;
  615. sgprv = NULL;
  616. for_each_sg(sglist, sg, nelems, i) {
  617. if (sg->dma_length == 0)
  618. break;
  619. sgprv = sg;
  620. }
  621. npages = (IO_PAGE_ALIGN(sgprv->dma_address + sgprv->dma_length)
  622. - bus_addr) >> IO_PAGE_SHIFT;
  623. strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
  624. spin_unlock_irqrestore(&iommu->lock, flags);
  625. }
  626. const struct dma_ops sun4u_dma_ops = {
  627. .alloc_coherent = dma_4u_alloc_coherent,
  628. .free_coherent = dma_4u_free_coherent,
  629. .map_single = dma_4u_map_single,
  630. .unmap_single = dma_4u_unmap_single,
  631. .map_sg = dma_4u_map_sg,
  632. .unmap_sg = dma_4u_unmap_sg,
  633. .sync_single_for_cpu = dma_4u_sync_single_for_cpu,
  634. .sync_sg_for_cpu = dma_4u_sync_sg_for_cpu,
  635. };
  636. const struct dma_ops *dma_ops = &sun4u_dma_ops;
  637. EXPORT_SYMBOL(dma_ops);
  638. int dma_supported(struct device *dev, u64 device_mask)
  639. {
  640. struct iommu *iommu = dev->archdata.iommu;
  641. u64 dma_addr_mask = iommu->dma_addr_mask;
  642. if (device_mask >= (1UL << 32UL))
  643. return 0;
  644. if ((device_mask & dma_addr_mask) == dma_addr_mask)
  645. return 1;
  646. #ifdef CONFIG_PCI
  647. if (dev->bus == &pci_bus_type)
  648. return pci_dma_supported(to_pci_dev(dev), device_mask);
  649. #endif
  650. return 0;
  651. }
  652. EXPORT_SYMBOL(dma_supported);
  653. int dma_set_mask(struct device *dev, u64 dma_mask)
  654. {
  655. #ifdef CONFIG_PCI
  656. if (dev->bus == &pci_bus_type)
  657. return pci_set_dma_mask(to_pci_dev(dev), dma_mask);
  658. #endif
  659. return -EINVAL;
  660. }
  661. EXPORT_SYMBOL(dma_set_mask);