resource_tracker.c 85 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies.
  4. * All rights reserved.
  5. * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
  6. *
  7. * This software is available to you under a choice of one of two
  8. * licenses. You may choose to be licensed under the terms of the GNU
  9. * General Public License (GPL) Version 2, available from the file
  10. * COPYING in the main directory of this source tree, or the
  11. * OpenIB.org BSD license below:
  12. *
  13. * Redistribution and use in source and binary forms, with or
  14. * without modification, are permitted provided that the following
  15. * conditions are met:
  16. *
  17. * - Redistributions of source code must retain the above
  18. * copyright notice, this list of conditions and the following
  19. * disclaimer.
  20. *
  21. * - Redistributions in binary form must reproduce the above
  22. * copyright notice, this list of conditions and the following
  23. * disclaimer in the documentation and/or other materials
  24. * provided with the distribution.
  25. *
  26. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33. * SOFTWARE.
  34. */
  35. #include <linux/sched.h>
  36. #include <linux/pci.h>
  37. #include <linux/errno.h>
  38. #include <linux/kernel.h>
  39. #include <linux/io.h>
  40. #include <linux/slab.h>
  41. #include <linux/mlx4/cmd.h>
  42. #include <linux/mlx4/qp.h>
  43. #include <linux/if_ether.h>
  44. #include <linux/etherdevice.h>
  45. #include "mlx4.h"
  46. #include "fw.h"
  47. #define MLX4_MAC_VALID (1ull << 63)
  48. struct mac_res {
  49. struct list_head list;
  50. u64 mac;
  51. u8 port;
  52. };
  53. struct res_common {
  54. struct list_head list;
  55. struct rb_node node;
  56. u64 res_id;
  57. int owner;
  58. int state;
  59. int from_state;
  60. int to_state;
  61. int removing;
  62. };
  63. enum {
  64. RES_ANY_BUSY = 1
  65. };
  66. struct res_gid {
  67. struct list_head list;
  68. u8 gid[16];
  69. enum mlx4_protocol prot;
  70. enum mlx4_steer_type steer;
  71. };
  72. enum res_qp_states {
  73. RES_QP_BUSY = RES_ANY_BUSY,
  74. /* QP number was allocated */
  75. RES_QP_RESERVED,
  76. /* ICM memory for QP context was mapped */
  77. RES_QP_MAPPED,
  78. /* QP is in hw ownership */
  79. RES_QP_HW
  80. };
  81. struct res_qp {
  82. struct res_common com;
  83. struct res_mtt *mtt;
  84. struct res_cq *rcq;
  85. struct res_cq *scq;
  86. struct res_srq *srq;
  87. struct list_head mcg_list;
  88. spinlock_t mcg_spl;
  89. int local_qpn;
  90. };
  91. enum res_mtt_states {
  92. RES_MTT_BUSY = RES_ANY_BUSY,
  93. RES_MTT_ALLOCATED,
  94. };
  95. static inline const char *mtt_states_str(enum res_mtt_states state)
  96. {
  97. switch (state) {
  98. case RES_MTT_BUSY: return "RES_MTT_BUSY";
  99. case RES_MTT_ALLOCATED: return "RES_MTT_ALLOCATED";
  100. default: return "Unknown";
  101. }
  102. }
  103. struct res_mtt {
  104. struct res_common com;
  105. int order;
  106. atomic_t ref_count;
  107. };
  108. enum res_mpt_states {
  109. RES_MPT_BUSY = RES_ANY_BUSY,
  110. RES_MPT_RESERVED,
  111. RES_MPT_MAPPED,
  112. RES_MPT_HW,
  113. };
  114. struct res_mpt {
  115. struct res_common com;
  116. struct res_mtt *mtt;
  117. int key;
  118. };
  119. enum res_eq_states {
  120. RES_EQ_BUSY = RES_ANY_BUSY,
  121. RES_EQ_RESERVED,
  122. RES_EQ_HW,
  123. };
  124. struct res_eq {
  125. struct res_common com;
  126. struct res_mtt *mtt;
  127. };
  128. enum res_cq_states {
  129. RES_CQ_BUSY = RES_ANY_BUSY,
  130. RES_CQ_ALLOCATED,
  131. RES_CQ_HW,
  132. };
  133. struct res_cq {
  134. struct res_common com;
  135. struct res_mtt *mtt;
  136. atomic_t ref_count;
  137. };
  138. enum res_srq_states {
  139. RES_SRQ_BUSY = RES_ANY_BUSY,
  140. RES_SRQ_ALLOCATED,
  141. RES_SRQ_HW,
  142. };
  143. struct res_srq {
  144. struct res_common com;
  145. struct res_mtt *mtt;
  146. struct res_cq *cq;
  147. atomic_t ref_count;
  148. };
  149. enum res_counter_states {
  150. RES_COUNTER_BUSY = RES_ANY_BUSY,
  151. RES_COUNTER_ALLOCATED,
  152. };
  153. struct res_counter {
  154. struct res_common com;
  155. int port;
  156. };
  157. enum res_xrcdn_states {
  158. RES_XRCD_BUSY = RES_ANY_BUSY,
  159. RES_XRCD_ALLOCATED,
  160. };
  161. struct res_xrcdn {
  162. struct res_common com;
  163. int port;
  164. };
  165. enum res_fs_rule_states {
  166. RES_FS_RULE_BUSY = RES_ANY_BUSY,
  167. RES_FS_RULE_ALLOCATED,
  168. };
  169. struct res_fs_rule {
  170. struct res_common com;
  171. };
  172. static void *res_tracker_lookup(struct rb_root *root, u64 res_id)
  173. {
  174. struct rb_node *node = root->rb_node;
  175. while (node) {
  176. struct res_common *res = container_of(node, struct res_common,
  177. node);
  178. if (res_id < res->res_id)
  179. node = node->rb_left;
  180. else if (res_id > res->res_id)
  181. node = node->rb_right;
  182. else
  183. return res;
  184. }
  185. return NULL;
  186. }
  187. static int res_tracker_insert(struct rb_root *root, struct res_common *res)
  188. {
  189. struct rb_node **new = &(root->rb_node), *parent = NULL;
  190. /* Figure out where to put new node */
  191. while (*new) {
  192. struct res_common *this = container_of(*new, struct res_common,
  193. node);
  194. parent = *new;
  195. if (res->res_id < this->res_id)
  196. new = &((*new)->rb_left);
  197. else if (res->res_id > this->res_id)
  198. new = &((*new)->rb_right);
  199. else
  200. return -EEXIST;
  201. }
  202. /* Add new node and rebalance tree. */
  203. rb_link_node(&res->node, parent, new);
  204. rb_insert_color(&res->node, root);
  205. return 0;
  206. }
  207. enum qp_transition {
  208. QP_TRANS_INIT2RTR,
  209. QP_TRANS_RTR2RTS,
  210. QP_TRANS_RTS2RTS,
  211. QP_TRANS_SQERR2RTS,
  212. QP_TRANS_SQD2SQD,
  213. QP_TRANS_SQD2RTS
  214. };
  215. /* For Debug uses */
  216. static const char *ResourceType(enum mlx4_resource rt)
  217. {
  218. switch (rt) {
  219. case RES_QP: return "RES_QP";
  220. case RES_CQ: return "RES_CQ";
  221. case RES_SRQ: return "RES_SRQ";
  222. case RES_MPT: return "RES_MPT";
  223. case RES_MTT: return "RES_MTT";
  224. case RES_MAC: return "RES_MAC";
  225. case RES_EQ: return "RES_EQ";
  226. case RES_COUNTER: return "RES_COUNTER";
  227. case RES_FS_RULE: return "RES_FS_RULE";
  228. case RES_XRCD: return "RES_XRCD";
  229. default: return "Unknown resource type !!!";
  230. };
  231. }
  232. int mlx4_init_resource_tracker(struct mlx4_dev *dev)
  233. {
  234. struct mlx4_priv *priv = mlx4_priv(dev);
  235. int i;
  236. int t;
  237. priv->mfunc.master.res_tracker.slave_list =
  238. kzalloc(dev->num_slaves * sizeof(struct slave_list),
  239. GFP_KERNEL);
  240. if (!priv->mfunc.master.res_tracker.slave_list)
  241. return -ENOMEM;
  242. for (i = 0 ; i < dev->num_slaves; i++) {
  243. for (t = 0; t < MLX4_NUM_OF_RESOURCE_TYPE; ++t)
  244. INIT_LIST_HEAD(&priv->mfunc.master.res_tracker.
  245. slave_list[i].res_list[t]);
  246. mutex_init(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
  247. }
  248. mlx4_dbg(dev, "Started init_resource_tracker: %ld slaves\n",
  249. dev->num_slaves);
  250. for (i = 0 ; i < MLX4_NUM_OF_RESOURCE_TYPE; i++)
  251. priv->mfunc.master.res_tracker.res_tree[i] = RB_ROOT;
  252. spin_lock_init(&priv->mfunc.master.res_tracker.lock);
  253. return 0 ;
  254. }
  255. void mlx4_free_resource_tracker(struct mlx4_dev *dev,
  256. enum mlx4_res_tracker_free_type type)
  257. {
  258. struct mlx4_priv *priv = mlx4_priv(dev);
  259. int i;
  260. if (priv->mfunc.master.res_tracker.slave_list) {
  261. if (type != RES_TR_FREE_STRUCTS_ONLY)
  262. for (i = 0 ; i < dev->num_slaves; i++)
  263. if (type == RES_TR_FREE_ALL ||
  264. dev->caps.function != i)
  265. mlx4_delete_all_resources_for_slave(dev, i);
  266. if (type != RES_TR_FREE_SLAVES_ONLY) {
  267. kfree(priv->mfunc.master.res_tracker.slave_list);
  268. priv->mfunc.master.res_tracker.slave_list = NULL;
  269. }
  270. }
  271. }
  272. static void update_pkey_index(struct mlx4_dev *dev, int slave,
  273. struct mlx4_cmd_mailbox *inbox)
  274. {
  275. u8 sched = *(u8 *)(inbox->buf + 64);
  276. u8 orig_index = *(u8 *)(inbox->buf + 35);
  277. u8 new_index;
  278. struct mlx4_priv *priv = mlx4_priv(dev);
  279. int port;
  280. port = (sched >> 6 & 1) + 1;
  281. new_index = priv->virt2phys_pkey[slave][port - 1][orig_index];
  282. *(u8 *)(inbox->buf + 35) = new_index;
  283. }
  284. static void update_gid(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *inbox,
  285. u8 slave)
  286. {
  287. struct mlx4_qp_context *qp_ctx = inbox->buf + 8;
  288. enum mlx4_qp_optpar optpar = be32_to_cpu(*(__be32 *) inbox->buf);
  289. u32 ts = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
  290. if (MLX4_QP_ST_UD == ts)
  291. qp_ctx->pri_path.mgid_index = 0x80 | slave;
  292. if (MLX4_QP_ST_RC == ts || MLX4_QP_ST_UC == ts) {
  293. if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH)
  294. qp_ctx->pri_path.mgid_index = slave & 0x7F;
  295. if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH)
  296. qp_ctx->alt_path.mgid_index = slave & 0x7F;
  297. }
  298. }
  299. static int mpt_mask(struct mlx4_dev *dev)
  300. {
  301. return dev->caps.num_mpts - 1;
  302. }
  303. static void *find_res(struct mlx4_dev *dev, int res_id,
  304. enum mlx4_resource type)
  305. {
  306. struct mlx4_priv *priv = mlx4_priv(dev);
  307. return res_tracker_lookup(&priv->mfunc.master.res_tracker.res_tree[type],
  308. res_id);
  309. }
  310. static int get_res(struct mlx4_dev *dev, int slave, u64 res_id,
  311. enum mlx4_resource type,
  312. void *res)
  313. {
  314. struct res_common *r;
  315. int err = 0;
  316. spin_lock_irq(mlx4_tlock(dev));
  317. r = find_res(dev, res_id, type);
  318. if (!r) {
  319. err = -ENONET;
  320. goto exit;
  321. }
  322. if (r->state == RES_ANY_BUSY) {
  323. err = -EBUSY;
  324. goto exit;
  325. }
  326. if (r->owner != slave) {
  327. err = -EPERM;
  328. goto exit;
  329. }
  330. r->from_state = r->state;
  331. r->state = RES_ANY_BUSY;
  332. if (res)
  333. *((struct res_common **)res) = r;
  334. exit:
  335. spin_unlock_irq(mlx4_tlock(dev));
  336. return err;
  337. }
  338. int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
  339. enum mlx4_resource type,
  340. u64 res_id, int *slave)
  341. {
  342. struct res_common *r;
  343. int err = -ENOENT;
  344. int id = res_id;
  345. if (type == RES_QP)
  346. id &= 0x7fffff;
  347. spin_lock(mlx4_tlock(dev));
  348. r = find_res(dev, id, type);
  349. if (r) {
  350. *slave = r->owner;
  351. err = 0;
  352. }
  353. spin_unlock(mlx4_tlock(dev));
  354. return err;
  355. }
  356. static void put_res(struct mlx4_dev *dev, int slave, u64 res_id,
  357. enum mlx4_resource type)
  358. {
  359. struct res_common *r;
  360. spin_lock_irq(mlx4_tlock(dev));
  361. r = find_res(dev, res_id, type);
  362. if (r)
  363. r->state = r->from_state;
  364. spin_unlock_irq(mlx4_tlock(dev));
  365. }
  366. static struct res_common *alloc_qp_tr(int id)
  367. {
  368. struct res_qp *ret;
  369. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  370. if (!ret)
  371. return NULL;
  372. ret->com.res_id = id;
  373. ret->com.state = RES_QP_RESERVED;
  374. ret->local_qpn = id;
  375. INIT_LIST_HEAD(&ret->mcg_list);
  376. spin_lock_init(&ret->mcg_spl);
  377. return &ret->com;
  378. }
  379. static struct res_common *alloc_mtt_tr(int id, int order)
  380. {
  381. struct res_mtt *ret;
  382. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  383. if (!ret)
  384. return NULL;
  385. ret->com.res_id = id;
  386. ret->order = order;
  387. ret->com.state = RES_MTT_ALLOCATED;
  388. atomic_set(&ret->ref_count, 0);
  389. return &ret->com;
  390. }
  391. static struct res_common *alloc_mpt_tr(int id, int key)
  392. {
  393. struct res_mpt *ret;
  394. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  395. if (!ret)
  396. return NULL;
  397. ret->com.res_id = id;
  398. ret->com.state = RES_MPT_RESERVED;
  399. ret->key = key;
  400. return &ret->com;
  401. }
  402. static struct res_common *alloc_eq_tr(int id)
  403. {
  404. struct res_eq *ret;
  405. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  406. if (!ret)
  407. return NULL;
  408. ret->com.res_id = id;
  409. ret->com.state = RES_EQ_RESERVED;
  410. return &ret->com;
  411. }
  412. static struct res_common *alloc_cq_tr(int id)
  413. {
  414. struct res_cq *ret;
  415. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  416. if (!ret)
  417. return NULL;
  418. ret->com.res_id = id;
  419. ret->com.state = RES_CQ_ALLOCATED;
  420. atomic_set(&ret->ref_count, 0);
  421. return &ret->com;
  422. }
  423. static struct res_common *alloc_srq_tr(int id)
  424. {
  425. struct res_srq *ret;
  426. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  427. if (!ret)
  428. return NULL;
  429. ret->com.res_id = id;
  430. ret->com.state = RES_SRQ_ALLOCATED;
  431. atomic_set(&ret->ref_count, 0);
  432. return &ret->com;
  433. }
  434. static struct res_common *alloc_counter_tr(int id)
  435. {
  436. struct res_counter *ret;
  437. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  438. if (!ret)
  439. return NULL;
  440. ret->com.res_id = id;
  441. ret->com.state = RES_COUNTER_ALLOCATED;
  442. return &ret->com;
  443. }
  444. static struct res_common *alloc_xrcdn_tr(int id)
  445. {
  446. struct res_xrcdn *ret;
  447. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  448. if (!ret)
  449. return NULL;
  450. ret->com.res_id = id;
  451. ret->com.state = RES_XRCD_ALLOCATED;
  452. return &ret->com;
  453. }
  454. static struct res_common *alloc_fs_rule_tr(u64 id)
  455. {
  456. struct res_fs_rule *ret;
  457. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  458. if (!ret)
  459. return NULL;
  460. ret->com.res_id = id;
  461. ret->com.state = RES_FS_RULE_ALLOCATED;
  462. return &ret->com;
  463. }
  464. static struct res_common *alloc_tr(u64 id, enum mlx4_resource type, int slave,
  465. int extra)
  466. {
  467. struct res_common *ret;
  468. switch (type) {
  469. case RES_QP:
  470. ret = alloc_qp_tr(id);
  471. break;
  472. case RES_MPT:
  473. ret = alloc_mpt_tr(id, extra);
  474. break;
  475. case RES_MTT:
  476. ret = alloc_mtt_tr(id, extra);
  477. break;
  478. case RES_EQ:
  479. ret = alloc_eq_tr(id);
  480. break;
  481. case RES_CQ:
  482. ret = alloc_cq_tr(id);
  483. break;
  484. case RES_SRQ:
  485. ret = alloc_srq_tr(id);
  486. break;
  487. case RES_MAC:
  488. printk(KERN_ERR "implementation missing\n");
  489. return NULL;
  490. case RES_COUNTER:
  491. ret = alloc_counter_tr(id);
  492. break;
  493. case RES_XRCD:
  494. ret = alloc_xrcdn_tr(id);
  495. break;
  496. case RES_FS_RULE:
  497. ret = alloc_fs_rule_tr(id);
  498. break;
  499. default:
  500. return NULL;
  501. }
  502. if (ret)
  503. ret->owner = slave;
  504. return ret;
  505. }
  506. static int add_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
  507. enum mlx4_resource type, int extra)
  508. {
  509. int i;
  510. int err;
  511. struct mlx4_priv *priv = mlx4_priv(dev);
  512. struct res_common **res_arr;
  513. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  514. struct rb_root *root = &tracker->res_tree[type];
  515. res_arr = kzalloc(count * sizeof *res_arr, GFP_KERNEL);
  516. if (!res_arr)
  517. return -ENOMEM;
  518. for (i = 0; i < count; ++i) {
  519. res_arr[i] = alloc_tr(base + i, type, slave, extra);
  520. if (!res_arr[i]) {
  521. for (--i; i >= 0; --i)
  522. kfree(res_arr[i]);
  523. kfree(res_arr);
  524. return -ENOMEM;
  525. }
  526. }
  527. spin_lock_irq(mlx4_tlock(dev));
  528. for (i = 0; i < count; ++i) {
  529. if (find_res(dev, base + i, type)) {
  530. err = -EEXIST;
  531. goto undo;
  532. }
  533. err = res_tracker_insert(root, res_arr[i]);
  534. if (err)
  535. goto undo;
  536. list_add_tail(&res_arr[i]->list,
  537. &tracker->slave_list[slave].res_list[type]);
  538. }
  539. spin_unlock_irq(mlx4_tlock(dev));
  540. kfree(res_arr);
  541. return 0;
  542. undo:
  543. for (--i; i >= base; --i)
  544. rb_erase(&res_arr[i]->node, root);
  545. spin_unlock_irq(mlx4_tlock(dev));
  546. for (i = 0; i < count; ++i)
  547. kfree(res_arr[i]);
  548. kfree(res_arr);
  549. return err;
  550. }
  551. static int remove_qp_ok(struct res_qp *res)
  552. {
  553. if (res->com.state == RES_QP_BUSY)
  554. return -EBUSY;
  555. else if (res->com.state != RES_QP_RESERVED)
  556. return -EPERM;
  557. return 0;
  558. }
  559. static int remove_mtt_ok(struct res_mtt *res, int order)
  560. {
  561. if (res->com.state == RES_MTT_BUSY ||
  562. atomic_read(&res->ref_count)) {
  563. printk(KERN_DEBUG "%s-%d: state %s, ref_count %d\n",
  564. __func__, __LINE__,
  565. mtt_states_str(res->com.state),
  566. atomic_read(&res->ref_count));
  567. return -EBUSY;
  568. } else if (res->com.state != RES_MTT_ALLOCATED)
  569. return -EPERM;
  570. else if (res->order != order)
  571. return -EINVAL;
  572. return 0;
  573. }
  574. static int remove_mpt_ok(struct res_mpt *res)
  575. {
  576. if (res->com.state == RES_MPT_BUSY)
  577. return -EBUSY;
  578. else if (res->com.state != RES_MPT_RESERVED)
  579. return -EPERM;
  580. return 0;
  581. }
  582. static int remove_eq_ok(struct res_eq *res)
  583. {
  584. if (res->com.state == RES_MPT_BUSY)
  585. return -EBUSY;
  586. else if (res->com.state != RES_MPT_RESERVED)
  587. return -EPERM;
  588. return 0;
  589. }
  590. static int remove_counter_ok(struct res_counter *res)
  591. {
  592. if (res->com.state == RES_COUNTER_BUSY)
  593. return -EBUSY;
  594. else if (res->com.state != RES_COUNTER_ALLOCATED)
  595. return -EPERM;
  596. return 0;
  597. }
  598. static int remove_xrcdn_ok(struct res_xrcdn *res)
  599. {
  600. if (res->com.state == RES_XRCD_BUSY)
  601. return -EBUSY;
  602. else if (res->com.state != RES_XRCD_ALLOCATED)
  603. return -EPERM;
  604. return 0;
  605. }
  606. static int remove_fs_rule_ok(struct res_fs_rule *res)
  607. {
  608. if (res->com.state == RES_FS_RULE_BUSY)
  609. return -EBUSY;
  610. else if (res->com.state != RES_FS_RULE_ALLOCATED)
  611. return -EPERM;
  612. return 0;
  613. }
  614. static int remove_cq_ok(struct res_cq *res)
  615. {
  616. if (res->com.state == RES_CQ_BUSY)
  617. return -EBUSY;
  618. else if (res->com.state != RES_CQ_ALLOCATED)
  619. return -EPERM;
  620. return 0;
  621. }
  622. static int remove_srq_ok(struct res_srq *res)
  623. {
  624. if (res->com.state == RES_SRQ_BUSY)
  625. return -EBUSY;
  626. else if (res->com.state != RES_SRQ_ALLOCATED)
  627. return -EPERM;
  628. return 0;
  629. }
  630. static int remove_ok(struct res_common *res, enum mlx4_resource type, int extra)
  631. {
  632. switch (type) {
  633. case RES_QP:
  634. return remove_qp_ok((struct res_qp *)res);
  635. case RES_CQ:
  636. return remove_cq_ok((struct res_cq *)res);
  637. case RES_SRQ:
  638. return remove_srq_ok((struct res_srq *)res);
  639. case RES_MPT:
  640. return remove_mpt_ok((struct res_mpt *)res);
  641. case RES_MTT:
  642. return remove_mtt_ok((struct res_mtt *)res, extra);
  643. case RES_MAC:
  644. return -ENOSYS;
  645. case RES_EQ:
  646. return remove_eq_ok((struct res_eq *)res);
  647. case RES_COUNTER:
  648. return remove_counter_ok((struct res_counter *)res);
  649. case RES_XRCD:
  650. return remove_xrcdn_ok((struct res_xrcdn *)res);
  651. case RES_FS_RULE:
  652. return remove_fs_rule_ok((struct res_fs_rule *)res);
  653. default:
  654. return -EINVAL;
  655. }
  656. }
  657. static int rem_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
  658. enum mlx4_resource type, int extra)
  659. {
  660. u64 i;
  661. int err;
  662. struct mlx4_priv *priv = mlx4_priv(dev);
  663. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  664. struct res_common *r;
  665. spin_lock_irq(mlx4_tlock(dev));
  666. for (i = base; i < base + count; ++i) {
  667. r = res_tracker_lookup(&tracker->res_tree[type], i);
  668. if (!r) {
  669. err = -ENOENT;
  670. goto out;
  671. }
  672. if (r->owner != slave) {
  673. err = -EPERM;
  674. goto out;
  675. }
  676. err = remove_ok(r, type, extra);
  677. if (err)
  678. goto out;
  679. }
  680. for (i = base; i < base + count; ++i) {
  681. r = res_tracker_lookup(&tracker->res_tree[type], i);
  682. rb_erase(&r->node, &tracker->res_tree[type]);
  683. list_del(&r->list);
  684. kfree(r);
  685. }
  686. err = 0;
  687. out:
  688. spin_unlock_irq(mlx4_tlock(dev));
  689. return err;
  690. }
  691. static int qp_res_start_move_to(struct mlx4_dev *dev, int slave, int qpn,
  692. enum res_qp_states state, struct res_qp **qp,
  693. int alloc)
  694. {
  695. struct mlx4_priv *priv = mlx4_priv(dev);
  696. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  697. struct res_qp *r;
  698. int err = 0;
  699. spin_lock_irq(mlx4_tlock(dev));
  700. r = res_tracker_lookup(&tracker->res_tree[RES_QP], qpn);
  701. if (!r)
  702. err = -ENOENT;
  703. else if (r->com.owner != slave)
  704. err = -EPERM;
  705. else {
  706. switch (state) {
  707. case RES_QP_BUSY:
  708. mlx4_dbg(dev, "%s: failed RES_QP, 0x%llx\n",
  709. __func__, r->com.res_id);
  710. err = -EBUSY;
  711. break;
  712. case RES_QP_RESERVED:
  713. if (r->com.state == RES_QP_MAPPED && !alloc)
  714. break;
  715. mlx4_dbg(dev, "failed RES_QP, 0x%llx\n", r->com.res_id);
  716. err = -EINVAL;
  717. break;
  718. case RES_QP_MAPPED:
  719. if ((r->com.state == RES_QP_RESERVED && alloc) ||
  720. r->com.state == RES_QP_HW)
  721. break;
  722. else {
  723. mlx4_dbg(dev, "failed RES_QP, 0x%llx\n",
  724. r->com.res_id);
  725. err = -EINVAL;
  726. }
  727. break;
  728. case RES_QP_HW:
  729. if (r->com.state != RES_QP_MAPPED)
  730. err = -EINVAL;
  731. break;
  732. default:
  733. err = -EINVAL;
  734. }
  735. if (!err) {
  736. r->com.from_state = r->com.state;
  737. r->com.to_state = state;
  738. r->com.state = RES_QP_BUSY;
  739. if (qp)
  740. *qp = r;
  741. }
  742. }
  743. spin_unlock_irq(mlx4_tlock(dev));
  744. return err;
  745. }
  746. static int mr_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  747. enum res_mpt_states state, struct res_mpt **mpt)
  748. {
  749. struct mlx4_priv *priv = mlx4_priv(dev);
  750. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  751. struct res_mpt *r;
  752. int err = 0;
  753. spin_lock_irq(mlx4_tlock(dev));
  754. r = res_tracker_lookup(&tracker->res_tree[RES_MPT], index);
  755. if (!r)
  756. err = -ENOENT;
  757. else if (r->com.owner != slave)
  758. err = -EPERM;
  759. else {
  760. switch (state) {
  761. case RES_MPT_BUSY:
  762. err = -EINVAL;
  763. break;
  764. case RES_MPT_RESERVED:
  765. if (r->com.state != RES_MPT_MAPPED)
  766. err = -EINVAL;
  767. break;
  768. case RES_MPT_MAPPED:
  769. if (r->com.state != RES_MPT_RESERVED &&
  770. r->com.state != RES_MPT_HW)
  771. err = -EINVAL;
  772. break;
  773. case RES_MPT_HW:
  774. if (r->com.state != RES_MPT_MAPPED)
  775. err = -EINVAL;
  776. break;
  777. default:
  778. err = -EINVAL;
  779. }
  780. if (!err) {
  781. r->com.from_state = r->com.state;
  782. r->com.to_state = state;
  783. r->com.state = RES_MPT_BUSY;
  784. if (mpt)
  785. *mpt = r;
  786. }
  787. }
  788. spin_unlock_irq(mlx4_tlock(dev));
  789. return err;
  790. }
  791. static int eq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  792. enum res_eq_states state, struct res_eq **eq)
  793. {
  794. struct mlx4_priv *priv = mlx4_priv(dev);
  795. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  796. struct res_eq *r;
  797. int err = 0;
  798. spin_lock_irq(mlx4_tlock(dev));
  799. r = res_tracker_lookup(&tracker->res_tree[RES_EQ], index);
  800. if (!r)
  801. err = -ENOENT;
  802. else if (r->com.owner != slave)
  803. err = -EPERM;
  804. else {
  805. switch (state) {
  806. case RES_EQ_BUSY:
  807. err = -EINVAL;
  808. break;
  809. case RES_EQ_RESERVED:
  810. if (r->com.state != RES_EQ_HW)
  811. err = -EINVAL;
  812. break;
  813. case RES_EQ_HW:
  814. if (r->com.state != RES_EQ_RESERVED)
  815. err = -EINVAL;
  816. break;
  817. default:
  818. err = -EINVAL;
  819. }
  820. if (!err) {
  821. r->com.from_state = r->com.state;
  822. r->com.to_state = state;
  823. r->com.state = RES_EQ_BUSY;
  824. if (eq)
  825. *eq = r;
  826. }
  827. }
  828. spin_unlock_irq(mlx4_tlock(dev));
  829. return err;
  830. }
  831. static int cq_res_start_move_to(struct mlx4_dev *dev, int slave, int cqn,
  832. enum res_cq_states state, struct res_cq **cq)
  833. {
  834. struct mlx4_priv *priv = mlx4_priv(dev);
  835. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  836. struct res_cq *r;
  837. int err;
  838. spin_lock_irq(mlx4_tlock(dev));
  839. r = res_tracker_lookup(&tracker->res_tree[RES_CQ], cqn);
  840. if (!r)
  841. err = -ENOENT;
  842. else if (r->com.owner != slave)
  843. err = -EPERM;
  844. else {
  845. switch (state) {
  846. case RES_CQ_BUSY:
  847. err = -EBUSY;
  848. break;
  849. case RES_CQ_ALLOCATED:
  850. if (r->com.state != RES_CQ_HW)
  851. err = -EINVAL;
  852. else if (atomic_read(&r->ref_count))
  853. err = -EBUSY;
  854. else
  855. err = 0;
  856. break;
  857. case RES_CQ_HW:
  858. if (r->com.state != RES_CQ_ALLOCATED)
  859. err = -EINVAL;
  860. else
  861. err = 0;
  862. break;
  863. default:
  864. err = -EINVAL;
  865. }
  866. if (!err) {
  867. r->com.from_state = r->com.state;
  868. r->com.to_state = state;
  869. r->com.state = RES_CQ_BUSY;
  870. if (cq)
  871. *cq = r;
  872. }
  873. }
  874. spin_unlock_irq(mlx4_tlock(dev));
  875. return err;
  876. }
  877. static int srq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  878. enum res_cq_states state, struct res_srq **srq)
  879. {
  880. struct mlx4_priv *priv = mlx4_priv(dev);
  881. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  882. struct res_srq *r;
  883. int err = 0;
  884. spin_lock_irq(mlx4_tlock(dev));
  885. r = res_tracker_lookup(&tracker->res_tree[RES_SRQ], index);
  886. if (!r)
  887. err = -ENOENT;
  888. else if (r->com.owner != slave)
  889. err = -EPERM;
  890. else {
  891. switch (state) {
  892. case RES_SRQ_BUSY:
  893. err = -EINVAL;
  894. break;
  895. case RES_SRQ_ALLOCATED:
  896. if (r->com.state != RES_SRQ_HW)
  897. err = -EINVAL;
  898. else if (atomic_read(&r->ref_count))
  899. err = -EBUSY;
  900. break;
  901. case RES_SRQ_HW:
  902. if (r->com.state != RES_SRQ_ALLOCATED)
  903. err = -EINVAL;
  904. break;
  905. default:
  906. err = -EINVAL;
  907. }
  908. if (!err) {
  909. r->com.from_state = r->com.state;
  910. r->com.to_state = state;
  911. r->com.state = RES_SRQ_BUSY;
  912. if (srq)
  913. *srq = r;
  914. }
  915. }
  916. spin_unlock_irq(mlx4_tlock(dev));
  917. return err;
  918. }
  919. static void res_abort_move(struct mlx4_dev *dev, int slave,
  920. enum mlx4_resource type, int id)
  921. {
  922. struct mlx4_priv *priv = mlx4_priv(dev);
  923. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  924. struct res_common *r;
  925. spin_lock_irq(mlx4_tlock(dev));
  926. r = res_tracker_lookup(&tracker->res_tree[type], id);
  927. if (r && (r->owner == slave))
  928. r->state = r->from_state;
  929. spin_unlock_irq(mlx4_tlock(dev));
  930. }
  931. static void res_end_move(struct mlx4_dev *dev, int slave,
  932. enum mlx4_resource type, int id)
  933. {
  934. struct mlx4_priv *priv = mlx4_priv(dev);
  935. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  936. struct res_common *r;
  937. spin_lock_irq(mlx4_tlock(dev));
  938. r = res_tracker_lookup(&tracker->res_tree[type], id);
  939. if (r && (r->owner == slave))
  940. r->state = r->to_state;
  941. spin_unlock_irq(mlx4_tlock(dev));
  942. }
  943. static int valid_reserved(struct mlx4_dev *dev, int slave, int qpn)
  944. {
  945. return mlx4_is_qp_reserved(dev, qpn) &&
  946. (mlx4_is_master(dev) || mlx4_is_guest_proxy(dev, slave, qpn));
  947. }
  948. static int fw_reserved(struct mlx4_dev *dev, int qpn)
  949. {
  950. return qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
  951. }
  952. static int qp_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  953. u64 in_param, u64 *out_param)
  954. {
  955. int err;
  956. int count;
  957. int align;
  958. int base;
  959. int qpn;
  960. switch (op) {
  961. case RES_OP_RESERVE:
  962. count = get_param_l(&in_param);
  963. align = get_param_h(&in_param);
  964. err = __mlx4_qp_reserve_range(dev, count, align, &base);
  965. if (err)
  966. return err;
  967. err = add_res_range(dev, slave, base, count, RES_QP, 0);
  968. if (err) {
  969. __mlx4_qp_release_range(dev, base, count);
  970. return err;
  971. }
  972. set_param_l(out_param, base);
  973. break;
  974. case RES_OP_MAP_ICM:
  975. qpn = get_param_l(&in_param) & 0x7fffff;
  976. if (valid_reserved(dev, slave, qpn)) {
  977. err = add_res_range(dev, slave, qpn, 1, RES_QP, 0);
  978. if (err)
  979. return err;
  980. }
  981. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED,
  982. NULL, 1);
  983. if (err)
  984. return err;
  985. if (!fw_reserved(dev, qpn)) {
  986. err = __mlx4_qp_alloc_icm(dev, qpn);
  987. if (err) {
  988. res_abort_move(dev, slave, RES_QP, qpn);
  989. return err;
  990. }
  991. }
  992. res_end_move(dev, slave, RES_QP, qpn);
  993. break;
  994. default:
  995. err = -EINVAL;
  996. break;
  997. }
  998. return err;
  999. }
  1000. static int mtt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1001. u64 in_param, u64 *out_param)
  1002. {
  1003. int err = -EINVAL;
  1004. int base;
  1005. int order;
  1006. if (op != RES_OP_RESERVE_AND_MAP)
  1007. return err;
  1008. order = get_param_l(&in_param);
  1009. base = __mlx4_alloc_mtt_range(dev, order);
  1010. if (base == -1)
  1011. return -ENOMEM;
  1012. err = add_res_range(dev, slave, base, 1, RES_MTT, order);
  1013. if (err)
  1014. __mlx4_free_mtt_range(dev, base, order);
  1015. else
  1016. set_param_l(out_param, base);
  1017. return err;
  1018. }
  1019. static int mpt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1020. u64 in_param, u64 *out_param)
  1021. {
  1022. int err = -EINVAL;
  1023. int index;
  1024. int id;
  1025. struct res_mpt *mpt;
  1026. switch (op) {
  1027. case RES_OP_RESERVE:
  1028. index = __mlx4_mr_reserve(dev);
  1029. if (index == -1)
  1030. break;
  1031. id = index & mpt_mask(dev);
  1032. err = add_res_range(dev, slave, id, 1, RES_MPT, index);
  1033. if (err) {
  1034. __mlx4_mr_release(dev, index);
  1035. break;
  1036. }
  1037. set_param_l(out_param, index);
  1038. break;
  1039. case RES_OP_MAP_ICM:
  1040. index = get_param_l(&in_param);
  1041. id = index & mpt_mask(dev);
  1042. err = mr_res_start_move_to(dev, slave, id,
  1043. RES_MPT_MAPPED, &mpt);
  1044. if (err)
  1045. return err;
  1046. err = __mlx4_mr_alloc_icm(dev, mpt->key);
  1047. if (err) {
  1048. res_abort_move(dev, slave, RES_MPT, id);
  1049. return err;
  1050. }
  1051. res_end_move(dev, slave, RES_MPT, id);
  1052. break;
  1053. }
  1054. return err;
  1055. }
  1056. static int cq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1057. u64 in_param, u64 *out_param)
  1058. {
  1059. int cqn;
  1060. int err;
  1061. switch (op) {
  1062. case RES_OP_RESERVE_AND_MAP:
  1063. err = __mlx4_cq_alloc_icm(dev, &cqn);
  1064. if (err)
  1065. break;
  1066. err = add_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  1067. if (err) {
  1068. __mlx4_cq_free_icm(dev, cqn);
  1069. break;
  1070. }
  1071. set_param_l(out_param, cqn);
  1072. break;
  1073. default:
  1074. err = -EINVAL;
  1075. }
  1076. return err;
  1077. }
  1078. static int srq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1079. u64 in_param, u64 *out_param)
  1080. {
  1081. int srqn;
  1082. int err;
  1083. switch (op) {
  1084. case RES_OP_RESERVE_AND_MAP:
  1085. err = __mlx4_srq_alloc_icm(dev, &srqn);
  1086. if (err)
  1087. break;
  1088. err = add_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  1089. if (err) {
  1090. __mlx4_srq_free_icm(dev, srqn);
  1091. break;
  1092. }
  1093. set_param_l(out_param, srqn);
  1094. break;
  1095. default:
  1096. err = -EINVAL;
  1097. }
  1098. return err;
  1099. }
  1100. static int mac_add_to_slave(struct mlx4_dev *dev, int slave, u64 mac, int port)
  1101. {
  1102. struct mlx4_priv *priv = mlx4_priv(dev);
  1103. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1104. struct mac_res *res;
  1105. res = kzalloc(sizeof *res, GFP_KERNEL);
  1106. if (!res)
  1107. return -ENOMEM;
  1108. res->mac = mac;
  1109. res->port = (u8) port;
  1110. list_add_tail(&res->list,
  1111. &tracker->slave_list[slave].res_list[RES_MAC]);
  1112. return 0;
  1113. }
  1114. static void mac_del_from_slave(struct mlx4_dev *dev, int slave, u64 mac,
  1115. int port)
  1116. {
  1117. struct mlx4_priv *priv = mlx4_priv(dev);
  1118. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1119. struct list_head *mac_list =
  1120. &tracker->slave_list[slave].res_list[RES_MAC];
  1121. struct mac_res *res, *tmp;
  1122. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1123. if (res->mac == mac && res->port == (u8) port) {
  1124. list_del(&res->list);
  1125. kfree(res);
  1126. break;
  1127. }
  1128. }
  1129. }
  1130. static void rem_slave_macs(struct mlx4_dev *dev, int slave)
  1131. {
  1132. struct mlx4_priv *priv = mlx4_priv(dev);
  1133. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1134. struct list_head *mac_list =
  1135. &tracker->slave_list[slave].res_list[RES_MAC];
  1136. struct mac_res *res, *tmp;
  1137. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1138. list_del(&res->list);
  1139. __mlx4_unregister_mac(dev, res->port, res->mac);
  1140. kfree(res);
  1141. }
  1142. }
  1143. static int mac_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1144. u64 in_param, u64 *out_param)
  1145. {
  1146. int err = -EINVAL;
  1147. int port;
  1148. u64 mac;
  1149. if (op != RES_OP_RESERVE_AND_MAP)
  1150. return err;
  1151. port = get_param_l(out_param);
  1152. mac = in_param;
  1153. err = __mlx4_register_mac(dev, port, mac);
  1154. if (err >= 0) {
  1155. set_param_l(out_param, err);
  1156. err = 0;
  1157. }
  1158. if (!err) {
  1159. err = mac_add_to_slave(dev, slave, mac, port);
  1160. if (err)
  1161. __mlx4_unregister_mac(dev, port, mac);
  1162. }
  1163. return err;
  1164. }
  1165. static int vlan_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1166. u64 in_param, u64 *out_param)
  1167. {
  1168. return 0;
  1169. }
  1170. static int counter_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1171. u64 in_param, u64 *out_param)
  1172. {
  1173. u32 index;
  1174. int err;
  1175. if (op != RES_OP_RESERVE)
  1176. return -EINVAL;
  1177. err = __mlx4_counter_alloc(dev, &index);
  1178. if (err)
  1179. return err;
  1180. err = add_res_range(dev, slave, index, 1, RES_COUNTER, 0);
  1181. if (err)
  1182. __mlx4_counter_free(dev, index);
  1183. else
  1184. set_param_l(out_param, index);
  1185. return err;
  1186. }
  1187. static int xrcdn_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1188. u64 in_param, u64 *out_param)
  1189. {
  1190. u32 xrcdn;
  1191. int err;
  1192. if (op != RES_OP_RESERVE)
  1193. return -EINVAL;
  1194. err = __mlx4_xrcd_alloc(dev, &xrcdn);
  1195. if (err)
  1196. return err;
  1197. err = add_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
  1198. if (err)
  1199. __mlx4_xrcd_free(dev, xrcdn);
  1200. else
  1201. set_param_l(out_param, xrcdn);
  1202. return err;
  1203. }
  1204. int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
  1205. struct mlx4_vhcr *vhcr,
  1206. struct mlx4_cmd_mailbox *inbox,
  1207. struct mlx4_cmd_mailbox *outbox,
  1208. struct mlx4_cmd_info *cmd)
  1209. {
  1210. int err;
  1211. int alop = vhcr->op_modifier;
  1212. switch (vhcr->in_modifier) {
  1213. case RES_QP:
  1214. err = qp_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1215. vhcr->in_param, &vhcr->out_param);
  1216. break;
  1217. case RES_MTT:
  1218. err = mtt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1219. vhcr->in_param, &vhcr->out_param);
  1220. break;
  1221. case RES_MPT:
  1222. err = mpt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1223. vhcr->in_param, &vhcr->out_param);
  1224. break;
  1225. case RES_CQ:
  1226. err = cq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1227. vhcr->in_param, &vhcr->out_param);
  1228. break;
  1229. case RES_SRQ:
  1230. err = srq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1231. vhcr->in_param, &vhcr->out_param);
  1232. break;
  1233. case RES_MAC:
  1234. err = mac_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1235. vhcr->in_param, &vhcr->out_param);
  1236. break;
  1237. case RES_VLAN:
  1238. err = vlan_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1239. vhcr->in_param, &vhcr->out_param);
  1240. break;
  1241. case RES_COUNTER:
  1242. err = counter_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1243. vhcr->in_param, &vhcr->out_param);
  1244. break;
  1245. case RES_XRCD:
  1246. err = xrcdn_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1247. vhcr->in_param, &vhcr->out_param);
  1248. break;
  1249. default:
  1250. err = -EINVAL;
  1251. break;
  1252. }
  1253. return err;
  1254. }
  1255. static int qp_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1256. u64 in_param)
  1257. {
  1258. int err;
  1259. int count;
  1260. int base;
  1261. int qpn;
  1262. switch (op) {
  1263. case RES_OP_RESERVE:
  1264. base = get_param_l(&in_param) & 0x7fffff;
  1265. count = get_param_h(&in_param);
  1266. err = rem_res_range(dev, slave, base, count, RES_QP, 0);
  1267. if (err)
  1268. break;
  1269. __mlx4_qp_release_range(dev, base, count);
  1270. break;
  1271. case RES_OP_MAP_ICM:
  1272. qpn = get_param_l(&in_param) & 0x7fffff;
  1273. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_RESERVED,
  1274. NULL, 0);
  1275. if (err)
  1276. return err;
  1277. if (!fw_reserved(dev, qpn))
  1278. __mlx4_qp_free_icm(dev, qpn);
  1279. res_end_move(dev, slave, RES_QP, qpn);
  1280. if (valid_reserved(dev, slave, qpn))
  1281. err = rem_res_range(dev, slave, qpn, 1, RES_QP, 0);
  1282. break;
  1283. default:
  1284. err = -EINVAL;
  1285. break;
  1286. }
  1287. return err;
  1288. }
  1289. static int mtt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1290. u64 in_param, u64 *out_param)
  1291. {
  1292. int err = -EINVAL;
  1293. int base;
  1294. int order;
  1295. if (op != RES_OP_RESERVE_AND_MAP)
  1296. return err;
  1297. base = get_param_l(&in_param);
  1298. order = get_param_h(&in_param);
  1299. err = rem_res_range(dev, slave, base, 1, RES_MTT, order);
  1300. if (!err)
  1301. __mlx4_free_mtt_range(dev, base, order);
  1302. return err;
  1303. }
  1304. static int mpt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1305. u64 in_param)
  1306. {
  1307. int err = -EINVAL;
  1308. int index;
  1309. int id;
  1310. struct res_mpt *mpt;
  1311. switch (op) {
  1312. case RES_OP_RESERVE:
  1313. index = get_param_l(&in_param);
  1314. id = index & mpt_mask(dev);
  1315. err = get_res(dev, slave, id, RES_MPT, &mpt);
  1316. if (err)
  1317. break;
  1318. index = mpt->key;
  1319. put_res(dev, slave, id, RES_MPT);
  1320. err = rem_res_range(dev, slave, id, 1, RES_MPT, 0);
  1321. if (err)
  1322. break;
  1323. __mlx4_mr_release(dev, index);
  1324. break;
  1325. case RES_OP_MAP_ICM:
  1326. index = get_param_l(&in_param);
  1327. id = index & mpt_mask(dev);
  1328. err = mr_res_start_move_to(dev, slave, id,
  1329. RES_MPT_RESERVED, &mpt);
  1330. if (err)
  1331. return err;
  1332. __mlx4_mr_free_icm(dev, mpt->key);
  1333. res_end_move(dev, slave, RES_MPT, id);
  1334. return err;
  1335. break;
  1336. default:
  1337. err = -EINVAL;
  1338. break;
  1339. }
  1340. return err;
  1341. }
  1342. static int cq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1343. u64 in_param, u64 *out_param)
  1344. {
  1345. int cqn;
  1346. int err;
  1347. switch (op) {
  1348. case RES_OP_RESERVE_AND_MAP:
  1349. cqn = get_param_l(&in_param);
  1350. err = rem_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  1351. if (err)
  1352. break;
  1353. __mlx4_cq_free_icm(dev, cqn);
  1354. break;
  1355. default:
  1356. err = -EINVAL;
  1357. break;
  1358. }
  1359. return err;
  1360. }
  1361. static int srq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1362. u64 in_param, u64 *out_param)
  1363. {
  1364. int srqn;
  1365. int err;
  1366. switch (op) {
  1367. case RES_OP_RESERVE_AND_MAP:
  1368. srqn = get_param_l(&in_param);
  1369. err = rem_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  1370. if (err)
  1371. break;
  1372. __mlx4_srq_free_icm(dev, srqn);
  1373. break;
  1374. default:
  1375. err = -EINVAL;
  1376. break;
  1377. }
  1378. return err;
  1379. }
  1380. static int mac_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1381. u64 in_param, u64 *out_param)
  1382. {
  1383. int port;
  1384. int err = 0;
  1385. switch (op) {
  1386. case RES_OP_RESERVE_AND_MAP:
  1387. port = get_param_l(out_param);
  1388. mac_del_from_slave(dev, slave, in_param, port);
  1389. __mlx4_unregister_mac(dev, port, in_param);
  1390. break;
  1391. default:
  1392. err = -EINVAL;
  1393. break;
  1394. }
  1395. return err;
  1396. }
  1397. static int vlan_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1398. u64 in_param, u64 *out_param)
  1399. {
  1400. return 0;
  1401. }
  1402. static int counter_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1403. u64 in_param, u64 *out_param)
  1404. {
  1405. int index;
  1406. int err;
  1407. if (op != RES_OP_RESERVE)
  1408. return -EINVAL;
  1409. index = get_param_l(&in_param);
  1410. err = rem_res_range(dev, slave, index, 1, RES_COUNTER, 0);
  1411. if (err)
  1412. return err;
  1413. __mlx4_counter_free(dev, index);
  1414. return err;
  1415. }
  1416. static int xrcdn_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1417. u64 in_param, u64 *out_param)
  1418. {
  1419. int xrcdn;
  1420. int err;
  1421. if (op != RES_OP_RESERVE)
  1422. return -EINVAL;
  1423. xrcdn = get_param_l(&in_param);
  1424. err = rem_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
  1425. if (err)
  1426. return err;
  1427. __mlx4_xrcd_free(dev, xrcdn);
  1428. return err;
  1429. }
  1430. int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
  1431. struct mlx4_vhcr *vhcr,
  1432. struct mlx4_cmd_mailbox *inbox,
  1433. struct mlx4_cmd_mailbox *outbox,
  1434. struct mlx4_cmd_info *cmd)
  1435. {
  1436. int err = -EINVAL;
  1437. int alop = vhcr->op_modifier;
  1438. switch (vhcr->in_modifier) {
  1439. case RES_QP:
  1440. err = qp_free_res(dev, slave, vhcr->op_modifier, alop,
  1441. vhcr->in_param);
  1442. break;
  1443. case RES_MTT:
  1444. err = mtt_free_res(dev, slave, vhcr->op_modifier, alop,
  1445. vhcr->in_param, &vhcr->out_param);
  1446. break;
  1447. case RES_MPT:
  1448. err = mpt_free_res(dev, slave, vhcr->op_modifier, alop,
  1449. vhcr->in_param);
  1450. break;
  1451. case RES_CQ:
  1452. err = cq_free_res(dev, slave, vhcr->op_modifier, alop,
  1453. vhcr->in_param, &vhcr->out_param);
  1454. break;
  1455. case RES_SRQ:
  1456. err = srq_free_res(dev, slave, vhcr->op_modifier, alop,
  1457. vhcr->in_param, &vhcr->out_param);
  1458. break;
  1459. case RES_MAC:
  1460. err = mac_free_res(dev, slave, vhcr->op_modifier, alop,
  1461. vhcr->in_param, &vhcr->out_param);
  1462. break;
  1463. case RES_VLAN:
  1464. err = vlan_free_res(dev, slave, vhcr->op_modifier, alop,
  1465. vhcr->in_param, &vhcr->out_param);
  1466. break;
  1467. case RES_COUNTER:
  1468. err = counter_free_res(dev, slave, vhcr->op_modifier, alop,
  1469. vhcr->in_param, &vhcr->out_param);
  1470. break;
  1471. case RES_XRCD:
  1472. err = xrcdn_free_res(dev, slave, vhcr->op_modifier, alop,
  1473. vhcr->in_param, &vhcr->out_param);
  1474. default:
  1475. break;
  1476. }
  1477. return err;
  1478. }
  1479. /* ugly but other choices are uglier */
  1480. static int mr_phys_mpt(struct mlx4_mpt_entry *mpt)
  1481. {
  1482. return (be32_to_cpu(mpt->flags) >> 9) & 1;
  1483. }
  1484. static int mr_get_mtt_addr(struct mlx4_mpt_entry *mpt)
  1485. {
  1486. return (int)be64_to_cpu(mpt->mtt_addr) & 0xfffffff8;
  1487. }
  1488. static int mr_get_mtt_size(struct mlx4_mpt_entry *mpt)
  1489. {
  1490. return be32_to_cpu(mpt->mtt_sz);
  1491. }
  1492. static int qp_get_mtt_addr(struct mlx4_qp_context *qpc)
  1493. {
  1494. return be32_to_cpu(qpc->mtt_base_addr_l) & 0xfffffff8;
  1495. }
  1496. static int srq_get_mtt_addr(struct mlx4_srq_context *srqc)
  1497. {
  1498. return be32_to_cpu(srqc->mtt_base_addr_l) & 0xfffffff8;
  1499. }
  1500. static int qp_get_mtt_size(struct mlx4_qp_context *qpc)
  1501. {
  1502. int page_shift = (qpc->log_page_size & 0x3f) + 12;
  1503. int log_sq_size = (qpc->sq_size_stride >> 3) & 0xf;
  1504. int log_sq_sride = qpc->sq_size_stride & 7;
  1505. int log_rq_size = (qpc->rq_size_stride >> 3) & 0xf;
  1506. int log_rq_stride = qpc->rq_size_stride & 7;
  1507. int srq = (be32_to_cpu(qpc->srqn) >> 24) & 1;
  1508. int rss = (be32_to_cpu(qpc->flags) >> 13) & 1;
  1509. int xrc = (be32_to_cpu(qpc->local_qpn) >> 23) & 1;
  1510. int sq_size;
  1511. int rq_size;
  1512. int total_pages;
  1513. int total_mem;
  1514. int page_offset = (be32_to_cpu(qpc->params2) >> 6) & 0x3f;
  1515. sq_size = 1 << (log_sq_size + log_sq_sride + 4);
  1516. rq_size = (srq|rss|xrc) ? 0 : (1 << (log_rq_size + log_rq_stride + 4));
  1517. total_mem = sq_size + rq_size;
  1518. total_pages =
  1519. roundup_pow_of_two((total_mem + (page_offset << 6)) >>
  1520. page_shift);
  1521. return total_pages;
  1522. }
  1523. static int check_mtt_range(struct mlx4_dev *dev, int slave, int start,
  1524. int size, struct res_mtt *mtt)
  1525. {
  1526. int res_start = mtt->com.res_id;
  1527. int res_size = (1 << mtt->order);
  1528. if (start < res_start || start + size > res_start + res_size)
  1529. return -EPERM;
  1530. return 0;
  1531. }
  1532. int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1533. struct mlx4_vhcr *vhcr,
  1534. struct mlx4_cmd_mailbox *inbox,
  1535. struct mlx4_cmd_mailbox *outbox,
  1536. struct mlx4_cmd_info *cmd)
  1537. {
  1538. int err;
  1539. int index = vhcr->in_modifier;
  1540. struct res_mtt *mtt;
  1541. struct res_mpt *mpt;
  1542. int mtt_base = mr_get_mtt_addr(inbox->buf) / dev->caps.mtt_entry_sz;
  1543. int phys;
  1544. int id;
  1545. id = index & mpt_mask(dev);
  1546. err = mr_res_start_move_to(dev, slave, id, RES_MPT_HW, &mpt);
  1547. if (err)
  1548. return err;
  1549. phys = mr_phys_mpt(inbox->buf);
  1550. if (!phys) {
  1551. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1552. if (err)
  1553. goto ex_abort;
  1554. err = check_mtt_range(dev, slave, mtt_base,
  1555. mr_get_mtt_size(inbox->buf), mtt);
  1556. if (err)
  1557. goto ex_put;
  1558. mpt->mtt = mtt;
  1559. }
  1560. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1561. if (err)
  1562. goto ex_put;
  1563. if (!phys) {
  1564. atomic_inc(&mtt->ref_count);
  1565. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1566. }
  1567. res_end_move(dev, slave, RES_MPT, id);
  1568. return 0;
  1569. ex_put:
  1570. if (!phys)
  1571. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1572. ex_abort:
  1573. res_abort_move(dev, slave, RES_MPT, id);
  1574. return err;
  1575. }
  1576. int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1577. struct mlx4_vhcr *vhcr,
  1578. struct mlx4_cmd_mailbox *inbox,
  1579. struct mlx4_cmd_mailbox *outbox,
  1580. struct mlx4_cmd_info *cmd)
  1581. {
  1582. int err;
  1583. int index = vhcr->in_modifier;
  1584. struct res_mpt *mpt;
  1585. int id;
  1586. id = index & mpt_mask(dev);
  1587. err = mr_res_start_move_to(dev, slave, id, RES_MPT_MAPPED, &mpt);
  1588. if (err)
  1589. return err;
  1590. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1591. if (err)
  1592. goto ex_abort;
  1593. if (mpt->mtt)
  1594. atomic_dec(&mpt->mtt->ref_count);
  1595. res_end_move(dev, slave, RES_MPT, id);
  1596. return 0;
  1597. ex_abort:
  1598. res_abort_move(dev, slave, RES_MPT, id);
  1599. return err;
  1600. }
  1601. int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1602. struct mlx4_vhcr *vhcr,
  1603. struct mlx4_cmd_mailbox *inbox,
  1604. struct mlx4_cmd_mailbox *outbox,
  1605. struct mlx4_cmd_info *cmd)
  1606. {
  1607. int err;
  1608. int index = vhcr->in_modifier;
  1609. struct res_mpt *mpt;
  1610. int id;
  1611. id = index & mpt_mask(dev);
  1612. err = get_res(dev, slave, id, RES_MPT, &mpt);
  1613. if (err)
  1614. return err;
  1615. if (mpt->com.from_state != RES_MPT_HW) {
  1616. err = -EBUSY;
  1617. goto out;
  1618. }
  1619. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1620. out:
  1621. put_res(dev, slave, id, RES_MPT);
  1622. return err;
  1623. }
  1624. static int qp_get_rcqn(struct mlx4_qp_context *qpc)
  1625. {
  1626. return be32_to_cpu(qpc->cqn_recv) & 0xffffff;
  1627. }
  1628. static int qp_get_scqn(struct mlx4_qp_context *qpc)
  1629. {
  1630. return be32_to_cpu(qpc->cqn_send) & 0xffffff;
  1631. }
  1632. static u32 qp_get_srqn(struct mlx4_qp_context *qpc)
  1633. {
  1634. return be32_to_cpu(qpc->srqn) & 0x1ffffff;
  1635. }
  1636. static void adjust_proxy_tun_qkey(struct mlx4_dev *dev, struct mlx4_vhcr *vhcr,
  1637. struct mlx4_qp_context *context)
  1638. {
  1639. u32 qpn = vhcr->in_modifier & 0xffffff;
  1640. u32 qkey = 0;
  1641. if (mlx4_get_parav_qkey(dev, qpn, &qkey))
  1642. return;
  1643. /* adjust qkey in qp context */
  1644. context->qkey = cpu_to_be32(qkey);
  1645. }
  1646. int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
  1647. struct mlx4_vhcr *vhcr,
  1648. struct mlx4_cmd_mailbox *inbox,
  1649. struct mlx4_cmd_mailbox *outbox,
  1650. struct mlx4_cmd_info *cmd)
  1651. {
  1652. int err;
  1653. int qpn = vhcr->in_modifier & 0x7fffff;
  1654. struct res_mtt *mtt;
  1655. struct res_qp *qp;
  1656. struct mlx4_qp_context *qpc = inbox->buf + 8;
  1657. int mtt_base = qp_get_mtt_addr(qpc) / dev->caps.mtt_entry_sz;
  1658. int mtt_size = qp_get_mtt_size(qpc);
  1659. struct res_cq *rcq;
  1660. struct res_cq *scq;
  1661. int rcqn = qp_get_rcqn(qpc);
  1662. int scqn = qp_get_scqn(qpc);
  1663. u32 srqn = qp_get_srqn(qpc) & 0xffffff;
  1664. int use_srq = (qp_get_srqn(qpc) >> 24) & 1;
  1665. struct res_srq *srq;
  1666. int local_qpn = be32_to_cpu(qpc->local_qpn) & 0xffffff;
  1667. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_HW, &qp, 0);
  1668. if (err)
  1669. return err;
  1670. qp->local_qpn = local_qpn;
  1671. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1672. if (err)
  1673. goto ex_abort;
  1674. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  1675. if (err)
  1676. goto ex_put_mtt;
  1677. err = get_res(dev, slave, rcqn, RES_CQ, &rcq);
  1678. if (err)
  1679. goto ex_put_mtt;
  1680. if (scqn != rcqn) {
  1681. err = get_res(dev, slave, scqn, RES_CQ, &scq);
  1682. if (err)
  1683. goto ex_put_rcq;
  1684. } else
  1685. scq = rcq;
  1686. if (use_srq) {
  1687. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  1688. if (err)
  1689. goto ex_put_scq;
  1690. }
  1691. adjust_proxy_tun_qkey(dev, vhcr, qpc);
  1692. update_pkey_index(dev, slave, inbox);
  1693. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1694. if (err)
  1695. goto ex_put_srq;
  1696. atomic_inc(&mtt->ref_count);
  1697. qp->mtt = mtt;
  1698. atomic_inc(&rcq->ref_count);
  1699. qp->rcq = rcq;
  1700. atomic_inc(&scq->ref_count);
  1701. qp->scq = scq;
  1702. if (scqn != rcqn)
  1703. put_res(dev, slave, scqn, RES_CQ);
  1704. if (use_srq) {
  1705. atomic_inc(&srq->ref_count);
  1706. put_res(dev, slave, srqn, RES_SRQ);
  1707. qp->srq = srq;
  1708. }
  1709. put_res(dev, slave, rcqn, RES_CQ);
  1710. put_res(dev, slave, mtt_base, RES_MTT);
  1711. res_end_move(dev, slave, RES_QP, qpn);
  1712. return 0;
  1713. ex_put_srq:
  1714. if (use_srq)
  1715. put_res(dev, slave, srqn, RES_SRQ);
  1716. ex_put_scq:
  1717. if (scqn != rcqn)
  1718. put_res(dev, slave, scqn, RES_CQ);
  1719. ex_put_rcq:
  1720. put_res(dev, slave, rcqn, RES_CQ);
  1721. ex_put_mtt:
  1722. put_res(dev, slave, mtt_base, RES_MTT);
  1723. ex_abort:
  1724. res_abort_move(dev, slave, RES_QP, qpn);
  1725. return err;
  1726. }
  1727. static int eq_get_mtt_addr(struct mlx4_eq_context *eqc)
  1728. {
  1729. return be32_to_cpu(eqc->mtt_base_addr_l) & 0xfffffff8;
  1730. }
  1731. static int eq_get_mtt_size(struct mlx4_eq_context *eqc)
  1732. {
  1733. int log_eq_size = eqc->log_eq_size & 0x1f;
  1734. int page_shift = (eqc->log_page_size & 0x3f) + 12;
  1735. if (log_eq_size + 5 < page_shift)
  1736. return 1;
  1737. return 1 << (log_eq_size + 5 - page_shift);
  1738. }
  1739. static int cq_get_mtt_addr(struct mlx4_cq_context *cqc)
  1740. {
  1741. return be32_to_cpu(cqc->mtt_base_addr_l) & 0xfffffff8;
  1742. }
  1743. static int cq_get_mtt_size(struct mlx4_cq_context *cqc)
  1744. {
  1745. int log_cq_size = (be32_to_cpu(cqc->logsize_usrpage) >> 24) & 0x1f;
  1746. int page_shift = (cqc->log_page_size & 0x3f) + 12;
  1747. if (log_cq_size + 5 < page_shift)
  1748. return 1;
  1749. return 1 << (log_cq_size + 5 - page_shift);
  1750. }
  1751. int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1752. struct mlx4_vhcr *vhcr,
  1753. struct mlx4_cmd_mailbox *inbox,
  1754. struct mlx4_cmd_mailbox *outbox,
  1755. struct mlx4_cmd_info *cmd)
  1756. {
  1757. int err;
  1758. int eqn = vhcr->in_modifier;
  1759. int res_id = (slave << 8) | eqn;
  1760. struct mlx4_eq_context *eqc = inbox->buf;
  1761. int mtt_base = eq_get_mtt_addr(eqc) / dev->caps.mtt_entry_sz;
  1762. int mtt_size = eq_get_mtt_size(eqc);
  1763. struct res_eq *eq;
  1764. struct res_mtt *mtt;
  1765. err = add_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1766. if (err)
  1767. return err;
  1768. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_HW, &eq);
  1769. if (err)
  1770. goto out_add;
  1771. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1772. if (err)
  1773. goto out_move;
  1774. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  1775. if (err)
  1776. goto out_put;
  1777. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1778. if (err)
  1779. goto out_put;
  1780. atomic_inc(&mtt->ref_count);
  1781. eq->mtt = mtt;
  1782. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1783. res_end_move(dev, slave, RES_EQ, res_id);
  1784. return 0;
  1785. out_put:
  1786. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1787. out_move:
  1788. res_abort_move(dev, slave, RES_EQ, res_id);
  1789. out_add:
  1790. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1791. return err;
  1792. }
  1793. static int get_containing_mtt(struct mlx4_dev *dev, int slave, int start,
  1794. int len, struct res_mtt **res)
  1795. {
  1796. struct mlx4_priv *priv = mlx4_priv(dev);
  1797. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1798. struct res_mtt *mtt;
  1799. int err = -EINVAL;
  1800. spin_lock_irq(mlx4_tlock(dev));
  1801. list_for_each_entry(mtt, &tracker->slave_list[slave].res_list[RES_MTT],
  1802. com.list) {
  1803. if (!check_mtt_range(dev, slave, start, len, mtt)) {
  1804. *res = mtt;
  1805. mtt->com.from_state = mtt->com.state;
  1806. mtt->com.state = RES_MTT_BUSY;
  1807. err = 0;
  1808. break;
  1809. }
  1810. }
  1811. spin_unlock_irq(mlx4_tlock(dev));
  1812. return err;
  1813. }
  1814. static int verify_qp_parameters(struct mlx4_dev *dev,
  1815. struct mlx4_cmd_mailbox *inbox,
  1816. enum qp_transition transition, u8 slave)
  1817. {
  1818. u32 qp_type;
  1819. struct mlx4_qp_context *qp_ctx;
  1820. enum mlx4_qp_optpar optpar;
  1821. qp_ctx = inbox->buf + 8;
  1822. qp_type = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
  1823. optpar = be32_to_cpu(*(__be32 *) inbox->buf);
  1824. switch (qp_type) {
  1825. case MLX4_QP_ST_RC:
  1826. case MLX4_QP_ST_UC:
  1827. switch (transition) {
  1828. case QP_TRANS_INIT2RTR:
  1829. case QP_TRANS_RTR2RTS:
  1830. case QP_TRANS_RTS2RTS:
  1831. case QP_TRANS_SQD2SQD:
  1832. case QP_TRANS_SQD2RTS:
  1833. if (slave != mlx4_master_func_num(dev))
  1834. /* slaves have only gid index 0 */
  1835. if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH)
  1836. if (qp_ctx->pri_path.mgid_index)
  1837. return -EINVAL;
  1838. if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH)
  1839. if (qp_ctx->alt_path.mgid_index)
  1840. return -EINVAL;
  1841. break;
  1842. default:
  1843. break;
  1844. }
  1845. break;
  1846. default:
  1847. break;
  1848. }
  1849. return 0;
  1850. }
  1851. int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
  1852. struct mlx4_vhcr *vhcr,
  1853. struct mlx4_cmd_mailbox *inbox,
  1854. struct mlx4_cmd_mailbox *outbox,
  1855. struct mlx4_cmd_info *cmd)
  1856. {
  1857. struct mlx4_mtt mtt;
  1858. __be64 *page_list = inbox->buf;
  1859. u64 *pg_list = (u64 *)page_list;
  1860. int i;
  1861. struct res_mtt *rmtt = NULL;
  1862. int start = be64_to_cpu(page_list[0]);
  1863. int npages = vhcr->in_modifier;
  1864. int err;
  1865. err = get_containing_mtt(dev, slave, start, npages, &rmtt);
  1866. if (err)
  1867. return err;
  1868. /* Call the SW implementation of write_mtt:
  1869. * - Prepare a dummy mtt struct
  1870. * - Translate inbox contents to simple addresses in host endianess */
  1871. mtt.offset = 0; /* TBD this is broken but I don't handle it since
  1872. we don't really use it */
  1873. mtt.order = 0;
  1874. mtt.page_shift = 0;
  1875. for (i = 0; i < npages; ++i)
  1876. pg_list[i + 2] = (be64_to_cpu(page_list[i + 2]) & ~1ULL);
  1877. err = __mlx4_write_mtt(dev, &mtt, be64_to_cpu(page_list[0]), npages,
  1878. ((u64 *)page_list + 2));
  1879. if (rmtt)
  1880. put_res(dev, slave, rmtt->com.res_id, RES_MTT);
  1881. return err;
  1882. }
  1883. int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1884. struct mlx4_vhcr *vhcr,
  1885. struct mlx4_cmd_mailbox *inbox,
  1886. struct mlx4_cmd_mailbox *outbox,
  1887. struct mlx4_cmd_info *cmd)
  1888. {
  1889. int eqn = vhcr->in_modifier;
  1890. int res_id = eqn | (slave << 8);
  1891. struct res_eq *eq;
  1892. int err;
  1893. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_RESERVED, &eq);
  1894. if (err)
  1895. return err;
  1896. err = get_res(dev, slave, eq->mtt->com.res_id, RES_MTT, NULL);
  1897. if (err)
  1898. goto ex_abort;
  1899. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1900. if (err)
  1901. goto ex_put;
  1902. atomic_dec(&eq->mtt->ref_count);
  1903. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  1904. res_end_move(dev, slave, RES_EQ, res_id);
  1905. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1906. return 0;
  1907. ex_put:
  1908. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  1909. ex_abort:
  1910. res_abort_move(dev, slave, RES_EQ, res_id);
  1911. return err;
  1912. }
  1913. int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe)
  1914. {
  1915. struct mlx4_priv *priv = mlx4_priv(dev);
  1916. struct mlx4_slave_event_eq_info *event_eq;
  1917. struct mlx4_cmd_mailbox *mailbox;
  1918. u32 in_modifier = 0;
  1919. int err;
  1920. int res_id;
  1921. struct res_eq *req;
  1922. if (!priv->mfunc.master.slave_state)
  1923. return -EINVAL;
  1924. event_eq = &priv->mfunc.master.slave_state[slave].event_eq[eqe->type];
  1925. /* Create the event only if the slave is registered */
  1926. if (event_eq->eqn < 0)
  1927. return 0;
  1928. mutex_lock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  1929. res_id = (slave << 8) | event_eq->eqn;
  1930. err = get_res(dev, slave, res_id, RES_EQ, &req);
  1931. if (err)
  1932. goto unlock;
  1933. if (req->com.from_state != RES_EQ_HW) {
  1934. err = -EINVAL;
  1935. goto put;
  1936. }
  1937. mailbox = mlx4_alloc_cmd_mailbox(dev);
  1938. if (IS_ERR(mailbox)) {
  1939. err = PTR_ERR(mailbox);
  1940. goto put;
  1941. }
  1942. if (eqe->type == MLX4_EVENT_TYPE_CMD) {
  1943. ++event_eq->token;
  1944. eqe->event.cmd.token = cpu_to_be16(event_eq->token);
  1945. }
  1946. memcpy(mailbox->buf, (u8 *) eqe, 28);
  1947. in_modifier = (slave & 0xff) | ((event_eq->eqn & 0xff) << 16);
  1948. err = mlx4_cmd(dev, mailbox->dma, in_modifier, 0,
  1949. MLX4_CMD_GEN_EQE, MLX4_CMD_TIME_CLASS_B,
  1950. MLX4_CMD_NATIVE);
  1951. put_res(dev, slave, res_id, RES_EQ);
  1952. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  1953. mlx4_free_cmd_mailbox(dev, mailbox);
  1954. return err;
  1955. put:
  1956. put_res(dev, slave, res_id, RES_EQ);
  1957. unlock:
  1958. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  1959. return err;
  1960. }
  1961. int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1962. struct mlx4_vhcr *vhcr,
  1963. struct mlx4_cmd_mailbox *inbox,
  1964. struct mlx4_cmd_mailbox *outbox,
  1965. struct mlx4_cmd_info *cmd)
  1966. {
  1967. int eqn = vhcr->in_modifier;
  1968. int res_id = eqn | (slave << 8);
  1969. struct res_eq *eq;
  1970. int err;
  1971. err = get_res(dev, slave, res_id, RES_EQ, &eq);
  1972. if (err)
  1973. return err;
  1974. if (eq->com.from_state != RES_EQ_HW) {
  1975. err = -EINVAL;
  1976. goto ex_put;
  1977. }
  1978. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1979. ex_put:
  1980. put_res(dev, slave, res_id, RES_EQ);
  1981. return err;
  1982. }
  1983. int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1984. struct mlx4_vhcr *vhcr,
  1985. struct mlx4_cmd_mailbox *inbox,
  1986. struct mlx4_cmd_mailbox *outbox,
  1987. struct mlx4_cmd_info *cmd)
  1988. {
  1989. int err;
  1990. int cqn = vhcr->in_modifier;
  1991. struct mlx4_cq_context *cqc = inbox->buf;
  1992. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  1993. struct res_cq *cq;
  1994. struct res_mtt *mtt;
  1995. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_HW, &cq);
  1996. if (err)
  1997. return err;
  1998. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1999. if (err)
  2000. goto out_move;
  2001. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  2002. if (err)
  2003. goto out_put;
  2004. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2005. if (err)
  2006. goto out_put;
  2007. atomic_inc(&mtt->ref_count);
  2008. cq->mtt = mtt;
  2009. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2010. res_end_move(dev, slave, RES_CQ, cqn);
  2011. return 0;
  2012. out_put:
  2013. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2014. out_move:
  2015. res_abort_move(dev, slave, RES_CQ, cqn);
  2016. return err;
  2017. }
  2018. int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  2019. struct mlx4_vhcr *vhcr,
  2020. struct mlx4_cmd_mailbox *inbox,
  2021. struct mlx4_cmd_mailbox *outbox,
  2022. struct mlx4_cmd_info *cmd)
  2023. {
  2024. int err;
  2025. int cqn = vhcr->in_modifier;
  2026. struct res_cq *cq;
  2027. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_ALLOCATED, &cq);
  2028. if (err)
  2029. return err;
  2030. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2031. if (err)
  2032. goto out_move;
  2033. atomic_dec(&cq->mtt->ref_count);
  2034. res_end_move(dev, slave, RES_CQ, cqn);
  2035. return 0;
  2036. out_move:
  2037. res_abort_move(dev, slave, RES_CQ, cqn);
  2038. return err;
  2039. }
  2040. int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  2041. struct mlx4_vhcr *vhcr,
  2042. struct mlx4_cmd_mailbox *inbox,
  2043. struct mlx4_cmd_mailbox *outbox,
  2044. struct mlx4_cmd_info *cmd)
  2045. {
  2046. int cqn = vhcr->in_modifier;
  2047. struct res_cq *cq;
  2048. int err;
  2049. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  2050. if (err)
  2051. return err;
  2052. if (cq->com.from_state != RES_CQ_HW)
  2053. goto ex_put;
  2054. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2055. ex_put:
  2056. put_res(dev, slave, cqn, RES_CQ);
  2057. return err;
  2058. }
  2059. static int handle_resize(struct mlx4_dev *dev, int slave,
  2060. struct mlx4_vhcr *vhcr,
  2061. struct mlx4_cmd_mailbox *inbox,
  2062. struct mlx4_cmd_mailbox *outbox,
  2063. struct mlx4_cmd_info *cmd,
  2064. struct res_cq *cq)
  2065. {
  2066. int err;
  2067. struct res_mtt *orig_mtt;
  2068. struct res_mtt *mtt;
  2069. struct mlx4_cq_context *cqc = inbox->buf;
  2070. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  2071. err = get_res(dev, slave, cq->mtt->com.res_id, RES_MTT, &orig_mtt);
  2072. if (err)
  2073. return err;
  2074. if (orig_mtt != cq->mtt) {
  2075. err = -EINVAL;
  2076. goto ex_put;
  2077. }
  2078. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2079. if (err)
  2080. goto ex_put;
  2081. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  2082. if (err)
  2083. goto ex_put1;
  2084. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2085. if (err)
  2086. goto ex_put1;
  2087. atomic_dec(&orig_mtt->ref_count);
  2088. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  2089. atomic_inc(&mtt->ref_count);
  2090. cq->mtt = mtt;
  2091. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2092. return 0;
  2093. ex_put1:
  2094. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2095. ex_put:
  2096. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  2097. return err;
  2098. }
  2099. int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  2100. struct mlx4_vhcr *vhcr,
  2101. struct mlx4_cmd_mailbox *inbox,
  2102. struct mlx4_cmd_mailbox *outbox,
  2103. struct mlx4_cmd_info *cmd)
  2104. {
  2105. int cqn = vhcr->in_modifier;
  2106. struct res_cq *cq;
  2107. int err;
  2108. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  2109. if (err)
  2110. return err;
  2111. if (cq->com.from_state != RES_CQ_HW)
  2112. goto ex_put;
  2113. if (vhcr->op_modifier == 0) {
  2114. err = handle_resize(dev, slave, vhcr, inbox, outbox, cmd, cq);
  2115. goto ex_put;
  2116. }
  2117. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2118. ex_put:
  2119. put_res(dev, slave, cqn, RES_CQ);
  2120. return err;
  2121. }
  2122. static int srq_get_mtt_size(struct mlx4_srq_context *srqc)
  2123. {
  2124. int log_srq_size = (be32_to_cpu(srqc->state_logsize_srqn) >> 24) & 0xf;
  2125. int log_rq_stride = srqc->logstride & 7;
  2126. int page_shift = (srqc->log_page_size & 0x3f) + 12;
  2127. if (log_srq_size + log_rq_stride + 4 < page_shift)
  2128. return 1;
  2129. return 1 << (log_srq_size + log_rq_stride + 4 - page_shift);
  2130. }
  2131. int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2132. struct mlx4_vhcr *vhcr,
  2133. struct mlx4_cmd_mailbox *inbox,
  2134. struct mlx4_cmd_mailbox *outbox,
  2135. struct mlx4_cmd_info *cmd)
  2136. {
  2137. int err;
  2138. int srqn = vhcr->in_modifier;
  2139. struct res_mtt *mtt;
  2140. struct res_srq *srq;
  2141. struct mlx4_srq_context *srqc = inbox->buf;
  2142. int mtt_base = srq_get_mtt_addr(srqc) / dev->caps.mtt_entry_sz;
  2143. if (srqn != (be32_to_cpu(srqc->state_logsize_srqn) & 0xffffff))
  2144. return -EINVAL;
  2145. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_HW, &srq);
  2146. if (err)
  2147. return err;
  2148. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2149. if (err)
  2150. goto ex_abort;
  2151. err = check_mtt_range(dev, slave, mtt_base, srq_get_mtt_size(srqc),
  2152. mtt);
  2153. if (err)
  2154. goto ex_put_mtt;
  2155. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2156. if (err)
  2157. goto ex_put_mtt;
  2158. atomic_inc(&mtt->ref_count);
  2159. srq->mtt = mtt;
  2160. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2161. res_end_move(dev, slave, RES_SRQ, srqn);
  2162. return 0;
  2163. ex_put_mtt:
  2164. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2165. ex_abort:
  2166. res_abort_move(dev, slave, RES_SRQ, srqn);
  2167. return err;
  2168. }
  2169. int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2170. struct mlx4_vhcr *vhcr,
  2171. struct mlx4_cmd_mailbox *inbox,
  2172. struct mlx4_cmd_mailbox *outbox,
  2173. struct mlx4_cmd_info *cmd)
  2174. {
  2175. int err;
  2176. int srqn = vhcr->in_modifier;
  2177. struct res_srq *srq;
  2178. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_ALLOCATED, &srq);
  2179. if (err)
  2180. return err;
  2181. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2182. if (err)
  2183. goto ex_abort;
  2184. atomic_dec(&srq->mtt->ref_count);
  2185. if (srq->cq)
  2186. atomic_dec(&srq->cq->ref_count);
  2187. res_end_move(dev, slave, RES_SRQ, srqn);
  2188. return 0;
  2189. ex_abort:
  2190. res_abort_move(dev, slave, RES_SRQ, srqn);
  2191. return err;
  2192. }
  2193. int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2194. struct mlx4_vhcr *vhcr,
  2195. struct mlx4_cmd_mailbox *inbox,
  2196. struct mlx4_cmd_mailbox *outbox,
  2197. struct mlx4_cmd_info *cmd)
  2198. {
  2199. int err;
  2200. int srqn = vhcr->in_modifier;
  2201. struct res_srq *srq;
  2202. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  2203. if (err)
  2204. return err;
  2205. if (srq->com.from_state != RES_SRQ_HW) {
  2206. err = -EBUSY;
  2207. goto out;
  2208. }
  2209. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2210. out:
  2211. put_res(dev, slave, srqn, RES_SRQ);
  2212. return err;
  2213. }
  2214. int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2215. struct mlx4_vhcr *vhcr,
  2216. struct mlx4_cmd_mailbox *inbox,
  2217. struct mlx4_cmd_mailbox *outbox,
  2218. struct mlx4_cmd_info *cmd)
  2219. {
  2220. int err;
  2221. int srqn = vhcr->in_modifier;
  2222. struct res_srq *srq;
  2223. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  2224. if (err)
  2225. return err;
  2226. if (srq->com.from_state != RES_SRQ_HW) {
  2227. err = -EBUSY;
  2228. goto out;
  2229. }
  2230. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2231. out:
  2232. put_res(dev, slave, srqn, RES_SRQ);
  2233. return err;
  2234. }
  2235. int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
  2236. struct mlx4_vhcr *vhcr,
  2237. struct mlx4_cmd_mailbox *inbox,
  2238. struct mlx4_cmd_mailbox *outbox,
  2239. struct mlx4_cmd_info *cmd)
  2240. {
  2241. int err;
  2242. int qpn = vhcr->in_modifier & 0x7fffff;
  2243. struct res_qp *qp;
  2244. err = get_res(dev, slave, qpn, RES_QP, &qp);
  2245. if (err)
  2246. return err;
  2247. if (qp->com.from_state != RES_QP_HW) {
  2248. err = -EBUSY;
  2249. goto out;
  2250. }
  2251. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2252. out:
  2253. put_res(dev, slave, qpn, RES_QP);
  2254. return err;
  2255. }
  2256. int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
  2257. struct mlx4_vhcr *vhcr,
  2258. struct mlx4_cmd_mailbox *inbox,
  2259. struct mlx4_cmd_mailbox *outbox,
  2260. struct mlx4_cmd_info *cmd)
  2261. {
  2262. struct mlx4_qp_context *context = inbox->buf + 8;
  2263. adjust_proxy_tun_qkey(dev, vhcr, context);
  2264. update_pkey_index(dev, slave, inbox);
  2265. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2266. }
  2267. int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
  2268. struct mlx4_vhcr *vhcr,
  2269. struct mlx4_cmd_mailbox *inbox,
  2270. struct mlx4_cmd_mailbox *outbox,
  2271. struct mlx4_cmd_info *cmd)
  2272. {
  2273. int err;
  2274. struct mlx4_qp_context *qpc = inbox->buf + 8;
  2275. err = verify_qp_parameters(dev, inbox, QP_TRANS_INIT2RTR, slave);
  2276. if (err)
  2277. return err;
  2278. update_pkey_index(dev, slave, inbox);
  2279. update_gid(dev, inbox, (u8)slave);
  2280. adjust_proxy_tun_qkey(dev, vhcr, qpc);
  2281. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2282. }
  2283. int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
  2284. struct mlx4_vhcr *vhcr,
  2285. struct mlx4_cmd_mailbox *inbox,
  2286. struct mlx4_cmd_mailbox *outbox,
  2287. struct mlx4_cmd_info *cmd)
  2288. {
  2289. int err;
  2290. struct mlx4_qp_context *context = inbox->buf + 8;
  2291. err = verify_qp_parameters(dev, inbox, QP_TRANS_RTR2RTS, slave);
  2292. if (err)
  2293. return err;
  2294. update_pkey_index(dev, slave, inbox);
  2295. update_gid(dev, inbox, (u8)slave);
  2296. adjust_proxy_tun_qkey(dev, vhcr, context);
  2297. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2298. }
  2299. int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
  2300. struct mlx4_vhcr *vhcr,
  2301. struct mlx4_cmd_mailbox *inbox,
  2302. struct mlx4_cmd_mailbox *outbox,
  2303. struct mlx4_cmd_info *cmd)
  2304. {
  2305. int err;
  2306. struct mlx4_qp_context *context = inbox->buf + 8;
  2307. err = verify_qp_parameters(dev, inbox, QP_TRANS_RTS2RTS, slave);
  2308. if (err)
  2309. return err;
  2310. update_pkey_index(dev, slave, inbox);
  2311. update_gid(dev, inbox, (u8)slave);
  2312. adjust_proxy_tun_qkey(dev, vhcr, context);
  2313. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2314. }
  2315. int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
  2316. struct mlx4_vhcr *vhcr,
  2317. struct mlx4_cmd_mailbox *inbox,
  2318. struct mlx4_cmd_mailbox *outbox,
  2319. struct mlx4_cmd_info *cmd)
  2320. {
  2321. struct mlx4_qp_context *context = inbox->buf + 8;
  2322. adjust_proxy_tun_qkey(dev, vhcr, context);
  2323. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2324. }
  2325. int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
  2326. struct mlx4_vhcr *vhcr,
  2327. struct mlx4_cmd_mailbox *inbox,
  2328. struct mlx4_cmd_mailbox *outbox,
  2329. struct mlx4_cmd_info *cmd)
  2330. {
  2331. int err;
  2332. struct mlx4_qp_context *context = inbox->buf + 8;
  2333. err = verify_qp_parameters(dev, inbox, QP_TRANS_SQD2SQD, slave);
  2334. if (err)
  2335. return err;
  2336. adjust_proxy_tun_qkey(dev, vhcr, context);
  2337. update_gid(dev, inbox, (u8)slave);
  2338. update_pkey_index(dev, slave, inbox);
  2339. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2340. }
  2341. int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
  2342. struct mlx4_vhcr *vhcr,
  2343. struct mlx4_cmd_mailbox *inbox,
  2344. struct mlx4_cmd_mailbox *outbox,
  2345. struct mlx4_cmd_info *cmd)
  2346. {
  2347. int err;
  2348. struct mlx4_qp_context *context = inbox->buf + 8;
  2349. err = verify_qp_parameters(dev, inbox, QP_TRANS_SQD2RTS, slave);
  2350. if (err)
  2351. return err;
  2352. adjust_proxy_tun_qkey(dev, vhcr, context);
  2353. update_gid(dev, inbox, (u8)slave);
  2354. update_pkey_index(dev, slave, inbox);
  2355. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2356. }
  2357. int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
  2358. struct mlx4_vhcr *vhcr,
  2359. struct mlx4_cmd_mailbox *inbox,
  2360. struct mlx4_cmd_mailbox *outbox,
  2361. struct mlx4_cmd_info *cmd)
  2362. {
  2363. int err;
  2364. int qpn = vhcr->in_modifier & 0x7fffff;
  2365. struct res_qp *qp;
  2366. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED, &qp, 0);
  2367. if (err)
  2368. return err;
  2369. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2370. if (err)
  2371. goto ex_abort;
  2372. atomic_dec(&qp->mtt->ref_count);
  2373. atomic_dec(&qp->rcq->ref_count);
  2374. atomic_dec(&qp->scq->ref_count);
  2375. if (qp->srq)
  2376. atomic_dec(&qp->srq->ref_count);
  2377. res_end_move(dev, slave, RES_QP, qpn);
  2378. return 0;
  2379. ex_abort:
  2380. res_abort_move(dev, slave, RES_QP, qpn);
  2381. return err;
  2382. }
  2383. static struct res_gid *find_gid(struct mlx4_dev *dev, int slave,
  2384. struct res_qp *rqp, u8 *gid)
  2385. {
  2386. struct res_gid *res;
  2387. list_for_each_entry(res, &rqp->mcg_list, list) {
  2388. if (!memcmp(res->gid, gid, 16))
  2389. return res;
  2390. }
  2391. return NULL;
  2392. }
  2393. static int add_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  2394. u8 *gid, enum mlx4_protocol prot,
  2395. enum mlx4_steer_type steer)
  2396. {
  2397. struct res_gid *res;
  2398. int err;
  2399. res = kzalloc(sizeof *res, GFP_KERNEL);
  2400. if (!res)
  2401. return -ENOMEM;
  2402. spin_lock_irq(&rqp->mcg_spl);
  2403. if (find_gid(dev, slave, rqp, gid)) {
  2404. kfree(res);
  2405. err = -EEXIST;
  2406. } else {
  2407. memcpy(res->gid, gid, 16);
  2408. res->prot = prot;
  2409. res->steer = steer;
  2410. list_add_tail(&res->list, &rqp->mcg_list);
  2411. err = 0;
  2412. }
  2413. spin_unlock_irq(&rqp->mcg_spl);
  2414. return err;
  2415. }
  2416. static int rem_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  2417. u8 *gid, enum mlx4_protocol prot,
  2418. enum mlx4_steer_type steer)
  2419. {
  2420. struct res_gid *res;
  2421. int err;
  2422. spin_lock_irq(&rqp->mcg_spl);
  2423. res = find_gid(dev, slave, rqp, gid);
  2424. if (!res || res->prot != prot || res->steer != steer)
  2425. err = -EINVAL;
  2426. else {
  2427. list_del(&res->list);
  2428. kfree(res);
  2429. err = 0;
  2430. }
  2431. spin_unlock_irq(&rqp->mcg_spl);
  2432. return err;
  2433. }
  2434. int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
  2435. struct mlx4_vhcr *vhcr,
  2436. struct mlx4_cmd_mailbox *inbox,
  2437. struct mlx4_cmd_mailbox *outbox,
  2438. struct mlx4_cmd_info *cmd)
  2439. {
  2440. struct mlx4_qp qp; /* dummy for calling attach/detach */
  2441. u8 *gid = inbox->buf;
  2442. enum mlx4_protocol prot = (vhcr->in_modifier >> 28) & 0x7;
  2443. int err;
  2444. int qpn;
  2445. struct res_qp *rqp;
  2446. int attach = vhcr->op_modifier;
  2447. int block_loopback = vhcr->in_modifier >> 31;
  2448. u8 steer_type_mask = 2;
  2449. enum mlx4_steer_type type = (gid[7] & steer_type_mask) >> 1;
  2450. qpn = vhcr->in_modifier & 0xffffff;
  2451. err = get_res(dev, slave, qpn, RES_QP, &rqp);
  2452. if (err)
  2453. return err;
  2454. qp.qpn = qpn;
  2455. if (attach) {
  2456. err = add_mcg_res(dev, slave, rqp, gid, prot, type);
  2457. if (err)
  2458. goto ex_put;
  2459. err = mlx4_qp_attach_common(dev, &qp, gid,
  2460. block_loopback, prot, type);
  2461. if (err)
  2462. goto ex_rem;
  2463. } else {
  2464. err = rem_mcg_res(dev, slave, rqp, gid, prot, type);
  2465. if (err)
  2466. goto ex_put;
  2467. err = mlx4_qp_detach_common(dev, &qp, gid, prot, type);
  2468. }
  2469. put_res(dev, slave, qpn, RES_QP);
  2470. return 0;
  2471. ex_rem:
  2472. /* ignore error return below, already in error */
  2473. (void) rem_mcg_res(dev, slave, rqp, gid, prot, type);
  2474. ex_put:
  2475. put_res(dev, slave, qpn, RES_QP);
  2476. return err;
  2477. }
  2478. /*
  2479. * MAC validation for Flow Steering rules.
  2480. * VF can attach rules only with a mac address which is assigned to it.
  2481. */
  2482. static int validate_eth_header_mac(int slave, struct _rule_hw *eth_header,
  2483. struct list_head *rlist)
  2484. {
  2485. struct mac_res *res, *tmp;
  2486. __be64 be_mac;
  2487. /* make sure it isn't multicast or broadcast mac*/
  2488. if (!is_multicast_ether_addr(eth_header->eth.dst_mac) &&
  2489. !is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
  2490. list_for_each_entry_safe(res, tmp, rlist, list) {
  2491. be_mac = cpu_to_be64(res->mac << 16);
  2492. if (!memcmp(&be_mac, eth_header->eth.dst_mac, ETH_ALEN))
  2493. return 0;
  2494. }
  2495. pr_err("MAC %pM doesn't belong to VF %d, Steering rule rejected\n",
  2496. eth_header->eth.dst_mac, slave);
  2497. return -EINVAL;
  2498. }
  2499. return 0;
  2500. }
  2501. /*
  2502. * In case of missing eth header, append eth header with a MAC address
  2503. * assigned to the VF.
  2504. */
  2505. static int add_eth_header(struct mlx4_dev *dev, int slave,
  2506. struct mlx4_cmd_mailbox *inbox,
  2507. struct list_head *rlist, int header_id)
  2508. {
  2509. struct mac_res *res, *tmp;
  2510. u8 port;
  2511. struct mlx4_net_trans_rule_hw_ctrl *ctrl;
  2512. struct mlx4_net_trans_rule_hw_eth *eth_header;
  2513. struct mlx4_net_trans_rule_hw_ipv4 *ip_header;
  2514. struct mlx4_net_trans_rule_hw_tcp_udp *l4_header;
  2515. __be64 be_mac = 0;
  2516. __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16);
  2517. ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
  2518. port = be32_to_cpu(ctrl->vf_vep_port) & 0xff;
  2519. eth_header = (struct mlx4_net_trans_rule_hw_eth *)(ctrl + 1);
  2520. /* Clear a space in the inbox for eth header */
  2521. switch (header_id) {
  2522. case MLX4_NET_TRANS_RULE_ID_IPV4:
  2523. ip_header =
  2524. (struct mlx4_net_trans_rule_hw_ipv4 *)(eth_header + 1);
  2525. memmove(ip_header, eth_header,
  2526. sizeof(*ip_header) + sizeof(*l4_header));
  2527. break;
  2528. case MLX4_NET_TRANS_RULE_ID_TCP:
  2529. case MLX4_NET_TRANS_RULE_ID_UDP:
  2530. l4_header = (struct mlx4_net_trans_rule_hw_tcp_udp *)
  2531. (eth_header + 1);
  2532. memmove(l4_header, eth_header, sizeof(*l4_header));
  2533. break;
  2534. default:
  2535. return -EINVAL;
  2536. }
  2537. list_for_each_entry_safe(res, tmp, rlist, list) {
  2538. if (port == res->port) {
  2539. be_mac = cpu_to_be64(res->mac << 16);
  2540. break;
  2541. }
  2542. }
  2543. if (!be_mac) {
  2544. pr_err("Failed adding eth header to FS rule, Can't find matching MAC for port %d .\n",
  2545. port);
  2546. return -EINVAL;
  2547. }
  2548. memset(eth_header, 0, sizeof(*eth_header));
  2549. eth_header->size = sizeof(*eth_header) >> 2;
  2550. eth_header->id = cpu_to_be16(__sw_id_hw[MLX4_NET_TRANS_RULE_ID_ETH]);
  2551. memcpy(eth_header->dst_mac, &be_mac, ETH_ALEN);
  2552. memcpy(eth_header->dst_mac_msk, &mac_msk, ETH_ALEN);
  2553. return 0;
  2554. }
  2555. int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
  2556. struct mlx4_vhcr *vhcr,
  2557. struct mlx4_cmd_mailbox *inbox,
  2558. struct mlx4_cmd_mailbox *outbox,
  2559. struct mlx4_cmd_info *cmd)
  2560. {
  2561. struct mlx4_priv *priv = mlx4_priv(dev);
  2562. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2563. struct list_head *rlist = &tracker->slave_list[slave].res_list[RES_MAC];
  2564. int err;
  2565. int qpn;
  2566. struct mlx4_net_trans_rule_hw_ctrl *ctrl;
  2567. struct _rule_hw *rule_header;
  2568. int header_id;
  2569. if (dev->caps.steering_mode !=
  2570. MLX4_STEERING_MODE_DEVICE_MANAGED)
  2571. return -EOPNOTSUPP;
  2572. ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
  2573. qpn = be32_to_cpu(ctrl->qpn) & 0xffffff;
  2574. err = get_res(dev, slave, qpn, RES_QP, NULL);
  2575. if (err) {
  2576. pr_err("Steering rule with qpn 0x%x rejected.\n", qpn);
  2577. return err;
  2578. }
  2579. rule_header = (struct _rule_hw *)(ctrl + 1);
  2580. header_id = map_hw_to_sw_id(be16_to_cpu(rule_header->id));
  2581. switch (header_id) {
  2582. case MLX4_NET_TRANS_RULE_ID_ETH:
  2583. if (validate_eth_header_mac(slave, rule_header, rlist)) {
  2584. err = -EINVAL;
  2585. goto err_put;
  2586. }
  2587. break;
  2588. case MLX4_NET_TRANS_RULE_ID_IB:
  2589. break;
  2590. case MLX4_NET_TRANS_RULE_ID_IPV4:
  2591. case MLX4_NET_TRANS_RULE_ID_TCP:
  2592. case MLX4_NET_TRANS_RULE_ID_UDP:
  2593. pr_warn("Can't attach FS rule without L2 headers, adding L2 header.\n");
  2594. if (add_eth_header(dev, slave, inbox, rlist, header_id)) {
  2595. err = -EINVAL;
  2596. goto err_put;
  2597. }
  2598. vhcr->in_modifier +=
  2599. sizeof(struct mlx4_net_trans_rule_hw_eth) >> 2;
  2600. break;
  2601. default:
  2602. pr_err("Corrupted mailbox.\n");
  2603. err = -EINVAL;
  2604. goto err_put;
  2605. }
  2606. err = mlx4_cmd_imm(dev, inbox->dma, &vhcr->out_param,
  2607. vhcr->in_modifier, 0,
  2608. MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
  2609. MLX4_CMD_NATIVE);
  2610. if (err)
  2611. goto err_put;
  2612. err = add_res_range(dev, slave, vhcr->out_param, 1, RES_FS_RULE, 0);
  2613. if (err) {
  2614. mlx4_err(dev, "Fail to add flow steering resources.\n ");
  2615. /* detach rule*/
  2616. mlx4_cmd(dev, vhcr->out_param, 0, 0,
  2617. MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
  2618. MLX4_CMD_NATIVE);
  2619. }
  2620. err_put:
  2621. put_res(dev, slave, qpn, RES_QP);
  2622. return err;
  2623. }
  2624. int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
  2625. struct mlx4_vhcr *vhcr,
  2626. struct mlx4_cmd_mailbox *inbox,
  2627. struct mlx4_cmd_mailbox *outbox,
  2628. struct mlx4_cmd_info *cmd)
  2629. {
  2630. int err;
  2631. if (dev->caps.steering_mode !=
  2632. MLX4_STEERING_MODE_DEVICE_MANAGED)
  2633. return -EOPNOTSUPP;
  2634. err = rem_res_range(dev, slave, vhcr->in_param, 1, RES_FS_RULE, 0);
  2635. if (err) {
  2636. mlx4_err(dev, "Fail to remove flow steering resources.\n ");
  2637. return err;
  2638. }
  2639. err = mlx4_cmd(dev, vhcr->in_param, 0, 0,
  2640. MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
  2641. MLX4_CMD_NATIVE);
  2642. return err;
  2643. }
  2644. enum {
  2645. BUSY_MAX_RETRIES = 10
  2646. };
  2647. int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
  2648. struct mlx4_vhcr *vhcr,
  2649. struct mlx4_cmd_mailbox *inbox,
  2650. struct mlx4_cmd_mailbox *outbox,
  2651. struct mlx4_cmd_info *cmd)
  2652. {
  2653. int err;
  2654. int index = vhcr->in_modifier & 0xffff;
  2655. err = get_res(dev, slave, index, RES_COUNTER, NULL);
  2656. if (err)
  2657. return err;
  2658. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2659. put_res(dev, slave, index, RES_COUNTER);
  2660. return err;
  2661. }
  2662. static void detach_qp(struct mlx4_dev *dev, int slave, struct res_qp *rqp)
  2663. {
  2664. struct res_gid *rgid;
  2665. struct res_gid *tmp;
  2666. struct mlx4_qp qp; /* dummy for calling attach/detach */
  2667. list_for_each_entry_safe(rgid, tmp, &rqp->mcg_list, list) {
  2668. qp.qpn = rqp->local_qpn;
  2669. (void) mlx4_qp_detach_common(dev, &qp, rgid->gid, rgid->prot,
  2670. rgid->steer);
  2671. list_del(&rgid->list);
  2672. kfree(rgid);
  2673. }
  2674. }
  2675. static int _move_all_busy(struct mlx4_dev *dev, int slave,
  2676. enum mlx4_resource type, int print)
  2677. {
  2678. struct mlx4_priv *priv = mlx4_priv(dev);
  2679. struct mlx4_resource_tracker *tracker =
  2680. &priv->mfunc.master.res_tracker;
  2681. struct list_head *rlist = &tracker->slave_list[slave].res_list[type];
  2682. struct res_common *r;
  2683. struct res_common *tmp;
  2684. int busy;
  2685. busy = 0;
  2686. spin_lock_irq(mlx4_tlock(dev));
  2687. list_for_each_entry_safe(r, tmp, rlist, list) {
  2688. if (r->owner == slave) {
  2689. if (!r->removing) {
  2690. if (r->state == RES_ANY_BUSY) {
  2691. if (print)
  2692. mlx4_dbg(dev,
  2693. "%s id 0x%llx is busy\n",
  2694. ResourceType(type),
  2695. r->res_id);
  2696. ++busy;
  2697. } else {
  2698. r->from_state = r->state;
  2699. r->state = RES_ANY_BUSY;
  2700. r->removing = 1;
  2701. }
  2702. }
  2703. }
  2704. }
  2705. spin_unlock_irq(mlx4_tlock(dev));
  2706. return busy;
  2707. }
  2708. static int move_all_busy(struct mlx4_dev *dev, int slave,
  2709. enum mlx4_resource type)
  2710. {
  2711. unsigned long begin;
  2712. int busy;
  2713. begin = jiffies;
  2714. do {
  2715. busy = _move_all_busy(dev, slave, type, 0);
  2716. if (time_after(jiffies, begin + 5 * HZ))
  2717. break;
  2718. if (busy)
  2719. cond_resched();
  2720. } while (busy);
  2721. if (busy)
  2722. busy = _move_all_busy(dev, slave, type, 1);
  2723. return busy;
  2724. }
  2725. static void rem_slave_qps(struct mlx4_dev *dev, int slave)
  2726. {
  2727. struct mlx4_priv *priv = mlx4_priv(dev);
  2728. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2729. struct list_head *qp_list =
  2730. &tracker->slave_list[slave].res_list[RES_QP];
  2731. struct res_qp *qp;
  2732. struct res_qp *tmp;
  2733. int state;
  2734. u64 in_param;
  2735. int qpn;
  2736. int err;
  2737. err = move_all_busy(dev, slave, RES_QP);
  2738. if (err)
  2739. mlx4_warn(dev, "rem_slave_qps: Could not move all qps to busy"
  2740. "for slave %d\n", slave);
  2741. spin_lock_irq(mlx4_tlock(dev));
  2742. list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
  2743. spin_unlock_irq(mlx4_tlock(dev));
  2744. if (qp->com.owner == slave) {
  2745. qpn = qp->com.res_id;
  2746. detach_qp(dev, slave, qp);
  2747. state = qp->com.from_state;
  2748. while (state != 0) {
  2749. switch (state) {
  2750. case RES_QP_RESERVED:
  2751. spin_lock_irq(mlx4_tlock(dev));
  2752. rb_erase(&qp->com.node,
  2753. &tracker->res_tree[RES_QP]);
  2754. list_del(&qp->com.list);
  2755. spin_unlock_irq(mlx4_tlock(dev));
  2756. kfree(qp);
  2757. state = 0;
  2758. break;
  2759. case RES_QP_MAPPED:
  2760. if (!valid_reserved(dev, slave, qpn))
  2761. __mlx4_qp_free_icm(dev, qpn);
  2762. state = RES_QP_RESERVED;
  2763. break;
  2764. case RES_QP_HW:
  2765. in_param = slave;
  2766. err = mlx4_cmd(dev, in_param,
  2767. qp->local_qpn, 2,
  2768. MLX4_CMD_2RST_QP,
  2769. MLX4_CMD_TIME_CLASS_A,
  2770. MLX4_CMD_NATIVE);
  2771. if (err)
  2772. mlx4_dbg(dev, "rem_slave_qps: failed"
  2773. " to move slave %d qpn %d to"
  2774. " reset\n", slave,
  2775. qp->local_qpn);
  2776. atomic_dec(&qp->rcq->ref_count);
  2777. atomic_dec(&qp->scq->ref_count);
  2778. atomic_dec(&qp->mtt->ref_count);
  2779. if (qp->srq)
  2780. atomic_dec(&qp->srq->ref_count);
  2781. state = RES_QP_MAPPED;
  2782. break;
  2783. default:
  2784. state = 0;
  2785. }
  2786. }
  2787. }
  2788. spin_lock_irq(mlx4_tlock(dev));
  2789. }
  2790. spin_unlock_irq(mlx4_tlock(dev));
  2791. }
  2792. static void rem_slave_srqs(struct mlx4_dev *dev, int slave)
  2793. {
  2794. struct mlx4_priv *priv = mlx4_priv(dev);
  2795. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2796. struct list_head *srq_list =
  2797. &tracker->slave_list[slave].res_list[RES_SRQ];
  2798. struct res_srq *srq;
  2799. struct res_srq *tmp;
  2800. int state;
  2801. u64 in_param;
  2802. LIST_HEAD(tlist);
  2803. int srqn;
  2804. int err;
  2805. err = move_all_busy(dev, slave, RES_SRQ);
  2806. if (err)
  2807. mlx4_warn(dev, "rem_slave_srqs: Could not move all srqs to "
  2808. "busy for slave %d\n", slave);
  2809. spin_lock_irq(mlx4_tlock(dev));
  2810. list_for_each_entry_safe(srq, tmp, srq_list, com.list) {
  2811. spin_unlock_irq(mlx4_tlock(dev));
  2812. if (srq->com.owner == slave) {
  2813. srqn = srq->com.res_id;
  2814. state = srq->com.from_state;
  2815. while (state != 0) {
  2816. switch (state) {
  2817. case RES_SRQ_ALLOCATED:
  2818. __mlx4_srq_free_icm(dev, srqn);
  2819. spin_lock_irq(mlx4_tlock(dev));
  2820. rb_erase(&srq->com.node,
  2821. &tracker->res_tree[RES_SRQ]);
  2822. list_del(&srq->com.list);
  2823. spin_unlock_irq(mlx4_tlock(dev));
  2824. kfree(srq);
  2825. state = 0;
  2826. break;
  2827. case RES_SRQ_HW:
  2828. in_param = slave;
  2829. err = mlx4_cmd(dev, in_param, srqn, 1,
  2830. MLX4_CMD_HW2SW_SRQ,
  2831. MLX4_CMD_TIME_CLASS_A,
  2832. MLX4_CMD_NATIVE);
  2833. if (err)
  2834. mlx4_dbg(dev, "rem_slave_srqs: failed"
  2835. " to move slave %d srq %d to"
  2836. " SW ownership\n",
  2837. slave, srqn);
  2838. atomic_dec(&srq->mtt->ref_count);
  2839. if (srq->cq)
  2840. atomic_dec(&srq->cq->ref_count);
  2841. state = RES_SRQ_ALLOCATED;
  2842. break;
  2843. default:
  2844. state = 0;
  2845. }
  2846. }
  2847. }
  2848. spin_lock_irq(mlx4_tlock(dev));
  2849. }
  2850. spin_unlock_irq(mlx4_tlock(dev));
  2851. }
  2852. static void rem_slave_cqs(struct mlx4_dev *dev, int slave)
  2853. {
  2854. struct mlx4_priv *priv = mlx4_priv(dev);
  2855. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2856. struct list_head *cq_list =
  2857. &tracker->slave_list[slave].res_list[RES_CQ];
  2858. struct res_cq *cq;
  2859. struct res_cq *tmp;
  2860. int state;
  2861. u64 in_param;
  2862. LIST_HEAD(tlist);
  2863. int cqn;
  2864. int err;
  2865. err = move_all_busy(dev, slave, RES_CQ);
  2866. if (err)
  2867. mlx4_warn(dev, "rem_slave_cqs: Could not move all cqs to "
  2868. "busy for slave %d\n", slave);
  2869. spin_lock_irq(mlx4_tlock(dev));
  2870. list_for_each_entry_safe(cq, tmp, cq_list, com.list) {
  2871. spin_unlock_irq(mlx4_tlock(dev));
  2872. if (cq->com.owner == slave && !atomic_read(&cq->ref_count)) {
  2873. cqn = cq->com.res_id;
  2874. state = cq->com.from_state;
  2875. while (state != 0) {
  2876. switch (state) {
  2877. case RES_CQ_ALLOCATED:
  2878. __mlx4_cq_free_icm(dev, cqn);
  2879. spin_lock_irq(mlx4_tlock(dev));
  2880. rb_erase(&cq->com.node,
  2881. &tracker->res_tree[RES_CQ]);
  2882. list_del(&cq->com.list);
  2883. spin_unlock_irq(mlx4_tlock(dev));
  2884. kfree(cq);
  2885. state = 0;
  2886. break;
  2887. case RES_CQ_HW:
  2888. in_param = slave;
  2889. err = mlx4_cmd(dev, in_param, cqn, 1,
  2890. MLX4_CMD_HW2SW_CQ,
  2891. MLX4_CMD_TIME_CLASS_A,
  2892. MLX4_CMD_NATIVE);
  2893. if (err)
  2894. mlx4_dbg(dev, "rem_slave_cqs: failed"
  2895. " to move slave %d cq %d to"
  2896. " SW ownership\n",
  2897. slave, cqn);
  2898. atomic_dec(&cq->mtt->ref_count);
  2899. state = RES_CQ_ALLOCATED;
  2900. break;
  2901. default:
  2902. state = 0;
  2903. }
  2904. }
  2905. }
  2906. spin_lock_irq(mlx4_tlock(dev));
  2907. }
  2908. spin_unlock_irq(mlx4_tlock(dev));
  2909. }
  2910. static void rem_slave_mrs(struct mlx4_dev *dev, int slave)
  2911. {
  2912. struct mlx4_priv *priv = mlx4_priv(dev);
  2913. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2914. struct list_head *mpt_list =
  2915. &tracker->slave_list[slave].res_list[RES_MPT];
  2916. struct res_mpt *mpt;
  2917. struct res_mpt *tmp;
  2918. int state;
  2919. u64 in_param;
  2920. LIST_HEAD(tlist);
  2921. int mptn;
  2922. int err;
  2923. err = move_all_busy(dev, slave, RES_MPT);
  2924. if (err)
  2925. mlx4_warn(dev, "rem_slave_mrs: Could not move all mpts to "
  2926. "busy for slave %d\n", slave);
  2927. spin_lock_irq(mlx4_tlock(dev));
  2928. list_for_each_entry_safe(mpt, tmp, mpt_list, com.list) {
  2929. spin_unlock_irq(mlx4_tlock(dev));
  2930. if (mpt->com.owner == slave) {
  2931. mptn = mpt->com.res_id;
  2932. state = mpt->com.from_state;
  2933. while (state != 0) {
  2934. switch (state) {
  2935. case RES_MPT_RESERVED:
  2936. __mlx4_mr_release(dev, mpt->key);
  2937. spin_lock_irq(mlx4_tlock(dev));
  2938. rb_erase(&mpt->com.node,
  2939. &tracker->res_tree[RES_MPT]);
  2940. list_del(&mpt->com.list);
  2941. spin_unlock_irq(mlx4_tlock(dev));
  2942. kfree(mpt);
  2943. state = 0;
  2944. break;
  2945. case RES_MPT_MAPPED:
  2946. __mlx4_mr_free_icm(dev, mpt->key);
  2947. state = RES_MPT_RESERVED;
  2948. break;
  2949. case RES_MPT_HW:
  2950. in_param = slave;
  2951. err = mlx4_cmd(dev, in_param, mptn, 0,
  2952. MLX4_CMD_HW2SW_MPT,
  2953. MLX4_CMD_TIME_CLASS_A,
  2954. MLX4_CMD_NATIVE);
  2955. if (err)
  2956. mlx4_dbg(dev, "rem_slave_mrs: failed"
  2957. " to move slave %d mpt %d to"
  2958. " SW ownership\n",
  2959. slave, mptn);
  2960. if (mpt->mtt)
  2961. atomic_dec(&mpt->mtt->ref_count);
  2962. state = RES_MPT_MAPPED;
  2963. break;
  2964. default:
  2965. state = 0;
  2966. }
  2967. }
  2968. }
  2969. spin_lock_irq(mlx4_tlock(dev));
  2970. }
  2971. spin_unlock_irq(mlx4_tlock(dev));
  2972. }
  2973. static void rem_slave_mtts(struct mlx4_dev *dev, int slave)
  2974. {
  2975. struct mlx4_priv *priv = mlx4_priv(dev);
  2976. struct mlx4_resource_tracker *tracker =
  2977. &priv->mfunc.master.res_tracker;
  2978. struct list_head *mtt_list =
  2979. &tracker->slave_list[slave].res_list[RES_MTT];
  2980. struct res_mtt *mtt;
  2981. struct res_mtt *tmp;
  2982. int state;
  2983. LIST_HEAD(tlist);
  2984. int base;
  2985. int err;
  2986. err = move_all_busy(dev, slave, RES_MTT);
  2987. if (err)
  2988. mlx4_warn(dev, "rem_slave_mtts: Could not move all mtts to "
  2989. "busy for slave %d\n", slave);
  2990. spin_lock_irq(mlx4_tlock(dev));
  2991. list_for_each_entry_safe(mtt, tmp, mtt_list, com.list) {
  2992. spin_unlock_irq(mlx4_tlock(dev));
  2993. if (mtt->com.owner == slave) {
  2994. base = mtt->com.res_id;
  2995. state = mtt->com.from_state;
  2996. while (state != 0) {
  2997. switch (state) {
  2998. case RES_MTT_ALLOCATED:
  2999. __mlx4_free_mtt_range(dev, base,
  3000. mtt->order);
  3001. spin_lock_irq(mlx4_tlock(dev));
  3002. rb_erase(&mtt->com.node,
  3003. &tracker->res_tree[RES_MTT]);
  3004. list_del(&mtt->com.list);
  3005. spin_unlock_irq(mlx4_tlock(dev));
  3006. kfree(mtt);
  3007. state = 0;
  3008. break;
  3009. default:
  3010. state = 0;
  3011. }
  3012. }
  3013. }
  3014. spin_lock_irq(mlx4_tlock(dev));
  3015. }
  3016. spin_unlock_irq(mlx4_tlock(dev));
  3017. }
  3018. static void rem_slave_fs_rule(struct mlx4_dev *dev, int slave)
  3019. {
  3020. struct mlx4_priv *priv = mlx4_priv(dev);
  3021. struct mlx4_resource_tracker *tracker =
  3022. &priv->mfunc.master.res_tracker;
  3023. struct list_head *fs_rule_list =
  3024. &tracker->slave_list[slave].res_list[RES_FS_RULE];
  3025. struct res_fs_rule *fs_rule;
  3026. struct res_fs_rule *tmp;
  3027. int state;
  3028. u64 base;
  3029. int err;
  3030. err = move_all_busy(dev, slave, RES_FS_RULE);
  3031. if (err)
  3032. mlx4_warn(dev, "rem_slave_fs_rule: Could not move all mtts to busy for slave %d\n",
  3033. slave);
  3034. spin_lock_irq(mlx4_tlock(dev));
  3035. list_for_each_entry_safe(fs_rule, tmp, fs_rule_list, com.list) {
  3036. spin_unlock_irq(mlx4_tlock(dev));
  3037. if (fs_rule->com.owner == slave) {
  3038. base = fs_rule->com.res_id;
  3039. state = fs_rule->com.from_state;
  3040. while (state != 0) {
  3041. switch (state) {
  3042. case RES_FS_RULE_ALLOCATED:
  3043. /* detach rule */
  3044. err = mlx4_cmd(dev, base, 0, 0,
  3045. MLX4_QP_FLOW_STEERING_DETACH,
  3046. MLX4_CMD_TIME_CLASS_A,
  3047. MLX4_CMD_NATIVE);
  3048. spin_lock_irq(mlx4_tlock(dev));
  3049. rb_erase(&fs_rule->com.node,
  3050. &tracker->res_tree[RES_FS_RULE]);
  3051. list_del(&fs_rule->com.list);
  3052. spin_unlock_irq(mlx4_tlock(dev));
  3053. kfree(fs_rule);
  3054. state = 0;
  3055. break;
  3056. default:
  3057. state = 0;
  3058. }
  3059. }
  3060. }
  3061. spin_lock_irq(mlx4_tlock(dev));
  3062. }
  3063. spin_unlock_irq(mlx4_tlock(dev));
  3064. }
  3065. static void rem_slave_eqs(struct mlx4_dev *dev, int slave)
  3066. {
  3067. struct mlx4_priv *priv = mlx4_priv(dev);
  3068. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3069. struct list_head *eq_list =
  3070. &tracker->slave_list[slave].res_list[RES_EQ];
  3071. struct res_eq *eq;
  3072. struct res_eq *tmp;
  3073. int err;
  3074. int state;
  3075. LIST_HEAD(tlist);
  3076. int eqn;
  3077. struct mlx4_cmd_mailbox *mailbox;
  3078. err = move_all_busy(dev, slave, RES_EQ);
  3079. if (err)
  3080. mlx4_warn(dev, "rem_slave_eqs: Could not move all eqs to "
  3081. "busy for slave %d\n", slave);
  3082. spin_lock_irq(mlx4_tlock(dev));
  3083. list_for_each_entry_safe(eq, tmp, eq_list, com.list) {
  3084. spin_unlock_irq(mlx4_tlock(dev));
  3085. if (eq->com.owner == slave) {
  3086. eqn = eq->com.res_id;
  3087. state = eq->com.from_state;
  3088. while (state != 0) {
  3089. switch (state) {
  3090. case RES_EQ_RESERVED:
  3091. spin_lock_irq(mlx4_tlock(dev));
  3092. rb_erase(&eq->com.node,
  3093. &tracker->res_tree[RES_EQ]);
  3094. list_del(&eq->com.list);
  3095. spin_unlock_irq(mlx4_tlock(dev));
  3096. kfree(eq);
  3097. state = 0;
  3098. break;
  3099. case RES_EQ_HW:
  3100. mailbox = mlx4_alloc_cmd_mailbox(dev);
  3101. if (IS_ERR(mailbox)) {
  3102. cond_resched();
  3103. continue;
  3104. }
  3105. err = mlx4_cmd_box(dev, slave, 0,
  3106. eqn & 0xff, 0,
  3107. MLX4_CMD_HW2SW_EQ,
  3108. MLX4_CMD_TIME_CLASS_A,
  3109. MLX4_CMD_NATIVE);
  3110. if (err)
  3111. mlx4_dbg(dev, "rem_slave_eqs: failed"
  3112. " to move slave %d eqs %d to"
  3113. " SW ownership\n", slave, eqn);
  3114. mlx4_free_cmd_mailbox(dev, mailbox);
  3115. atomic_dec(&eq->mtt->ref_count);
  3116. state = RES_EQ_RESERVED;
  3117. break;
  3118. default:
  3119. state = 0;
  3120. }
  3121. }
  3122. }
  3123. spin_lock_irq(mlx4_tlock(dev));
  3124. }
  3125. spin_unlock_irq(mlx4_tlock(dev));
  3126. }
  3127. static void rem_slave_counters(struct mlx4_dev *dev, int slave)
  3128. {
  3129. struct mlx4_priv *priv = mlx4_priv(dev);
  3130. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3131. struct list_head *counter_list =
  3132. &tracker->slave_list[slave].res_list[RES_COUNTER];
  3133. struct res_counter *counter;
  3134. struct res_counter *tmp;
  3135. int err;
  3136. int index;
  3137. err = move_all_busy(dev, slave, RES_COUNTER);
  3138. if (err)
  3139. mlx4_warn(dev, "rem_slave_counters: Could not move all counters to "
  3140. "busy for slave %d\n", slave);
  3141. spin_lock_irq(mlx4_tlock(dev));
  3142. list_for_each_entry_safe(counter, tmp, counter_list, com.list) {
  3143. if (counter->com.owner == slave) {
  3144. index = counter->com.res_id;
  3145. rb_erase(&counter->com.node,
  3146. &tracker->res_tree[RES_COUNTER]);
  3147. list_del(&counter->com.list);
  3148. kfree(counter);
  3149. __mlx4_counter_free(dev, index);
  3150. }
  3151. }
  3152. spin_unlock_irq(mlx4_tlock(dev));
  3153. }
  3154. static void rem_slave_xrcdns(struct mlx4_dev *dev, int slave)
  3155. {
  3156. struct mlx4_priv *priv = mlx4_priv(dev);
  3157. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3158. struct list_head *xrcdn_list =
  3159. &tracker->slave_list[slave].res_list[RES_XRCD];
  3160. struct res_xrcdn *xrcd;
  3161. struct res_xrcdn *tmp;
  3162. int err;
  3163. int xrcdn;
  3164. err = move_all_busy(dev, slave, RES_XRCD);
  3165. if (err)
  3166. mlx4_warn(dev, "rem_slave_xrcdns: Could not move all xrcdns to "
  3167. "busy for slave %d\n", slave);
  3168. spin_lock_irq(mlx4_tlock(dev));
  3169. list_for_each_entry_safe(xrcd, tmp, xrcdn_list, com.list) {
  3170. if (xrcd->com.owner == slave) {
  3171. xrcdn = xrcd->com.res_id;
  3172. rb_erase(&xrcd->com.node, &tracker->res_tree[RES_XRCD]);
  3173. list_del(&xrcd->com.list);
  3174. kfree(xrcd);
  3175. __mlx4_xrcd_free(dev, xrcdn);
  3176. }
  3177. }
  3178. spin_unlock_irq(mlx4_tlock(dev));
  3179. }
  3180. void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave)
  3181. {
  3182. struct mlx4_priv *priv = mlx4_priv(dev);
  3183. mutex_lock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  3184. /*VLAN*/
  3185. rem_slave_macs(dev, slave);
  3186. rem_slave_qps(dev, slave);
  3187. rem_slave_srqs(dev, slave);
  3188. rem_slave_cqs(dev, slave);
  3189. rem_slave_mrs(dev, slave);
  3190. rem_slave_eqs(dev, slave);
  3191. rem_slave_mtts(dev, slave);
  3192. rem_slave_counters(dev, slave);
  3193. rem_slave_xrcdns(dev, slave);
  3194. rem_slave_fs_rule(dev, slave);
  3195. mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  3196. }