s5p_mfc_common.h 19 KB

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  1. /*
  2. * Samsung S5P Multi Format Codec v 5.0
  3. *
  4. * This file contains definitions of enums and structs used by the codec
  5. * driver.
  6. *
  7. * Copyright (C) 2011 Samsung Electronics Co., Ltd.
  8. * Kamil Debski, <k.debski@samsung.com>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by the
  12. * Free Software Foundation; either version 2 of the
  13. * License, or (at your option) any later version
  14. */
  15. #ifndef S5P_MFC_COMMON_H_
  16. #define S5P_MFC_COMMON_H_
  17. #include <linux/platform_device.h>
  18. #include <linux/videodev2.h>
  19. #include <media/v4l2-ctrls.h>
  20. #include <media/v4l2-device.h>
  21. #include <media/v4l2-ioctl.h>
  22. #include <media/videobuf2-core.h>
  23. #include "regs-mfc.h"
  24. #include "regs-mfc-v6.h"
  25. /* Definitions related to MFC memory */
  26. /* Offset base used to differentiate between CAPTURE and OUTPUT
  27. * while mmaping */
  28. #define DST_QUEUE_OFF_BASE (TASK_SIZE / 2)
  29. #define MFC_BANK1_ALLOC_CTX 0
  30. #define MFC_BANK2_ALLOC_CTX 1
  31. #define MFC_BANK1_ALIGN_ORDER 13
  32. #define MFC_BANK2_ALIGN_ORDER 13
  33. #define MFC_BASE_ALIGN_ORDER 17
  34. #include <media/videobuf2-dma-contig.h>
  35. static inline dma_addr_t s5p_mfc_mem_cookie(void *a, void *b)
  36. {
  37. /* Same functionality as the vb2_dma_contig_plane_paddr */
  38. dma_addr_t *paddr = vb2_dma_contig_memops.cookie(b);
  39. return *paddr;
  40. }
  41. /* MFC definitions */
  42. #define MFC_MAX_EXTRA_DPB 5
  43. #define MFC_MAX_BUFFERS 32
  44. #define MFC_NUM_CONTEXTS 4
  45. /* Interrupt timeout */
  46. #define MFC_INT_TIMEOUT 2000
  47. /* Busy wait timeout */
  48. #define MFC_BW_TIMEOUT 500
  49. /* Watchdog interval */
  50. #define MFC_WATCHDOG_INTERVAL 1000
  51. /* After how many executions watchdog should assume lock up */
  52. #define MFC_WATCHDOG_CNT 10
  53. #define MFC_NO_INSTANCE_SET -1
  54. #define MFC_ENC_CAP_PLANE_COUNT 1
  55. #define MFC_ENC_OUT_PLANE_COUNT 2
  56. #define STUFF_BYTE 4
  57. #define MFC_MAX_CTRLS 70
  58. #define S5P_MFC_CODEC_NONE -1
  59. #define S5P_MFC_CODEC_H264_DEC 0
  60. #define S5P_MFC_CODEC_H264_MVC_DEC 1
  61. #define S5P_MFC_CODEC_VC1_DEC 2
  62. #define S5P_MFC_CODEC_MPEG4_DEC 3
  63. #define S5P_MFC_CODEC_MPEG2_DEC 4
  64. #define S5P_MFC_CODEC_H263_DEC 5
  65. #define S5P_MFC_CODEC_VC1RCV_DEC 6
  66. #define S5P_MFC_CODEC_VP8_DEC 7
  67. #define S5P_MFC_CODEC_H264_ENC 20
  68. #define S5P_MFC_CODEC_H264_MVC_ENC 21
  69. #define S5P_MFC_CODEC_MPEG4_ENC 22
  70. #define S5P_MFC_CODEC_H263_ENC 23
  71. #define S5P_MFC_R2H_CMD_EMPTY 0
  72. #define S5P_MFC_R2H_CMD_SYS_INIT_RET 1
  73. #define S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET 2
  74. #define S5P_MFC_R2H_CMD_SEQ_DONE_RET 3
  75. #define S5P_MFC_R2H_CMD_INIT_BUFFERS_RET 4
  76. #define S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET 6
  77. #define S5P_MFC_R2H_CMD_SLEEP_RET 7
  78. #define S5P_MFC_R2H_CMD_WAKEUP_RET 8
  79. #define S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET 9
  80. #define S5P_MFC_R2H_CMD_DPB_FLUSH_RET 10
  81. #define S5P_MFC_R2H_CMD_NAL_ABORT_RET 11
  82. #define S5P_MFC_R2H_CMD_FW_STATUS_RET 12
  83. #define S5P_MFC_R2H_CMD_FRAME_DONE_RET 13
  84. #define S5P_MFC_R2H_CMD_FIELD_DONE_RET 14
  85. #define S5P_MFC_R2H_CMD_SLICE_DONE_RET 15
  86. #define S5P_MFC_R2H_CMD_ENC_BUFFER_FUL_RET 16
  87. #define S5P_MFC_R2H_CMD_ERR_RET 32
  88. #define mfc_read(dev, offset) readl(dev->regs_base + (offset))
  89. #define mfc_write(dev, data, offset) writel((data), dev->regs_base + \
  90. (offset))
  91. /**
  92. * enum s5p_mfc_fmt_type - type of the pixelformat
  93. */
  94. enum s5p_mfc_fmt_type {
  95. MFC_FMT_DEC,
  96. MFC_FMT_ENC,
  97. MFC_FMT_RAW,
  98. };
  99. /**
  100. * enum s5p_mfc_node_type - The type of an MFC device node.
  101. */
  102. enum s5p_mfc_node_type {
  103. MFCNODE_INVALID = -1,
  104. MFCNODE_DECODER = 0,
  105. MFCNODE_ENCODER = 1,
  106. };
  107. /**
  108. * enum s5p_mfc_inst_type - The type of an MFC instance.
  109. */
  110. enum s5p_mfc_inst_type {
  111. MFCINST_INVALID,
  112. MFCINST_DECODER,
  113. MFCINST_ENCODER,
  114. };
  115. /**
  116. * enum s5p_mfc_inst_state - The state of an MFC instance.
  117. */
  118. enum s5p_mfc_inst_state {
  119. MFCINST_FREE = 0,
  120. MFCINST_INIT = 100,
  121. MFCINST_GOT_INST,
  122. MFCINST_HEAD_PARSED,
  123. MFCINST_BUFS_SET,
  124. MFCINST_RUNNING,
  125. MFCINST_FINISHING,
  126. MFCINST_FINISHED,
  127. MFCINST_RETURN_INST,
  128. MFCINST_ERROR,
  129. MFCINST_ABORT,
  130. MFCINST_RES_CHANGE_INIT,
  131. MFCINST_RES_CHANGE_FLUSH,
  132. MFCINST_RES_CHANGE_END,
  133. };
  134. /**
  135. * enum s5p_mfc_queue_state - The state of buffer queue.
  136. */
  137. enum s5p_mfc_queue_state {
  138. QUEUE_FREE,
  139. QUEUE_BUFS_REQUESTED,
  140. QUEUE_BUFS_QUERIED,
  141. QUEUE_BUFS_MMAPED,
  142. };
  143. /**
  144. * enum s5p_mfc_decode_arg - type of frame decoding
  145. */
  146. enum s5p_mfc_decode_arg {
  147. MFC_DEC_FRAME,
  148. MFC_DEC_LAST_FRAME,
  149. MFC_DEC_RES_CHANGE,
  150. };
  151. #define MFC_BUF_FLAG_USED (1 << 0)
  152. #define MFC_BUF_FLAG_EOS (1 << 1)
  153. struct s5p_mfc_ctx;
  154. /**
  155. * struct s5p_mfc_buf - MFC buffer
  156. */
  157. struct s5p_mfc_buf {
  158. struct list_head list;
  159. struct vb2_buffer *b;
  160. union {
  161. struct {
  162. size_t luma;
  163. size_t chroma;
  164. } raw;
  165. size_t stream;
  166. } cookie;
  167. int flags;
  168. };
  169. /**
  170. * struct s5p_mfc_pm - power management data structure
  171. */
  172. struct s5p_mfc_pm {
  173. struct clk *clock;
  174. struct clk *clock_gate;
  175. atomic_t power;
  176. struct device *device;
  177. };
  178. struct s5p_mfc_buf_size_v5 {
  179. unsigned int h264_ctx;
  180. unsigned int non_h264_ctx;
  181. unsigned int dsc;
  182. unsigned int shm;
  183. };
  184. struct s5p_mfc_buf_size_v6 {
  185. unsigned int dev_ctx;
  186. unsigned int h264_dec_ctx;
  187. unsigned int other_dec_ctx;
  188. unsigned int h264_enc_ctx;
  189. unsigned int other_enc_ctx;
  190. };
  191. struct s5p_mfc_buf_size {
  192. unsigned int fw;
  193. unsigned int cpb;
  194. void *priv;
  195. };
  196. struct s5p_mfc_buf_align {
  197. unsigned int base;
  198. };
  199. struct s5p_mfc_variant {
  200. unsigned int version;
  201. unsigned int port_num;
  202. struct s5p_mfc_buf_size *buf_size;
  203. struct s5p_mfc_buf_align *buf_align;
  204. char *mclk_name;
  205. char *fw_name;
  206. };
  207. /**
  208. * struct s5p_mfc_priv_buf - represents internal used buffer
  209. * @alloc: allocation-specific context for each buffer
  210. * (videobuf2 allocator)
  211. * @ofs: offset of each buffer, will be used for MFC
  212. * @virt: kernel virtual address, only valid when the
  213. * buffer accessed by driver
  214. * @dma: DMA address, only valid when kernel DMA API used
  215. * @size: size of the buffer
  216. */
  217. struct s5p_mfc_priv_buf {
  218. void *alloc;
  219. unsigned long ofs;
  220. void *virt;
  221. dma_addr_t dma;
  222. size_t size;
  223. };
  224. /**
  225. * struct s5p_mfc_dev - The struct containing driver internal parameters.
  226. *
  227. * @v4l2_dev: v4l2_device
  228. * @vfd_dec: video device for decoding
  229. * @vfd_enc: video device for encoding
  230. * @plat_dev: platform device
  231. * @mem_dev_l: child device of the left memory bank (0)
  232. * @mem_dev_r: child device of the right memory bank (1)
  233. * @regs_base: base address of the MFC hw registers
  234. * @irq: irq resource
  235. * @dec_ctrl_handler: control framework handler for decoding
  236. * @enc_ctrl_handler: control framework handler for encoding
  237. * @pm: power management control
  238. * @variant: MFC hardware variant information
  239. * @num_inst: couter of active MFC instances
  240. * @irqlock: lock for operations on videobuf2 queues
  241. * @condlock: lock for changing/checking if a context is ready to be
  242. * processed
  243. * @mfc_mutex: lock for video_device
  244. * @int_cond: variable used by the waitqueue
  245. * @int_type: type of last interrupt
  246. * @int_err: error number for last interrupt
  247. * @queue: waitqueue for waiting for completion of device commands
  248. * @fw_size: size of firmware
  249. * @bank1: address of the beggining of bank 1 memory
  250. * @bank2: address of the beggining of bank 2 memory
  251. * @hw_lock: used for hardware locking
  252. * @ctx: array of driver contexts
  253. * @curr_ctx: number of the currently running context
  254. * @ctx_work_bits: used to mark which contexts are waiting for hardware
  255. * @watchdog_cnt: counter for the watchdog
  256. * @watchdog_workqueue: workqueue for the watchdog
  257. * @watchdog_work: worker for the watchdog
  258. * @alloc_ctx: videobuf2 allocator contexts for two memory banks
  259. * @enter_suspend: flag set when entering suspend
  260. * @ctx_buf: common context memory (MFCv6)
  261. * @warn_start: hardware error code from which warnings start
  262. * @mfc_ops: ops structure holding HW operation function pointers
  263. * @mfc_cmds: cmd structure holding HW commands function pointers
  264. *
  265. */
  266. struct s5p_mfc_dev {
  267. struct v4l2_device v4l2_dev;
  268. struct video_device *vfd_dec;
  269. struct video_device *vfd_enc;
  270. struct platform_device *plat_dev;
  271. struct device *mem_dev_l;
  272. struct device *mem_dev_r;
  273. void __iomem *regs_base;
  274. int irq;
  275. struct v4l2_ctrl_handler dec_ctrl_handler;
  276. struct v4l2_ctrl_handler enc_ctrl_handler;
  277. struct s5p_mfc_pm pm;
  278. struct s5p_mfc_variant *variant;
  279. int num_inst;
  280. spinlock_t irqlock; /* lock when operating on videobuf2 queues */
  281. spinlock_t condlock; /* lock when changing/checking if a context is
  282. ready to be processed */
  283. struct mutex mfc_mutex; /* video_device lock */
  284. int int_cond;
  285. int int_type;
  286. unsigned int int_err;
  287. wait_queue_head_t queue;
  288. size_t fw_size;
  289. size_t bank1;
  290. size_t bank2;
  291. unsigned long hw_lock;
  292. struct s5p_mfc_ctx *ctx[MFC_NUM_CONTEXTS];
  293. int curr_ctx;
  294. unsigned long ctx_work_bits;
  295. atomic_t watchdog_cnt;
  296. struct timer_list watchdog_timer;
  297. struct workqueue_struct *watchdog_workqueue;
  298. struct work_struct watchdog_work;
  299. void *alloc_ctx[2];
  300. unsigned long enter_suspend;
  301. struct s5p_mfc_priv_buf ctx_buf;
  302. int warn_start;
  303. struct s5p_mfc_hw_ops *mfc_ops;
  304. struct s5p_mfc_hw_cmds *mfc_cmds;
  305. };
  306. /**
  307. * struct s5p_mfc_h264_enc_params - encoding parameters for h264
  308. */
  309. struct s5p_mfc_h264_enc_params {
  310. enum v4l2_mpeg_video_h264_profile profile;
  311. enum v4l2_mpeg_video_h264_loop_filter_mode loop_filter_mode;
  312. s8 loop_filter_alpha;
  313. s8 loop_filter_beta;
  314. enum v4l2_mpeg_video_h264_entropy_mode entropy_mode;
  315. u8 max_ref_pic;
  316. u8 num_ref_pic_4p;
  317. int _8x8_transform;
  318. int rc_mb_dark;
  319. int rc_mb_smooth;
  320. int rc_mb_static;
  321. int rc_mb_activity;
  322. int vui_sar;
  323. u8 vui_sar_idc;
  324. u16 vui_ext_sar_width;
  325. u16 vui_ext_sar_height;
  326. int open_gop;
  327. u16 open_gop_size;
  328. u8 rc_frame_qp;
  329. u8 rc_min_qp;
  330. u8 rc_max_qp;
  331. u8 rc_p_frame_qp;
  332. u8 rc_b_frame_qp;
  333. enum v4l2_mpeg_video_h264_level level_v4l2;
  334. int level;
  335. u16 cpb_size;
  336. int interlace;
  337. u8 hier_qp;
  338. u8 hier_qp_type;
  339. u8 hier_qp_layer;
  340. u8 hier_qp_layer_qp[7];
  341. u8 sei_frame_packing;
  342. u8 sei_fp_curr_frame_0;
  343. u8 sei_fp_arrangement_type;
  344. u8 fmo;
  345. u8 fmo_map_type;
  346. u8 fmo_slice_grp;
  347. u8 fmo_chg_dir;
  348. u32 fmo_chg_rate;
  349. u32 fmo_run_len[4];
  350. u8 aso;
  351. u32 aso_slice_order[8];
  352. };
  353. /**
  354. * struct s5p_mfc_mpeg4_enc_params - encoding parameters for h263 and mpeg4
  355. */
  356. struct s5p_mfc_mpeg4_enc_params {
  357. /* MPEG4 Only */
  358. enum v4l2_mpeg_video_mpeg4_profile profile;
  359. int quarter_pixel;
  360. /* Common for MPEG4, H263 */
  361. u16 vop_time_res;
  362. u16 vop_frm_delta;
  363. u8 rc_frame_qp;
  364. u8 rc_min_qp;
  365. u8 rc_max_qp;
  366. u8 rc_p_frame_qp;
  367. u8 rc_b_frame_qp;
  368. enum v4l2_mpeg_video_mpeg4_level level_v4l2;
  369. int level;
  370. };
  371. /**
  372. * struct s5p_mfc_enc_params - general encoding parameters
  373. */
  374. struct s5p_mfc_enc_params {
  375. u16 width;
  376. u16 height;
  377. u16 gop_size;
  378. enum v4l2_mpeg_video_multi_slice_mode slice_mode;
  379. u16 slice_mb;
  380. u32 slice_bit;
  381. u16 intra_refresh_mb;
  382. int pad;
  383. u8 pad_luma;
  384. u8 pad_cb;
  385. u8 pad_cr;
  386. int rc_frame;
  387. int rc_mb;
  388. u32 rc_bitrate;
  389. u16 rc_reaction_coeff;
  390. u16 vbv_size;
  391. u32 vbv_delay;
  392. enum v4l2_mpeg_video_header_mode seq_hdr_mode;
  393. enum v4l2_mpeg_mfc51_video_frame_skip_mode frame_skip_mode;
  394. int fixed_target_bit;
  395. u8 num_b_frame;
  396. u32 rc_framerate_num;
  397. u32 rc_framerate_denom;
  398. union {
  399. struct s5p_mfc_h264_enc_params h264;
  400. struct s5p_mfc_mpeg4_enc_params mpeg4;
  401. } codec;
  402. };
  403. /**
  404. * struct s5p_mfc_codec_ops - codec ops, used by encoding
  405. */
  406. struct s5p_mfc_codec_ops {
  407. /* initialization routines */
  408. int (*pre_seq_start) (struct s5p_mfc_ctx *ctx);
  409. int (*post_seq_start) (struct s5p_mfc_ctx *ctx);
  410. /* execution routines */
  411. int (*pre_frame_start) (struct s5p_mfc_ctx *ctx);
  412. int (*post_frame_start) (struct s5p_mfc_ctx *ctx);
  413. };
  414. #define call_cop(c, op, args...) \
  415. (((c)->c_ops->op) ? \
  416. ((c)->c_ops->op(args)) : 0)
  417. /**
  418. * struct s5p_mfc_ctx - This struct contains the instance context
  419. *
  420. * @dev: pointer to the s5p_mfc_dev of the device
  421. * @fh: struct v4l2_fh
  422. * @num: number of the context that this structure describes
  423. * @int_cond: variable used by the waitqueue
  424. * @int_type: type of the last interrupt
  425. * @int_err: error number received from MFC hw in the interrupt
  426. * @queue: waitqueue that can be used to wait for this context to
  427. * finish
  428. * @src_fmt: source pixelformat information
  429. * @dst_fmt: destination pixelformat information
  430. * @vq_src: vb2 queue for source buffers
  431. * @vq_dst: vb2 queue for destination buffers
  432. * @src_queue: driver internal queue for source buffers
  433. * @dst_queue: driver internal queue for destination buffers
  434. * @src_queue_cnt: number of buffers queued on the source internal queue
  435. * @dst_queue_cnt: number of buffers queued on the dest internal queue
  436. * @type: type of the instance - decoder or encoder
  437. * @state: state of the context
  438. * @inst_no: number of hw instance associated with the context
  439. * @img_width: width of the image that is decoded or encoded
  440. * @img_height: height of the image that is decoded or encoded
  441. * @buf_width: width of the buffer for processed image
  442. * @buf_height: height of the buffer for processed image
  443. * @luma_size: size of a luma plane
  444. * @chroma_size: size of a chroma plane
  445. * @mv_size: size of a motion vectors buffer
  446. * @consumed_stream: number of bytes that have been used so far from the
  447. * decoding buffer
  448. * @dpb_flush_flag: flag used to indicate that a DPB buffers are being
  449. * flushed
  450. * @head_processed: flag mentioning whether the header data is processed
  451. * completely or not
  452. * @bank1_buf: handle to memory allocated for temporary buffers from
  453. * memory bank 1
  454. * @bank1_phys: address of the temporary buffers from memory bank 1
  455. * @bank1_size: size of the memory allocated for temporary buffers from
  456. * memory bank 1
  457. * @bank2_buf: handle to memory allocated for temporary buffers from
  458. * memory bank 2
  459. * @bank2_phys: address of the temporary buffers from memory bank 2
  460. * @bank2_size: size of the memory allocated for temporary buffers from
  461. * memory bank 2
  462. * @capture_state: state of the capture buffers queue
  463. * @output_state: state of the output buffers queue
  464. * @src_bufs: information on allocated source buffers
  465. * @dst_bufs: information on allocated destination buffers
  466. * @sequence: counter for the sequence number for v4l2
  467. * @dec_dst_flag: flags for buffers queued in the hardware
  468. * @dec_src_buf_size: size of the buffer for source buffers in decoding
  469. * @codec_mode: number of codec mode used by MFC hw
  470. * @slice_interface: slice interface flag
  471. * @loop_filter_mpeg4: loop filter for MPEG4 flag
  472. * @display_delay: value of the display delay for H264
  473. * @display_delay_enable: display delay for H264 enable flag
  474. * @after_packed_pb: flag used to track buffer when stream is in
  475. * Packed PB format
  476. * @sei_fp_parse: enable/disable parsing of frame packing SEI information
  477. * @dpb_count: count of the DPB buffers required by MFC hw
  478. * @total_dpb_count: count of DPB buffers with additional buffers
  479. * requested by the application
  480. * @ctx: context buffer information
  481. * @dsc: descriptor buffer information
  482. * @shm: shared memory buffer information
  483. * @mv_count: number of MV buffers allocated for decoding
  484. * @enc_params: encoding parameters for MFC
  485. * @enc_dst_buf_size: size of the buffers for encoder output
  486. * @luma_dpb_size: dpb buffer size for luma
  487. * @chroma_dpb_size: dpb buffer size for chroma
  488. * @me_buffer_size: size of the motion estimation buffer
  489. * @tmv_buffer_size: size of temporal predictor motion vector buffer
  490. * @frame_type: used to force the type of the next encoded frame
  491. * @ref_queue: list of the reference buffers for encoding
  492. * @ref_queue_cnt: number of the buffers in the reference list
  493. * @c_ops: ops for encoding
  494. * @ctrls: array of controls, used when adding controls to the
  495. * v4l2 control framework
  496. * @ctrl_handler: handler for v4l2 framework
  497. */
  498. struct s5p_mfc_ctx {
  499. struct s5p_mfc_dev *dev;
  500. struct v4l2_fh fh;
  501. int num;
  502. int int_cond;
  503. int int_type;
  504. unsigned int int_err;
  505. wait_queue_head_t queue;
  506. struct s5p_mfc_fmt *src_fmt;
  507. struct s5p_mfc_fmt *dst_fmt;
  508. struct vb2_queue vq_src;
  509. struct vb2_queue vq_dst;
  510. struct list_head src_queue;
  511. struct list_head dst_queue;
  512. unsigned int src_queue_cnt;
  513. unsigned int dst_queue_cnt;
  514. enum s5p_mfc_inst_type type;
  515. enum s5p_mfc_inst_state state;
  516. int inst_no;
  517. /* Image parameters */
  518. int img_width;
  519. int img_height;
  520. int buf_width;
  521. int buf_height;
  522. int luma_size;
  523. int chroma_size;
  524. int mv_size;
  525. unsigned long consumed_stream;
  526. unsigned int dpb_flush_flag;
  527. unsigned int head_processed;
  528. /* Buffers */
  529. void *bank1_buf;
  530. size_t bank1_phys;
  531. size_t bank1_size;
  532. void *bank2_buf;
  533. size_t bank2_phys;
  534. size_t bank2_size;
  535. enum s5p_mfc_queue_state capture_state;
  536. enum s5p_mfc_queue_state output_state;
  537. struct s5p_mfc_buf src_bufs[MFC_MAX_BUFFERS];
  538. int src_bufs_cnt;
  539. struct s5p_mfc_buf dst_bufs[MFC_MAX_BUFFERS];
  540. int dst_bufs_cnt;
  541. unsigned int sequence;
  542. unsigned long dec_dst_flag;
  543. size_t dec_src_buf_size;
  544. /* Control values */
  545. int codec_mode;
  546. int slice_interface;
  547. int loop_filter_mpeg4;
  548. int display_delay;
  549. int display_delay_enable;
  550. int after_packed_pb;
  551. int sei_fp_parse;
  552. int dpb_count;
  553. int total_dpb_count;
  554. int mv_count;
  555. /* Buffers */
  556. struct s5p_mfc_priv_buf ctx;
  557. struct s5p_mfc_priv_buf dsc;
  558. struct s5p_mfc_priv_buf shm;
  559. struct s5p_mfc_enc_params enc_params;
  560. size_t enc_dst_buf_size;
  561. size_t luma_dpb_size;
  562. size_t chroma_dpb_size;
  563. size_t me_buffer_size;
  564. size_t tmv_buffer_size;
  565. enum v4l2_mpeg_mfc51_video_force_frame_type force_frame_type;
  566. struct list_head ref_queue;
  567. unsigned int ref_queue_cnt;
  568. enum v4l2_mpeg_video_multi_slice_mode slice_mode;
  569. union {
  570. unsigned int mb;
  571. unsigned int bits;
  572. } slice_size;
  573. struct s5p_mfc_codec_ops *c_ops;
  574. struct v4l2_ctrl *ctrls[MFC_MAX_CTRLS];
  575. struct v4l2_ctrl_handler ctrl_handler;
  576. unsigned int frame_tag;
  577. size_t scratch_buf_size;
  578. };
  579. /*
  580. * struct s5p_mfc_fmt - structure used to store information about pixelformats
  581. * used by the MFC
  582. */
  583. struct s5p_mfc_fmt {
  584. char *name;
  585. u32 fourcc;
  586. u32 codec_mode;
  587. enum s5p_mfc_fmt_type type;
  588. u32 num_planes;
  589. };
  590. /**
  591. * struct mfc_control - structure used to store information about MFC controls
  592. * it is used to initialize the control framework.
  593. */
  594. struct mfc_control {
  595. __u32 id;
  596. enum v4l2_ctrl_type type;
  597. __u8 name[32]; /* Whatever */
  598. __s32 minimum; /* Note signedness */
  599. __s32 maximum;
  600. __s32 step;
  601. __u32 menu_skip_mask;
  602. __s32 default_value;
  603. __u32 flags;
  604. __u32 reserved[2];
  605. __u8 is_volatile;
  606. };
  607. /* Macro for making hardware specific calls */
  608. #define s5p_mfc_hw_call(f, op, args...) \
  609. ((f && f->op) ? f->op(args) : -ENODEV)
  610. #define fh_to_ctx(__fh) container_of(__fh, struct s5p_mfc_ctx, fh)
  611. #define ctrl_to_ctx(__ctrl) \
  612. container_of((__ctrl)->handler, struct s5p_mfc_ctx, ctrl_handler)
  613. void clear_work_bit(struct s5p_mfc_ctx *ctx);
  614. void set_work_bit(struct s5p_mfc_ctx *ctx);
  615. void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx);
  616. void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx);
  617. #define HAS_PORTNUM(dev) (dev ? (dev->variant ? \
  618. (dev->variant->port_num ? 1 : 0) : 0) : 0)
  619. #define IS_TWOPORT(dev) (dev->variant->port_num == 2 ? 1 : 0)
  620. #define IS_MFCV6(dev) (dev->variant->version >= 0x60 ? 1 : 0)
  621. #endif /* S5P_MFC_COMMON_H_ */