coda.c 55 KB

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  1. /*
  2. * Coda multi-standard codec IP
  3. *
  4. * Copyright (C) 2012 Vista Silicon S.L.
  5. * Javier Martin, <javier.martin@vista-silicon.com>
  6. * Xavier Duret
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/delay.h>
  15. #include <linux/firmware.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/io.h>
  18. #include <linux/irq.h>
  19. #include <linux/module.h>
  20. #include <linux/of_device.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/slab.h>
  23. #include <linux/videodev2.h>
  24. #include <linux/of.h>
  25. #include <mach/iram.h>
  26. #include <media/v4l2-ctrls.h>
  27. #include <media/v4l2-device.h>
  28. #include <media/v4l2-ioctl.h>
  29. #include <media/v4l2-mem2mem.h>
  30. #include <media/videobuf2-core.h>
  31. #include <media/videobuf2-dma-contig.h>
  32. #include "coda.h"
  33. #define CODA_NAME "coda"
  34. #define CODA_MAX_INSTANCES 4
  35. #define CODA_FMO_BUF_SIZE 32
  36. #define CODADX6_WORK_BUF_SIZE (288 * 1024 + CODA_FMO_BUF_SIZE * 8 * 1024)
  37. #define CODA7_WORK_BUF_SIZE (512 * 1024 + CODA_FMO_BUF_SIZE * 8 * 1024)
  38. #define CODA_PARA_BUF_SIZE (10 * 1024)
  39. #define CODA_ISRAM_SIZE (2048 * 2)
  40. #define CODA7_IRAM_SIZE 0x14000 /* 81920 bytes */
  41. #define CODA_MAX_FRAMEBUFFERS 2
  42. #define MAX_W 720
  43. #define MAX_H 576
  44. #define CODA_MAX_FRAME_SIZE 0x90000
  45. #define FMO_SLICE_SAVE_BUF_SIZE (32)
  46. #define CODA_DEFAULT_GAMMA 4096
  47. #define MIN_W 176
  48. #define MIN_H 144
  49. #define MAX_W 720
  50. #define MAX_H 576
  51. #define S_ALIGN 1 /* multiple of 2 */
  52. #define W_ALIGN 1 /* multiple of 2 */
  53. #define H_ALIGN 1 /* multiple of 2 */
  54. #define fh_to_ctx(__fh) container_of(__fh, struct coda_ctx, fh)
  55. static int coda_debug;
  56. module_param(coda_debug, int, 0);
  57. MODULE_PARM_DESC(coda_debug, "Debug level (0-1)");
  58. enum {
  59. V4L2_M2M_SRC = 0,
  60. V4L2_M2M_DST = 1,
  61. };
  62. enum coda_fmt_type {
  63. CODA_FMT_ENC,
  64. CODA_FMT_RAW,
  65. };
  66. enum coda_inst_type {
  67. CODA_INST_ENCODER,
  68. CODA_INST_DECODER,
  69. };
  70. enum coda_product {
  71. CODA_DX6 = 0xf001,
  72. CODA_7541 = 0xf012,
  73. };
  74. struct coda_fmt {
  75. char *name;
  76. u32 fourcc;
  77. enum coda_fmt_type type;
  78. };
  79. struct coda_devtype {
  80. char *firmware;
  81. enum coda_product product;
  82. struct coda_fmt *formats;
  83. unsigned int num_formats;
  84. size_t workbuf_size;
  85. };
  86. /* Per-queue, driver-specific private data */
  87. struct coda_q_data {
  88. unsigned int width;
  89. unsigned int height;
  90. unsigned int sizeimage;
  91. struct coda_fmt *fmt;
  92. };
  93. struct coda_aux_buf {
  94. void *vaddr;
  95. dma_addr_t paddr;
  96. u32 size;
  97. };
  98. struct coda_dev {
  99. struct v4l2_device v4l2_dev;
  100. struct video_device vfd;
  101. struct platform_device *plat_dev;
  102. const struct coda_devtype *devtype;
  103. void __iomem *regs_base;
  104. struct clk *clk_per;
  105. struct clk *clk_ahb;
  106. struct coda_aux_buf codebuf;
  107. struct coda_aux_buf workbuf;
  108. long unsigned int iram_paddr;
  109. spinlock_t irqlock;
  110. struct mutex dev_mutex;
  111. struct v4l2_m2m_dev *m2m_dev;
  112. struct vb2_alloc_ctx *alloc_ctx;
  113. struct list_head instances;
  114. unsigned long instance_mask;
  115. struct delayed_work timeout;
  116. struct completion done;
  117. };
  118. struct coda_params {
  119. u8 rot_mode;
  120. u8 h264_intra_qp;
  121. u8 h264_inter_qp;
  122. u8 mpeg4_intra_qp;
  123. u8 mpeg4_inter_qp;
  124. u8 gop_size;
  125. int codec_mode;
  126. enum v4l2_mpeg_video_multi_slice_mode slice_mode;
  127. u32 framerate;
  128. u16 bitrate;
  129. u32 slice_max_bits;
  130. u32 slice_max_mb;
  131. };
  132. struct coda_ctx {
  133. struct coda_dev *dev;
  134. struct list_head list;
  135. int aborting;
  136. int rawstreamon;
  137. int compstreamon;
  138. u32 isequence;
  139. struct coda_q_data q_data[2];
  140. enum coda_inst_type inst_type;
  141. enum v4l2_colorspace colorspace;
  142. struct coda_params params;
  143. struct v4l2_m2m_ctx *m2m_ctx;
  144. struct v4l2_ctrl_handler ctrls;
  145. struct v4l2_fh fh;
  146. int gopcounter;
  147. char vpu_header[3][64];
  148. int vpu_header_size[3];
  149. struct coda_aux_buf parabuf;
  150. struct coda_aux_buf internal_frames[CODA_MAX_FRAMEBUFFERS];
  151. int num_internal_frames;
  152. int idx;
  153. };
  154. static inline void coda_write(struct coda_dev *dev, u32 data, u32 reg)
  155. {
  156. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  157. "%s: data=0x%x, reg=0x%x\n", __func__, data, reg);
  158. writel(data, dev->regs_base + reg);
  159. }
  160. static inline unsigned int coda_read(struct coda_dev *dev, u32 reg)
  161. {
  162. u32 data;
  163. data = readl(dev->regs_base + reg);
  164. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  165. "%s: data=0x%x, reg=0x%x\n", __func__, data, reg);
  166. return data;
  167. }
  168. static inline unsigned long coda_isbusy(struct coda_dev *dev)
  169. {
  170. return coda_read(dev, CODA_REG_BIT_BUSY);
  171. }
  172. static inline int coda_is_initialized(struct coda_dev *dev)
  173. {
  174. return (coda_read(dev, CODA_REG_BIT_CUR_PC) != 0);
  175. }
  176. static int coda_wait_timeout(struct coda_dev *dev)
  177. {
  178. unsigned long timeout = jiffies + msecs_to_jiffies(1000);
  179. while (coda_isbusy(dev)) {
  180. if (time_after(jiffies, timeout))
  181. return -ETIMEDOUT;
  182. }
  183. return 0;
  184. }
  185. static void coda_command_async(struct coda_ctx *ctx, int cmd)
  186. {
  187. struct coda_dev *dev = ctx->dev;
  188. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  189. coda_write(dev, ctx->idx, CODA_REG_BIT_RUN_INDEX);
  190. coda_write(dev, ctx->params.codec_mode, CODA_REG_BIT_RUN_COD_STD);
  191. coda_write(dev, cmd, CODA_REG_BIT_RUN_COMMAND);
  192. }
  193. static int coda_command_sync(struct coda_ctx *ctx, int cmd)
  194. {
  195. struct coda_dev *dev = ctx->dev;
  196. coda_command_async(ctx, cmd);
  197. return coda_wait_timeout(dev);
  198. }
  199. static struct coda_q_data *get_q_data(struct coda_ctx *ctx,
  200. enum v4l2_buf_type type)
  201. {
  202. switch (type) {
  203. case V4L2_BUF_TYPE_VIDEO_OUTPUT:
  204. return &(ctx->q_data[V4L2_M2M_SRC]);
  205. case V4L2_BUF_TYPE_VIDEO_CAPTURE:
  206. return &(ctx->q_data[V4L2_M2M_DST]);
  207. default:
  208. BUG();
  209. }
  210. return NULL;
  211. }
  212. /*
  213. * Add one array of supported formats for each version of Coda:
  214. * i.MX27 -> codadx6
  215. * i.MX51 -> coda7
  216. * i.MX6 -> coda960
  217. */
  218. static struct coda_fmt codadx6_formats[] = {
  219. {
  220. .name = "YUV 4:2:0 Planar",
  221. .fourcc = V4L2_PIX_FMT_YUV420,
  222. .type = CODA_FMT_RAW,
  223. },
  224. {
  225. .name = "H264 Encoded Stream",
  226. .fourcc = V4L2_PIX_FMT_H264,
  227. .type = CODA_FMT_ENC,
  228. },
  229. {
  230. .name = "MPEG4 Encoded Stream",
  231. .fourcc = V4L2_PIX_FMT_MPEG4,
  232. .type = CODA_FMT_ENC,
  233. },
  234. };
  235. static struct coda_fmt coda7_formats[] = {
  236. {
  237. .name = "YUV 4:2:0 Planar",
  238. .fourcc = V4L2_PIX_FMT_YUV420,
  239. .type = CODA_FMT_RAW,
  240. },
  241. {
  242. .name = "H264 Encoded Stream",
  243. .fourcc = V4L2_PIX_FMT_H264,
  244. .type = CODA_FMT_ENC,
  245. },
  246. {
  247. .name = "MPEG4 Encoded Stream",
  248. .fourcc = V4L2_PIX_FMT_MPEG4,
  249. .type = CODA_FMT_ENC,
  250. },
  251. };
  252. static struct coda_fmt *find_format(struct coda_dev *dev, struct v4l2_format *f)
  253. {
  254. struct coda_fmt *formats = dev->devtype->formats;
  255. int num_formats = dev->devtype->num_formats;
  256. unsigned int k;
  257. for (k = 0; k < num_formats; k++) {
  258. if (formats[k].fourcc == f->fmt.pix.pixelformat)
  259. break;
  260. }
  261. if (k == num_formats)
  262. return NULL;
  263. return &formats[k];
  264. }
  265. /*
  266. * V4L2 ioctl() operations.
  267. */
  268. static int vidioc_querycap(struct file *file, void *priv,
  269. struct v4l2_capability *cap)
  270. {
  271. strlcpy(cap->driver, CODA_NAME, sizeof(cap->driver));
  272. strlcpy(cap->card, CODA_NAME, sizeof(cap->card));
  273. strlcpy(cap->bus_info, CODA_NAME, sizeof(cap->bus_info));
  274. /*
  275. * This is only a mem-to-mem video device. The capture and output
  276. * device capability flags are left only for backward compatibility
  277. * and are scheduled for removal.
  278. */
  279. cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT |
  280. V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING;
  281. cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
  282. return 0;
  283. }
  284. static int enum_fmt(void *priv, struct v4l2_fmtdesc *f,
  285. enum coda_fmt_type type)
  286. {
  287. struct coda_ctx *ctx = fh_to_ctx(priv);
  288. struct coda_dev *dev = ctx->dev;
  289. struct coda_fmt *formats = dev->devtype->formats;
  290. struct coda_fmt *fmt;
  291. int num_formats = dev->devtype->num_formats;
  292. int i, num = 0;
  293. for (i = 0; i < num_formats; i++) {
  294. if (formats[i].type == type) {
  295. if (num == f->index)
  296. break;
  297. ++num;
  298. }
  299. }
  300. if (i < num_formats) {
  301. fmt = &formats[i];
  302. strlcpy(f->description, fmt->name, sizeof(f->description));
  303. f->pixelformat = fmt->fourcc;
  304. return 0;
  305. }
  306. /* Format not found */
  307. return -EINVAL;
  308. }
  309. static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
  310. struct v4l2_fmtdesc *f)
  311. {
  312. return enum_fmt(priv, f, CODA_FMT_ENC);
  313. }
  314. static int vidioc_enum_fmt_vid_out(struct file *file, void *priv,
  315. struct v4l2_fmtdesc *f)
  316. {
  317. return enum_fmt(priv, f, CODA_FMT_RAW);
  318. }
  319. static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
  320. {
  321. struct vb2_queue *vq;
  322. struct coda_q_data *q_data;
  323. struct coda_ctx *ctx = fh_to_ctx(priv);
  324. vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
  325. if (!vq)
  326. return -EINVAL;
  327. q_data = get_q_data(ctx, f->type);
  328. f->fmt.pix.field = V4L2_FIELD_NONE;
  329. f->fmt.pix.pixelformat = q_data->fmt->fourcc;
  330. f->fmt.pix.width = q_data->width;
  331. f->fmt.pix.height = q_data->height;
  332. if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420)
  333. f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 2);
  334. else /* encoded formats h.264/mpeg4 */
  335. f->fmt.pix.bytesperline = 0;
  336. f->fmt.pix.sizeimage = q_data->sizeimage;
  337. f->fmt.pix.colorspace = ctx->colorspace;
  338. return 0;
  339. }
  340. static int vidioc_try_fmt(struct coda_dev *dev, struct v4l2_format *f)
  341. {
  342. enum v4l2_field field;
  343. field = f->fmt.pix.field;
  344. if (field == V4L2_FIELD_ANY)
  345. field = V4L2_FIELD_NONE;
  346. else if (V4L2_FIELD_NONE != field)
  347. return -EINVAL;
  348. /* V4L2 specification suggests the driver corrects the format struct
  349. * if any of the dimensions is unsupported */
  350. f->fmt.pix.field = field;
  351. if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) {
  352. v4l_bound_align_image(&f->fmt.pix.width, MIN_W, MAX_W,
  353. W_ALIGN, &f->fmt.pix.height,
  354. MIN_H, MAX_H, H_ALIGN, S_ALIGN);
  355. f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 2);
  356. f->fmt.pix.sizeimage = f->fmt.pix.width *
  357. f->fmt.pix.height * 3 / 2;
  358. } else { /*encoded formats h.264/mpeg4 */
  359. f->fmt.pix.bytesperline = 0;
  360. f->fmt.pix.sizeimage = CODA_MAX_FRAME_SIZE;
  361. }
  362. return 0;
  363. }
  364. static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
  365. struct v4l2_format *f)
  366. {
  367. int ret;
  368. struct coda_fmt *fmt;
  369. struct coda_ctx *ctx = fh_to_ctx(priv);
  370. fmt = find_format(ctx->dev, f);
  371. /*
  372. * Since decoding support is not implemented yet do not allow
  373. * CODA_FMT_RAW formats in the capture interface.
  374. */
  375. if (!fmt || !(fmt->type == CODA_FMT_ENC))
  376. f->fmt.pix.pixelformat = V4L2_PIX_FMT_H264;
  377. f->fmt.pix.colorspace = ctx->colorspace;
  378. ret = vidioc_try_fmt(ctx->dev, f);
  379. if (ret < 0)
  380. return ret;
  381. return 0;
  382. }
  383. static int vidioc_try_fmt_vid_out(struct file *file, void *priv,
  384. struct v4l2_format *f)
  385. {
  386. struct coda_ctx *ctx = fh_to_ctx(priv);
  387. struct coda_fmt *fmt;
  388. int ret;
  389. fmt = find_format(ctx->dev, f);
  390. /*
  391. * Since decoding support is not implemented yet do not allow
  392. * CODA_FMT formats in the capture interface.
  393. */
  394. if (!fmt || !(fmt->type == CODA_FMT_RAW))
  395. f->fmt.pix.pixelformat = V4L2_PIX_FMT_YUV420;
  396. if (!f->fmt.pix.colorspace)
  397. f->fmt.pix.colorspace = V4L2_COLORSPACE_REC709;
  398. ret = vidioc_try_fmt(ctx->dev, f);
  399. if (ret < 0)
  400. return ret;
  401. return 0;
  402. }
  403. static int vidioc_s_fmt(struct coda_ctx *ctx, struct v4l2_format *f)
  404. {
  405. struct coda_q_data *q_data;
  406. struct vb2_queue *vq;
  407. int ret;
  408. vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
  409. if (!vq)
  410. return -EINVAL;
  411. q_data = get_q_data(ctx, f->type);
  412. if (!q_data)
  413. return -EINVAL;
  414. if (vb2_is_busy(vq)) {
  415. v4l2_err(&ctx->dev->v4l2_dev, "%s queue busy\n", __func__);
  416. return -EBUSY;
  417. }
  418. ret = vidioc_try_fmt(ctx->dev, f);
  419. if (ret)
  420. return ret;
  421. q_data->fmt = find_format(ctx->dev, f);
  422. q_data->width = f->fmt.pix.width;
  423. q_data->height = f->fmt.pix.height;
  424. q_data->sizeimage = f->fmt.pix.sizeimage;
  425. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  426. "Setting format for type %d, wxh: %dx%d, fmt: %d\n",
  427. f->type, q_data->width, q_data->height, q_data->fmt->fourcc);
  428. return 0;
  429. }
  430. static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
  431. struct v4l2_format *f)
  432. {
  433. int ret;
  434. ret = vidioc_try_fmt_vid_cap(file, priv, f);
  435. if (ret)
  436. return ret;
  437. return vidioc_s_fmt(fh_to_ctx(priv), f);
  438. }
  439. static int vidioc_s_fmt_vid_out(struct file *file, void *priv,
  440. struct v4l2_format *f)
  441. {
  442. struct coda_ctx *ctx = fh_to_ctx(priv);
  443. int ret;
  444. ret = vidioc_try_fmt_vid_out(file, priv, f);
  445. if (ret)
  446. return ret;
  447. ret = vidioc_s_fmt(ctx, f);
  448. if (ret)
  449. ctx->colorspace = f->fmt.pix.colorspace;
  450. return ret;
  451. }
  452. static int vidioc_reqbufs(struct file *file, void *priv,
  453. struct v4l2_requestbuffers *reqbufs)
  454. {
  455. struct coda_ctx *ctx = fh_to_ctx(priv);
  456. return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
  457. }
  458. static int vidioc_querybuf(struct file *file, void *priv,
  459. struct v4l2_buffer *buf)
  460. {
  461. struct coda_ctx *ctx = fh_to_ctx(priv);
  462. return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
  463. }
  464. static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
  465. {
  466. struct coda_ctx *ctx = fh_to_ctx(priv);
  467. return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
  468. }
  469. static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
  470. {
  471. struct coda_ctx *ctx = fh_to_ctx(priv);
  472. return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
  473. }
  474. static int vidioc_streamon(struct file *file, void *priv,
  475. enum v4l2_buf_type type)
  476. {
  477. struct coda_ctx *ctx = fh_to_ctx(priv);
  478. return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
  479. }
  480. static int vidioc_streamoff(struct file *file, void *priv,
  481. enum v4l2_buf_type type)
  482. {
  483. struct coda_ctx *ctx = fh_to_ctx(priv);
  484. return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
  485. }
  486. static const struct v4l2_ioctl_ops coda_ioctl_ops = {
  487. .vidioc_querycap = vidioc_querycap,
  488. .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
  489. .vidioc_g_fmt_vid_cap = vidioc_g_fmt,
  490. .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
  491. .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
  492. .vidioc_enum_fmt_vid_out = vidioc_enum_fmt_vid_out,
  493. .vidioc_g_fmt_vid_out = vidioc_g_fmt,
  494. .vidioc_try_fmt_vid_out = vidioc_try_fmt_vid_out,
  495. .vidioc_s_fmt_vid_out = vidioc_s_fmt_vid_out,
  496. .vidioc_reqbufs = vidioc_reqbufs,
  497. .vidioc_querybuf = vidioc_querybuf,
  498. .vidioc_qbuf = vidioc_qbuf,
  499. .vidioc_dqbuf = vidioc_dqbuf,
  500. .vidioc_streamon = vidioc_streamon,
  501. .vidioc_streamoff = vidioc_streamoff,
  502. };
  503. /*
  504. * Mem-to-mem operations.
  505. */
  506. static void coda_device_run(void *m2m_priv)
  507. {
  508. struct coda_ctx *ctx = m2m_priv;
  509. struct coda_q_data *q_data_src, *q_data_dst;
  510. struct vb2_buffer *src_buf, *dst_buf;
  511. struct coda_dev *dev = ctx->dev;
  512. int force_ipicture;
  513. int quant_param = 0;
  514. u32 picture_y, picture_cb, picture_cr;
  515. u32 pic_stream_buffer_addr, pic_stream_buffer_size;
  516. u32 dst_fourcc;
  517. src_buf = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
  518. dst_buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
  519. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  520. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  521. dst_fourcc = q_data_dst->fmt->fourcc;
  522. src_buf->v4l2_buf.sequence = ctx->isequence;
  523. dst_buf->v4l2_buf.sequence = ctx->isequence;
  524. ctx->isequence++;
  525. /*
  526. * Workaround coda firmware BUG that only marks the first
  527. * frame as IDR. This is a problem for some decoders that can't
  528. * recover when a frame is lost.
  529. */
  530. if (src_buf->v4l2_buf.sequence % ctx->params.gop_size) {
  531. src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
  532. src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
  533. } else {
  534. src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
  535. src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
  536. }
  537. /*
  538. * Copy headers at the beginning of the first frame for H.264 only.
  539. * In MPEG4 they are already copied by the coda.
  540. */
  541. if (src_buf->v4l2_buf.sequence == 0) {
  542. pic_stream_buffer_addr =
  543. vb2_dma_contig_plane_dma_addr(dst_buf, 0) +
  544. ctx->vpu_header_size[0] +
  545. ctx->vpu_header_size[1] +
  546. ctx->vpu_header_size[2];
  547. pic_stream_buffer_size = CODA_MAX_FRAME_SIZE -
  548. ctx->vpu_header_size[0] -
  549. ctx->vpu_header_size[1] -
  550. ctx->vpu_header_size[2];
  551. memcpy(vb2_plane_vaddr(dst_buf, 0),
  552. &ctx->vpu_header[0][0], ctx->vpu_header_size[0]);
  553. memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0],
  554. &ctx->vpu_header[1][0], ctx->vpu_header_size[1]);
  555. memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0] +
  556. ctx->vpu_header_size[1], &ctx->vpu_header[2][0],
  557. ctx->vpu_header_size[2]);
  558. } else {
  559. pic_stream_buffer_addr =
  560. vb2_dma_contig_plane_dma_addr(dst_buf, 0);
  561. pic_stream_buffer_size = CODA_MAX_FRAME_SIZE;
  562. }
  563. if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
  564. force_ipicture = 1;
  565. switch (dst_fourcc) {
  566. case V4L2_PIX_FMT_H264:
  567. quant_param = ctx->params.h264_intra_qp;
  568. break;
  569. case V4L2_PIX_FMT_MPEG4:
  570. quant_param = ctx->params.mpeg4_intra_qp;
  571. break;
  572. default:
  573. v4l2_warn(&ctx->dev->v4l2_dev,
  574. "cannot set intra qp, fmt not supported\n");
  575. break;
  576. }
  577. } else {
  578. force_ipicture = 0;
  579. switch (dst_fourcc) {
  580. case V4L2_PIX_FMT_H264:
  581. quant_param = ctx->params.h264_inter_qp;
  582. break;
  583. case V4L2_PIX_FMT_MPEG4:
  584. quant_param = ctx->params.mpeg4_inter_qp;
  585. break;
  586. default:
  587. v4l2_warn(&ctx->dev->v4l2_dev,
  588. "cannot set inter qp, fmt not supported\n");
  589. break;
  590. }
  591. }
  592. /* submit */
  593. coda_write(dev, CODA_ROT_MIR_ENABLE | ctx->params.rot_mode, CODA_CMD_ENC_PIC_ROT_MODE);
  594. coda_write(dev, quant_param, CODA_CMD_ENC_PIC_QS);
  595. picture_y = vb2_dma_contig_plane_dma_addr(src_buf, 0);
  596. picture_cb = picture_y + q_data_src->width * q_data_src->height;
  597. picture_cr = picture_cb + q_data_src->width / 2 *
  598. q_data_src->height / 2;
  599. coda_write(dev, picture_y, CODA_CMD_ENC_PIC_SRC_ADDR_Y);
  600. coda_write(dev, picture_cb, CODA_CMD_ENC_PIC_SRC_ADDR_CB);
  601. coda_write(dev, picture_cr, CODA_CMD_ENC_PIC_SRC_ADDR_CR);
  602. coda_write(dev, force_ipicture << 1 & 0x2,
  603. CODA_CMD_ENC_PIC_OPTION);
  604. coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START);
  605. coda_write(dev, pic_stream_buffer_size / 1024,
  606. CODA_CMD_ENC_PIC_BB_SIZE);
  607. if (dev->devtype->product == CODA_7541) {
  608. coda_write(dev, CODA7_USE_BIT_ENABLE | CODA7_USE_HOST_BIT_ENABLE |
  609. CODA7_USE_ME_ENABLE | CODA7_USE_HOST_ME_ENABLE,
  610. CODA7_REG_BIT_AXI_SRAM_USE);
  611. }
  612. /* 1 second timeout in case CODA locks up */
  613. schedule_delayed_work(&dev->timeout, HZ);
  614. INIT_COMPLETION(dev->done);
  615. coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
  616. }
  617. static int coda_job_ready(void *m2m_priv)
  618. {
  619. struct coda_ctx *ctx = m2m_priv;
  620. /*
  621. * For both 'P' and 'key' frame cases 1 picture
  622. * and 1 frame are needed.
  623. */
  624. if (!v4l2_m2m_num_src_bufs_ready(ctx->m2m_ctx) ||
  625. !v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx)) {
  626. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  627. "not ready: not enough video buffers.\n");
  628. return 0;
  629. }
  630. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  631. "job ready\n");
  632. return 1;
  633. }
  634. static void coda_job_abort(void *priv)
  635. {
  636. struct coda_ctx *ctx = priv;
  637. struct coda_dev *dev = ctx->dev;
  638. ctx->aborting = 1;
  639. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  640. "Aborting task\n");
  641. v4l2_m2m_job_finish(dev->m2m_dev, ctx->m2m_ctx);
  642. }
  643. static void coda_lock(void *m2m_priv)
  644. {
  645. struct coda_ctx *ctx = m2m_priv;
  646. struct coda_dev *pcdev = ctx->dev;
  647. mutex_lock(&pcdev->dev_mutex);
  648. }
  649. static void coda_unlock(void *m2m_priv)
  650. {
  651. struct coda_ctx *ctx = m2m_priv;
  652. struct coda_dev *pcdev = ctx->dev;
  653. mutex_unlock(&pcdev->dev_mutex);
  654. }
  655. static struct v4l2_m2m_ops coda_m2m_ops = {
  656. .device_run = coda_device_run,
  657. .job_ready = coda_job_ready,
  658. .job_abort = coda_job_abort,
  659. .lock = coda_lock,
  660. .unlock = coda_unlock,
  661. };
  662. static void set_default_params(struct coda_ctx *ctx)
  663. {
  664. struct coda_dev *dev = ctx->dev;
  665. ctx->params.codec_mode = CODA_MODE_INVALID;
  666. ctx->colorspace = V4L2_COLORSPACE_REC709;
  667. ctx->params.framerate = 30;
  668. ctx->aborting = 0;
  669. /* Default formats for output and input queues */
  670. ctx->q_data[V4L2_M2M_SRC].fmt = &dev->devtype->formats[0];
  671. ctx->q_data[V4L2_M2M_DST].fmt = &dev->devtype->formats[1];
  672. ctx->q_data[V4L2_M2M_SRC].width = MAX_W;
  673. ctx->q_data[V4L2_M2M_SRC].height = MAX_H;
  674. ctx->q_data[V4L2_M2M_SRC].sizeimage = (MAX_W * MAX_H * 3) / 2;
  675. ctx->q_data[V4L2_M2M_DST].width = MAX_W;
  676. ctx->q_data[V4L2_M2M_DST].height = MAX_H;
  677. ctx->q_data[V4L2_M2M_DST].sizeimage = CODA_MAX_FRAME_SIZE;
  678. }
  679. /*
  680. * Queue operations
  681. */
  682. static int coda_queue_setup(struct vb2_queue *vq,
  683. const struct v4l2_format *fmt,
  684. unsigned int *nbuffers, unsigned int *nplanes,
  685. unsigned int sizes[], void *alloc_ctxs[])
  686. {
  687. struct coda_ctx *ctx = vb2_get_drv_priv(vq);
  688. struct coda_q_data *q_data;
  689. unsigned int size;
  690. q_data = get_q_data(ctx, vq->type);
  691. size = q_data->sizeimage;
  692. *nplanes = 1;
  693. sizes[0] = size;
  694. alloc_ctxs[0] = ctx->dev->alloc_ctx;
  695. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  696. "get %d buffer(s) of size %d each.\n", *nbuffers, size);
  697. return 0;
  698. }
  699. static int coda_buf_prepare(struct vb2_buffer *vb)
  700. {
  701. struct coda_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
  702. struct coda_q_data *q_data;
  703. q_data = get_q_data(ctx, vb->vb2_queue->type);
  704. if (vb2_plane_size(vb, 0) < q_data->sizeimage) {
  705. v4l2_warn(&ctx->dev->v4l2_dev,
  706. "%s data will not fit into plane (%lu < %lu)\n",
  707. __func__, vb2_plane_size(vb, 0),
  708. (long)q_data->sizeimage);
  709. return -EINVAL;
  710. }
  711. vb2_set_plane_payload(vb, 0, q_data->sizeimage);
  712. return 0;
  713. }
  714. static void coda_buf_queue(struct vb2_buffer *vb)
  715. {
  716. struct coda_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
  717. v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
  718. }
  719. static void coda_wait_prepare(struct vb2_queue *q)
  720. {
  721. struct coda_ctx *ctx = vb2_get_drv_priv(q);
  722. coda_unlock(ctx);
  723. }
  724. static void coda_wait_finish(struct vb2_queue *q)
  725. {
  726. struct coda_ctx *ctx = vb2_get_drv_priv(q);
  727. coda_lock(ctx);
  728. }
  729. static void coda_free_framebuffers(struct coda_ctx *ctx)
  730. {
  731. int i;
  732. for (i = 0; i < CODA_MAX_FRAMEBUFFERS; i++) {
  733. if (ctx->internal_frames[i].vaddr) {
  734. dma_free_coherent(&ctx->dev->plat_dev->dev,
  735. ctx->internal_frames[i].size,
  736. ctx->internal_frames[i].vaddr,
  737. ctx->internal_frames[i].paddr);
  738. ctx->internal_frames[i].vaddr = NULL;
  739. }
  740. }
  741. }
  742. static int coda_alloc_framebuffers(struct coda_ctx *ctx, struct coda_q_data *q_data, u32 fourcc)
  743. {
  744. struct coda_dev *dev = ctx->dev;
  745. int height = q_data->height;
  746. int width = q_data->width;
  747. u32 *p;
  748. int i;
  749. /* Allocate frame buffers */
  750. ctx->num_internal_frames = CODA_MAX_FRAMEBUFFERS;
  751. for (i = 0; i < ctx->num_internal_frames; i++) {
  752. ctx->internal_frames[i].size = q_data->sizeimage;
  753. if (fourcc == V4L2_PIX_FMT_H264 && dev->devtype->product != CODA_DX6)
  754. ctx->internal_frames[i].size += width / 2 * height / 2;
  755. ctx->internal_frames[i].vaddr = dma_alloc_coherent(
  756. &dev->plat_dev->dev, ctx->internal_frames[i].size,
  757. &ctx->internal_frames[i].paddr, GFP_KERNEL);
  758. if (!ctx->internal_frames[i].vaddr) {
  759. coda_free_framebuffers(ctx);
  760. return -ENOMEM;
  761. }
  762. }
  763. /* Register frame buffers in the parameter buffer */
  764. p = ctx->parabuf.vaddr;
  765. if (dev->devtype->product == CODA_DX6) {
  766. for (i = 0; i < ctx->num_internal_frames; i++) {
  767. p[i * 3] = ctx->internal_frames[i].paddr; /* Y */
  768. p[i * 3 + 1] = p[i * 3] + width * height; /* Cb */
  769. p[i * 3 + 2] = p[i * 3 + 1] + width / 2 * height / 2; /* Cr */
  770. }
  771. } else {
  772. for (i = 0; i < ctx->num_internal_frames; i += 2) {
  773. p[i * 3 + 1] = ctx->internal_frames[i].paddr; /* Y */
  774. p[i * 3] = p[i * 3 + 1] + width * height; /* Cb */
  775. p[i * 3 + 3] = p[i * 3] + (width / 2) * (height / 2); /* Cr */
  776. if (fourcc == V4L2_PIX_FMT_H264)
  777. p[96 + i + 1] = p[i * 3 + 3] + (width / 2) * (height / 2);
  778. if (i + 1 < ctx->num_internal_frames) {
  779. p[i * 3 + 2] = ctx->internal_frames[i+1].paddr; /* Y */
  780. p[i * 3 + 5] = p[i * 3 + 2] + width * height ; /* Cb */
  781. p[i * 3 + 4] = p[i * 3 + 5] + (width / 2) * (height / 2); /* Cr */
  782. if (fourcc == V4L2_PIX_FMT_H264)
  783. p[96 + i] = p[i * 3 + 4] + (width / 2) * (height / 2);
  784. }
  785. }
  786. }
  787. return 0;
  788. }
  789. static int coda_start_streaming(struct vb2_queue *q, unsigned int count)
  790. {
  791. struct coda_ctx *ctx = vb2_get_drv_priv(q);
  792. struct v4l2_device *v4l2_dev = &ctx->dev->v4l2_dev;
  793. u32 bitstream_buf, bitstream_size;
  794. struct coda_dev *dev = ctx->dev;
  795. struct coda_q_data *q_data_src, *q_data_dst;
  796. struct vb2_buffer *buf;
  797. u32 dst_fourcc;
  798. u32 value;
  799. int ret;
  800. if (count < 1)
  801. return -EINVAL;
  802. if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
  803. ctx->rawstreamon = 1;
  804. else
  805. ctx->compstreamon = 1;
  806. /* Don't start the coda unless both queues are on */
  807. if (!(ctx->rawstreamon & ctx->compstreamon))
  808. return 0;
  809. if (coda_isbusy(dev))
  810. if (wait_for_completion_interruptible_timeout(&dev->done, HZ) <= 0)
  811. return -EBUSY;
  812. ctx->gopcounter = ctx->params.gop_size - 1;
  813. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  814. buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
  815. bitstream_buf = vb2_dma_contig_plane_dma_addr(buf, 0);
  816. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  817. bitstream_size = q_data_dst->sizeimage;
  818. dst_fourcc = q_data_dst->fmt->fourcc;
  819. /* Find out whether coda must encode or decode */
  820. if (q_data_src->fmt->type == CODA_FMT_RAW &&
  821. q_data_dst->fmt->type == CODA_FMT_ENC) {
  822. ctx->inst_type = CODA_INST_ENCODER;
  823. } else if (q_data_src->fmt->type == CODA_FMT_ENC &&
  824. q_data_dst->fmt->type == CODA_FMT_RAW) {
  825. ctx->inst_type = CODA_INST_DECODER;
  826. v4l2_err(v4l2_dev, "decoding not supported.\n");
  827. return -EINVAL;
  828. } else {
  829. v4l2_err(v4l2_dev, "couldn't tell instance type.\n");
  830. return -EINVAL;
  831. }
  832. if (!coda_is_initialized(dev)) {
  833. v4l2_err(v4l2_dev, "coda is not initialized.\n");
  834. return -EFAULT;
  835. }
  836. coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
  837. coda_write(dev, bitstream_buf, CODA_REG_BIT_RD_PTR(ctx->idx));
  838. coda_write(dev, bitstream_buf, CODA_REG_BIT_WR_PTR(ctx->idx));
  839. switch (dev->devtype->product) {
  840. case CODA_DX6:
  841. coda_write(dev, CODADX6_STREAM_BUF_DYNALLOC_EN |
  842. CODADX6_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
  843. break;
  844. default:
  845. coda_write(dev, CODA7_STREAM_BUF_DYNALLOC_EN |
  846. CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
  847. }
  848. if (dev->devtype->product == CODA_DX6) {
  849. /* Configure the coda */
  850. coda_write(dev, dev->iram_paddr, CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR);
  851. }
  852. /* Could set rotation here if needed */
  853. switch (dev->devtype->product) {
  854. case CODA_DX6:
  855. value = (q_data_src->width & CODADX6_PICWIDTH_MASK) << CODADX6_PICWIDTH_OFFSET;
  856. break;
  857. default:
  858. value = (q_data_src->width & CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
  859. }
  860. value |= (q_data_src->height & CODA_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
  861. coda_write(dev, value, CODA_CMD_ENC_SEQ_SRC_SIZE);
  862. coda_write(dev, ctx->params.framerate,
  863. CODA_CMD_ENC_SEQ_SRC_F_RATE);
  864. switch (dst_fourcc) {
  865. case V4L2_PIX_FMT_MPEG4:
  866. if (dev->devtype->product == CODA_DX6)
  867. ctx->params.codec_mode = CODADX6_MODE_ENCODE_MP4;
  868. else
  869. ctx->params.codec_mode = CODA7_MODE_ENCODE_MP4;
  870. coda_write(dev, CODA_STD_MPEG4, CODA_CMD_ENC_SEQ_COD_STD);
  871. coda_write(dev, 0, CODA_CMD_ENC_SEQ_MP4_PARA);
  872. break;
  873. case V4L2_PIX_FMT_H264:
  874. if (dev->devtype->product == CODA_DX6)
  875. ctx->params.codec_mode = CODADX6_MODE_ENCODE_H264;
  876. else
  877. ctx->params.codec_mode = CODA7_MODE_ENCODE_H264;
  878. coda_write(dev, CODA_STD_H264, CODA_CMD_ENC_SEQ_COD_STD);
  879. coda_write(dev, 0, CODA_CMD_ENC_SEQ_264_PARA);
  880. break;
  881. default:
  882. v4l2_err(v4l2_dev,
  883. "dst format (0x%08x) invalid.\n", dst_fourcc);
  884. return -EINVAL;
  885. }
  886. switch (ctx->params.slice_mode) {
  887. case V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE:
  888. value = 0;
  889. break;
  890. case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB:
  891. value = (ctx->params.slice_max_mb & CODA_SLICING_SIZE_MASK) << CODA_SLICING_SIZE_OFFSET;
  892. value |= (1 & CODA_SLICING_UNIT_MASK) << CODA_SLICING_UNIT_OFFSET;
  893. value |= 1 & CODA_SLICING_MODE_MASK;
  894. break;
  895. case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES:
  896. value = (ctx->params.slice_max_bits & CODA_SLICING_SIZE_MASK) << CODA_SLICING_SIZE_OFFSET;
  897. value |= (0 & CODA_SLICING_UNIT_MASK) << CODA_SLICING_UNIT_OFFSET;
  898. value |= 1 & CODA_SLICING_MODE_MASK;
  899. break;
  900. }
  901. coda_write(dev, value, CODA_CMD_ENC_SEQ_SLICE_MODE);
  902. value = ctx->params.gop_size & CODA_GOP_SIZE_MASK;
  903. coda_write(dev, value, CODA_CMD_ENC_SEQ_GOP_SIZE);
  904. if (ctx->params.bitrate) {
  905. /* Rate control enabled */
  906. value = (ctx->params.bitrate & CODA_RATECONTROL_BITRATE_MASK) << CODA_RATECONTROL_BITRATE_OFFSET;
  907. value |= 1 & CODA_RATECONTROL_ENABLE_MASK;
  908. } else {
  909. value = 0;
  910. }
  911. coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_PARA);
  912. coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_BUF_SIZE);
  913. coda_write(dev, 0, CODA_CMD_ENC_SEQ_INTRA_REFRESH);
  914. coda_write(dev, bitstream_buf, CODA_CMD_ENC_SEQ_BB_START);
  915. coda_write(dev, bitstream_size / 1024, CODA_CMD_ENC_SEQ_BB_SIZE);
  916. /* set default gamma */
  917. value = (CODA_DEFAULT_GAMMA & CODA_GAMMA_MASK) << CODA_GAMMA_OFFSET;
  918. coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_GAMMA);
  919. value = (CODA_DEFAULT_GAMMA > 0) << CODA_OPTION_GAMMA_OFFSET;
  920. value |= (0 & CODA_OPTION_SLICEREPORT_MASK) << CODA_OPTION_SLICEREPORT_OFFSET;
  921. coda_write(dev, value, CODA_CMD_ENC_SEQ_OPTION);
  922. if (dst_fourcc == V4L2_PIX_FMT_H264) {
  923. value = (FMO_SLICE_SAVE_BUF_SIZE << 7);
  924. value |= (0 & CODA_FMOPARAM_TYPE_MASK) << CODA_FMOPARAM_TYPE_OFFSET;
  925. value |= 0 & CODA_FMOPARAM_SLICENUM_MASK;
  926. if (dev->devtype->product == CODA_DX6) {
  927. coda_write(dev, value, CODADX6_CMD_ENC_SEQ_FMO);
  928. } else {
  929. coda_write(dev, dev->iram_paddr, CODA7_CMD_ENC_SEQ_SEARCH_BASE);
  930. coda_write(dev, 48 * 1024, CODA7_CMD_ENC_SEQ_SEARCH_SIZE);
  931. }
  932. }
  933. if (coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT)) {
  934. v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
  935. return -ETIMEDOUT;
  936. }
  937. if (coda_read(dev, CODA_RET_ENC_SEQ_SUCCESS) == 0)
  938. return -EFAULT;
  939. ret = coda_alloc_framebuffers(ctx, q_data_src, dst_fourcc);
  940. if (ret < 0)
  941. return ret;
  942. coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
  943. coda_write(dev, round_up(q_data_src->width, 8), CODA_CMD_SET_FRAME_BUF_STRIDE);
  944. if (dev->devtype->product != CODA_DX6) {
  945. coda_write(dev, round_up(q_data_src->width, 8), CODA7_CMD_SET_FRAME_SOURCE_BUF_STRIDE);
  946. coda_write(dev, dev->iram_paddr + 48 * 1024, CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
  947. coda_write(dev, dev->iram_paddr + 53 * 1024, CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
  948. coda_write(dev, dev->iram_paddr + 58 * 1024, CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
  949. coda_write(dev, dev->iram_paddr + 68 * 1024, CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
  950. coda_write(dev, 0x0, CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
  951. }
  952. if (coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF)) {
  953. v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n");
  954. return -ETIMEDOUT;
  955. }
  956. /* Save stream headers */
  957. buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
  958. switch (dst_fourcc) {
  959. case V4L2_PIX_FMT_H264:
  960. /*
  961. * Get SPS in the first frame and copy it to an
  962. * intermediate buffer.
  963. */
  964. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
  965. coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
  966. coda_write(dev, CODA_HEADER_H264_SPS, CODA_CMD_ENC_HEADER_CODE);
  967. if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
  968. v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
  969. return -ETIMEDOUT;
  970. }
  971. ctx->vpu_header_size[0] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
  972. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  973. memcpy(&ctx->vpu_header[0][0], vb2_plane_vaddr(buf, 0),
  974. ctx->vpu_header_size[0]);
  975. /*
  976. * Get PPS in the first frame and copy it to an
  977. * intermediate buffer.
  978. */
  979. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
  980. coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
  981. coda_write(dev, CODA_HEADER_H264_PPS, CODA_CMD_ENC_HEADER_CODE);
  982. if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
  983. v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
  984. return -ETIMEDOUT;
  985. }
  986. ctx->vpu_header_size[1] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
  987. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  988. memcpy(&ctx->vpu_header[1][0], vb2_plane_vaddr(buf, 0),
  989. ctx->vpu_header_size[1]);
  990. ctx->vpu_header_size[2] = 0;
  991. break;
  992. case V4L2_PIX_FMT_MPEG4:
  993. /*
  994. * Get VOS in the first frame and copy it to an
  995. * intermediate buffer
  996. */
  997. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
  998. coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
  999. coda_write(dev, CODA_HEADER_MP4V_VOS, CODA_CMD_ENC_HEADER_CODE);
  1000. if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
  1001. v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
  1002. return -ETIMEDOUT;
  1003. }
  1004. ctx->vpu_header_size[0] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
  1005. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  1006. memcpy(&ctx->vpu_header[0][0], vb2_plane_vaddr(buf, 0),
  1007. ctx->vpu_header_size[0]);
  1008. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
  1009. coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
  1010. coda_write(dev, CODA_HEADER_MP4V_VIS, CODA_CMD_ENC_HEADER_CODE);
  1011. if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
  1012. v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER failed\n");
  1013. return -ETIMEDOUT;
  1014. }
  1015. ctx->vpu_header_size[1] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
  1016. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  1017. memcpy(&ctx->vpu_header[1][0], vb2_plane_vaddr(buf, 0),
  1018. ctx->vpu_header_size[1]);
  1019. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
  1020. coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
  1021. coda_write(dev, CODA_HEADER_MP4V_VOL, CODA_CMD_ENC_HEADER_CODE);
  1022. if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
  1023. v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER failed\n");
  1024. return -ETIMEDOUT;
  1025. }
  1026. ctx->vpu_header_size[2] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
  1027. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  1028. memcpy(&ctx->vpu_header[2][0], vb2_plane_vaddr(buf, 0),
  1029. ctx->vpu_header_size[2]);
  1030. break;
  1031. default:
  1032. /* No more formats need to save headers at the moment */
  1033. break;
  1034. }
  1035. return 0;
  1036. }
  1037. static int coda_stop_streaming(struct vb2_queue *q)
  1038. {
  1039. struct coda_ctx *ctx = vb2_get_drv_priv(q);
  1040. struct coda_dev *dev = ctx->dev;
  1041. if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
  1042. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1043. "%s: output\n", __func__);
  1044. ctx->rawstreamon = 0;
  1045. } else {
  1046. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1047. "%s: capture\n", __func__);
  1048. ctx->compstreamon = 0;
  1049. }
  1050. /* Don't stop the coda unless both queues are off */
  1051. if (ctx->rawstreamon || ctx->compstreamon)
  1052. return 0;
  1053. if (coda_isbusy(dev)) {
  1054. if (wait_for_completion_interruptible_timeout(&dev->done, HZ) <= 0) {
  1055. v4l2_warn(&dev->v4l2_dev,
  1056. "%s: timeout, sending SEQ_END anyway\n", __func__);
  1057. }
  1058. }
  1059. cancel_delayed_work(&dev->timeout);
  1060. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1061. "%s: sent command 'SEQ_END' to coda\n", __func__);
  1062. if (coda_command_sync(ctx, CODA_COMMAND_SEQ_END)) {
  1063. v4l2_err(&dev->v4l2_dev,
  1064. "CODA_COMMAND_SEQ_END failed\n");
  1065. return -ETIMEDOUT;
  1066. }
  1067. coda_free_framebuffers(ctx);
  1068. return 0;
  1069. }
  1070. static struct vb2_ops coda_qops = {
  1071. .queue_setup = coda_queue_setup,
  1072. .buf_prepare = coda_buf_prepare,
  1073. .buf_queue = coda_buf_queue,
  1074. .wait_prepare = coda_wait_prepare,
  1075. .wait_finish = coda_wait_finish,
  1076. .start_streaming = coda_start_streaming,
  1077. .stop_streaming = coda_stop_streaming,
  1078. };
  1079. static int coda_s_ctrl(struct v4l2_ctrl *ctrl)
  1080. {
  1081. struct coda_ctx *ctx =
  1082. container_of(ctrl->handler, struct coda_ctx, ctrls);
  1083. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1084. "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val);
  1085. switch (ctrl->id) {
  1086. case V4L2_CID_HFLIP:
  1087. if (ctrl->val)
  1088. ctx->params.rot_mode |= CODA_MIR_HOR;
  1089. else
  1090. ctx->params.rot_mode &= ~CODA_MIR_HOR;
  1091. break;
  1092. case V4L2_CID_VFLIP:
  1093. if (ctrl->val)
  1094. ctx->params.rot_mode |= CODA_MIR_VER;
  1095. else
  1096. ctx->params.rot_mode &= ~CODA_MIR_VER;
  1097. break;
  1098. case V4L2_CID_MPEG_VIDEO_BITRATE:
  1099. ctx->params.bitrate = ctrl->val / 1000;
  1100. break;
  1101. case V4L2_CID_MPEG_VIDEO_GOP_SIZE:
  1102. ctx->params.gop_size = ctrl->val;
  1103. break;
  1104. case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP:
  1105. ctx->params.h264_intra_qp = ctrl->val;
  1106. break;
  1107. case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP:
  1108. ctx->params.h264_inter_qp = ctrl->val;
  1109. break;
  1110. case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP:
  1111. ctx->params.mpeg4_intra_qp = ctrl->val;
  1112. break;
  1113. case V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP:
  1114. ctx->params.mpeg4_inter_qp = ctrl->val;
  1115. break;
  1116. case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE:
  1117. ctx->params.slice_mode = ctrl->val;
  1118. break;
  1119. case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB:
  1120. ctx->params.slice_max_mb = ctrl->val;
  1121. break;
  1122. case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES:
  1123. ctx->params.slice_max_bits = ctrl->val * 8;
  1124. break;
  1125. case V4L2_CID_MPEG_VIDEO_HEADER_MODE:
  1126. break;
  1127. default:
  1128. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1129. "Invalid control, id=%d, val=%d\n",
  1130. ctrl->id, ctrl->val);
  1131. return -EINVAL;
  1132. }
  1133. return 0;
  1134. }
  1135. static struct v4l2_ctrl_ops coda_ctrl_ops = {
  1136. .s_ctrl = coda_s_ctrl,
  1137. };
  1138. static int coda_ctrls_setup(struct coda_ctx *ctx)
  1139. {
  1140. v4l2_ctrl_handler_init(&ctx->ctrls, 9);
  1141. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1142. V4L2_CID_HFLIP, 0, 1, 1, 0);
  1143. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1144. V4L2_CID_VFLIP, 0, 1, 1, 0);
  1145. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1146. V4L2_CID_MPEG_VIDEO_BITRATE, 0, 32767000, 1, 0);
  1147. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1148. V4L2_CID_MPEG_VIDEO_GOP_SIZE, 1, 60, 1, 16);
  1149. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1150. V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP, 1, 51, 1, 25);
  1151. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1152. V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP, 1, 51, 1, 25);
  1153. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1154. V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP, 1, 31, 1, 2);
  1155. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1156. V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP, 1, 31, 1, 2);
  1157. v4l2_ctrl_new_std_menu(&ctx->ctrls, &coda_ctrl_ops,
  1158. V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE,
  1159. V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES, 0x0,
  1160. V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE);
  1161. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1162. V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB, 1, 0x3fffffff, 1, 1);
  1163. v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
  1164. V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES, 1, 0x3fffffff, 1, 500);
  1165. v4l2_ctrl_new_std_menu(&ctx->ctrls, &coda_ctrl_ops,
  1166. V4L2_CID_MPEG_VIDEO_HEADER_MODE,
  1167. V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
  1168. (1 << V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE),
  1169. V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME);
  1170. if (ctx->ctrls.error) {
  1171. v4l2_err(&ctx->dev->v4l2_dev, "control initialization error (%d)",
  1172. ctx->ctrls.error);
  1173. return -EINVAL;
  1174. }
  1175. return v4l2_ctrl_handler_setup(&ctx->ctrls);
  1176. }
  1177. static int coda_queue_init(void *priv, struct vb2_queue *src_vq,
  1178. struct vb2_queue *dst_vq)
  1179. {
  1180. struct coda_ctx *ctx = priv;
  1181. int ret;
  1182. src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
  1183. src_vq->io_modes = VB2_MMAP | VB2_USERPTR;
  1184. src_vq->drv_priv = ctx;
  1185. src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
  1186. src_vq->ops = &coda_qops;
  1187. src_vq->mem_ops = &vb2_dma_contig_memops;
  1188. ret = vb2_queue_init(src_vq);
  1189. if (ret)
  1190. return ret;
  1191. dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
  1192. dst_vq->io_modes = VB2_MMAP | VB2_USERPTR;
  1193. dst_vq->drv_priv = ctx;
  1194. dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
  1195. dst_vq->ops = &coda_qops;
  1196. dst_vq->mem_ops = &vb2_dma_contig_memops;
  1197. return vb2_queue_init(dst_vq);
  1198. }
  1199. static int coda_next_free_instance(struct coda_dev *dev)
  1200. {
  1201. return ffz(dev->instance_mask);
  1202. }
  1203. static int coda_open(struct file *file)
  1204. {
  1205. struct coda_dev *dev = video_drvdata(file);
  1206. struct coda_ctx *ctx = NULL;
  1207. int ret = 0;
  1208. int idx;
  1209. idx = coda_next_free_instance(dev);
  1210. if (idx >= CODA_MAX_INSTANCES)
  1211. return -EBUSY;
  1212. set_bit(idx, &dev->instance_mask);
  1213. ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
  1214. if (!ctx)
  1215. return -ENOMEM;
  1216. v4l2_fh_init(&ctx->fh, video_devdata(file));
  1217. file->private_data = &ctx->fh;
  1218. v4l2_fh_add(&ctx->fh);
  1219. ctx->dev = dev;
  1220. ctx->idx = idx;
  1221. set_default_params(ctx);
  1222. ctx->m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx,
  1223. &coda_queue_init);
  1224. if (IS_ERR(ctx->m2m_ctx)) {
  1225. int ret = PTR_ERR(ctx->m2m_ctx);
  1226. v4l2_err(&dev->v4l2_dev, "%s return error (%d)\n",
  1227. __func__, ret);
  1228. goto err;
  1229. }
  1230. ret = coda_ctrls_setup(ctx);
  1231. if (ret) {
  1232. v4l2_err(&dev->v4l2_dev, "failed to setup coda controls\n");
  1233. goto err;
  1234. }
  1235. ctx->fh.ctrl_handler = &ctx->ctrls;
  1236. ctx->parabuf.vaddr = dma_alloc_coherent(&dev->plat_dev->dev,
  1237. CODA_PARA_BUF_SIZE, &ctx->parabuf.paddr, GFP_KERNEL);
  1238. if (!ctx->parabuf.vaddr) {
  1239. v4l2_err(&dev->v4l2_dev, "failed to allocate parabuf");
  1240. ret = -ENOMEM;
  1241. goto err;
  1242. }
  1243. coda_lock(ctx);
  1244. list_add(&ctx->list, &dev->instances);
  1245. coda_unlock(ctx);
  1246. clk_prepare_enable(dev->clk_per);
  1247. clk_prepare_enable(dev->clk_ahb);
  1248. v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "Created instance %d (%p)\n",
  1249. ctx->idx, ctx);
  1250. return 0;
  1251. err:
  1252. v4l2_fh_del(&ctx->fh);
  1253. v4l2_fh_exit(&ctx->fh);
  1254. kfree(ctx);
  1255. return ret;
  1256. }
  1257. static int coda_release(struct file *file)
  1258. {
  1259. struct coda_dev *dev = video_drvdata(file);
  1260. struct coda_ctx *ctx = fh_to_ctx(file->private_data);
  1261. v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "Releasing instance %p\n",
  1262. ctx);
  1263. coda_lock(ctx);
  1264. list_del(&ctx->list);
  1265. coda_unlock(ctx);
  1266. dma_free_coherent(&dev->plat_dev->dev, CODA_PARA_BUF_SIZE,
  1267. ctx->parabuf.vaddr, ctx->parabuf.paddr);
  1268. v4l2_m2m_ctx_release(ctx->m2m_ctx);
  1269. v4l2_ctrl_handler_free(&ctx->ctrls);
  1270. clk_disable_unprepare(dev->clk_per);
  1271. clk_disable_unprepare(dev->clk_ahb);
  1272. v4l2_fh_del(&ctx->fh);
  1273. v4l2_fh_exit(&ctx->fh);
  1274. clear_bit(ctx->idx, &dev->instance_mask);
  1275. kfree(ctx);
  1276. return 0;
  1277. }
  1278. static unsigned int coda_poll(struct file *file,
  1279. struct poll_table_struct *wait)
  1280. {
  1281. struct coda_ctx *ctx = fh_to_ctx(file->private_data);
  1282. int ret;
  1283. coda_lock(ctx);
  1284. ret = v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
  1285. coda_unlock(ctx);
  1286. return ret;
  1287. }
  1288. static int coda_mmap(struct file *file, struct vm_area_struct *vma)
  1289. {
  1290. struct coda_ctx *ctx = fh_to_ctx(file->private_data);
  1291. return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
  1292. }
  1293. static const struct v4l2_file_operations coda_fops = {
  1294. .owner = THIS_MODULE,
  1295. .open = coda_open,
  1296. .release = coda_release,
  1297. .poll = coda_poll,
  1298. .unlocked_ioctl = video_ioctl2,
  1299. .mmap = coda_mmap,
  1300. };
  1301. static irqreturn_t coda_irq_handler(int irq, void *data)
  1302. {
  1303. struct vb2_buffer *src_buf, *dst_buf;
  1304. struct coda_dev *dev = data;
  1305. u32 wr_ptr, start_ptr;
  1306. struct coda_ctx *ctx;
  1307. cancel_delayed_work(&dev->timeout);
  1308. /* read status register to attend the IRQ */
  1309. coda_read(dev, CODA_REG_BIT_INT_STATUS);
  1310. coda_write(dev, CODA_REG_BIT_INT_CLEAR_SET,
  1311. CODA_REG_BIT_INT_CLEAR);
  1312. ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
  1313. if (ctx == NULL) {
  1314. v4l2_err(&dev->v4l2_dev, "Instance released before the end of transaction\n");
  1315. return IRQ_HANDLED;
  1316. }
  1317. if (ctx->aborting) {
  1318. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1319. "task has been aborted\n");
  1320. return IRQ_HANDLED;
  1321. }
  1322. if (coda_isbusy(ctx->dev)) {
  1323. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1324. "coda is still busy!!!!\n");
  1325. return IRQ_NONE;
  1326. }
  1327. complete(&dev->done);
  1328. src_buf = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
  1329. dst_buf = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
  1330. /* Get results from the coda */
  1331. coda_read(dev, CODA_RET_ENC_PIC_TYPE);
  1332. start_ptr = coda_read(dev, CODA_CMD_ENC_PIC_BB_START);
  1333. wr_ptr = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx));
  1334. /* Calculate bytesused field */
  1335. if (dst_buf->v4l2_buf.sequence == 0) {
  1336. dst_buf->v4l2_planes[0].bytesused = (wr_ptr - start_ptr) +
  1337. ctx->vpu_header_size[0] +
  1338. ctx->vpu_header_size[1] +
  1339. ctx->vpu_header_size[2];
  1340. } else {
  1341. dst_buf->v4l2_planes[0].bytesused = (wr_ptr - start_ptr);
  1342. }
  1343. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, "frame size = %u\n",
  1344. wr_ptr - start_ptr);
  1345. coda_read(dev, CODA_RET_ENC_PIC_SLICE_NUM);
  1346. coda_read(dev, CODA_RET_ENC_PIC_FLAG);
  1347. if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
  1348. dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
  1349. dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
  1350. } else {
  1351. dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
  1352. dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
  1353. }
  1354. v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
  1355. v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);
  1356. ctx->gopcounter--;
  1357. if (ctx->gopcounter < 0)
  1358. ctx->gopcounter = ctx->params.gop_size - 1;
  1359. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1360. "job finished: encoding frame (%d) (%s)\n",
  1361. dst_buf->v4l2_buf.sequence,
  1362. (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
  1363. "KEYFRAME" : "PFRAME");
  1364. v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->m2m_ctx);
  1365. return IRQ_HANDLED;
  1366. }
  1367. static void coda_timeout(struct work_struct *work)
  1368. {
  1369. struct coda_ctx *ctx;
  1370. struct coda_dev *dev = container_of(to_delayed_work(work),
  1371. struct coda_dev, timeout);
  1372. if (completion_done(&dev->done))
  1373. return;
  1374. complete(&dev->done);
  1375. v4l2_err(&dev->v4l2_dev, "CODA PIC_RUN timeout, stopping all streams\n");
  1376. mutex_lock(&dev->dev_mutex);
  1377. list_for_each_entry(ctx, &dev->instances, list) {
  1378. v4l2_m2m_streamoff(NULL, ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1379. v4l2_m2m_streamoff(NULL, ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1380. }
  1381. mutex_unlock(&dev->dev_mutex);
  1382. }
  1383. static u32 coda_supported_firmwares[] = {
  1384. CODA_FIRMWARE_VERNUM(CODA_DX6, 2, 2, 5),
  1385. CODA_FIRMWARE_VERNUM(CODA_7541, 13, 4, 29),
  1386. };
  1387. static bool coda_firmware_supported(u32 vernum)
  1388. {
  1389. int i;
  1390. for (i = 0; i < ARRAY_SIZE(coda_supported_firmwares); i++)
  1391. if (vernum == coda_supported_firmwares[i])
  1392. return true;
  1393. return false;
  1394. }
  1395. static char *coda_product_name(int product)
  1396. {
  1397. static char buf[9];
  1398. switch (product) {
  1399. case CODA_DX6:
  1400. return "CodaDx6";
  1401. case CODA_7541:
  1402. return "CODA7541";
  1403. default:
  1404. snprintf(buf, sizeof(buf), "(0x%04x)", product);
  1405. return buf;
  1406. }
  1407. }
  1408. static int coda_hw_init(struct coda_dev *dev)
  1409. {
  1410. u16 product, major, minor, release;
  1411. u32 data;
  1412. u16 *p;
  1413. int i;
  1414. clk_prepare_enable(dev->clk_per);
  1415. clk_prepare_enable(dev->clk_ahb);
  1416. /*
  1417. * Copy the first CODA_ISRAM_SIZE in the internal SRAM.
  1418. * The 16-bit chars in the code buffer are in memory access
  1419. * order, re-sort them to CODA order for register download.
  1420. * Data in this SRAM survives a reboot.
  1421. */
  1422. p = (u16 *)dev->codebuf.vaddr;
  1423. if (dev->devtype->product == CODA_DX6) {
  1424. for (i = 0; i < (CODA_ISRAM_SIZE / 2); i++) {
  1425. data = CODA_DOWN_ADDRESS_SET(i) |
  1426. CODA_DOWN_DATA_SET(p[i ^ 1]);
  1427. coda_write(dev, data, CODA_REG_BIT_CODE_DOWN);
  1428. }
  1429. } else {
  1430. for (i = 0; i < (CODA_ISRAM_SIZE / 2); i++) {
  1431. data = CODA_DOWN_ADDRESS_SET(i) |
  1432. CODA_DOWN_DATA_SET(p[round_down(i, 4) +
  1433. 3 - (i % 4)]);
  1434. coda_write(dev, data, CODA_REG_BIT_CODE_DOWN);
  1435. }
  1436. }
  1437. /* Tell the BIT where to find everything it needs */
  1438. coda_write(dev, dev->workbuf.paddr,
  1439. CODA_REG_BIT_WORK_BUF_ADDR);
  1440. coda_write(dev, dev->codebuf.paddr,
  1441. CODA_REG_BIT_CODE_BUF_ADDR);
  1442. coda_write(dev, 0, CODA_REG_BIT_CODE_RUN);
  1443. /* Set default values */
  1444. switch (dev->devtype->product) {
  1445. case CODA_DX6:
  1446. coda_write(dev, CODADX6_STREAM_BUF_PIC_FLUSH, CODA_REG_BIT_STREAM_CTRL);
  1447. break;
  1448. default:
  1449. coda_write(dev, CODA7_STREAM_BUF_PIC_FLUSH, CODA_REG_BIT_STREAM_CTRL);
  1450. }
  1451. coda_write(dev, 0, CODA_REG_BIT_FRAME_MEM_CTRL);
  1452. if (dev->devtype->product != CODA_DX6)
  1453. coda_write(dev, 0, CODA7_REG_BIT_AXI_SRAM_USE);
  1454. coda_write(dev, CODA_INT_INTERRUPT_ENABLE,
  1455. CODA_REG_BIT_INT_ENABLE);
  1456. /* Reset VPU and start processor */
  1457. data = coda_read(dev, CODA_REG_BIT_CODE_RESET);
  1458. data |= CODA_REG_RESET_ENABLE;
  1459. coda_write(dev, data, CODA_REG_BIT_CODE_RESET);
  1460. udelay(10);
  1461. data &= ~CODA_REG_RESET_ENABLE;
  1462. coda_write(dev, data, CODA_REG_BIT_CODE_RESET);
  1463. coda_write(dev, CODA_REG_RUN_ENABLE, CODA_REG_BIT_CODE_RUN);
  1464. /* Load firmware */
  1465. coda_write(dev, 0, CODA_CMD_FIRMWARE_VERNUM);
  1466. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  1467. coda_write(dev, 0, CODA_REG_BIT_RUN_INDEX);
  1468. coda_write(dev, 0, CODA_REG_BIT_RUN_COD_STD);
  1469. coda_write(dev, CODA_COMMAND_FIRMWARE_GET, CODA_REG_BIT_RUN_COMMAND);
  1470. if (coda_wait_timeout(dev)) {
  1471. clk_disable_unprepare(dev->clk_per);
  1472. clk_disable_unprepare(dev->clk_ahb);
  1473. v4l2_err(&dev->v4l2_dev, "firmware get command error\n");
  1474. return -EIO;
  1475. }
  1476. /* Check we are compatible with the loaded firmware */
  1477. data = coda_read(dev, CODA_CMD_FIRMWARE_VERNUM);
  1478. product = CODA_FIRMWARE_PRODUCT(data);
  1479. major = CODA_FIRMWARE_MAJOR(data);
  1480. minor = CODA_FIRMWARE_MINOR(data);
  1481. release = CODA_FIRMWARE_RELEASE(data);
  1482. clk_disable_unprepare(dev->clk_per);
  1483. clk_disable_unprepare(dev->clk_ahb);
  1484. if (product != dev->devtype->product) {
  1485. v4l2_err(&dev->v4l2_dev, "Wrong firmware. Hw: %s, Fw: %s,"
  1486. " Version: %u.%u.%u\n",
  1487. coda_product_name(dev->devtype->product),
  1488. coda_product_name(product), major, minor, release);
  1489. return -EINVAL;
  1490. }
  1491. v4l2_info(&dev->v4l2_dev, "Initialized %s.\n",
  1492. coda_product_name(product));
  1493. if (coda_firmware_supported(data)) {
  1494. v4l2_info(&dev->v4l2_dev, "Firmware version: %u.%u.%u\n",
  1495. major, minor, release);
  1496. } else {
  1497. v4l2_warn(&dev->v4l2_dev, "Unsupported firmware version: "
  1498. "%u.%u.%u\n", major, minor, release);
  1499. }
  1500. return 0;
  1501. }
  1502. static void coda_fw_callback(const struct firmware *fw, void *context)
  1503. {
  1504. struct coda_dev *dev = context;
  1505. struct platform_device *pdev = dev->plat_dev;
  1506. int ret;
  1507. if (!fw) {
  1508. v4l2_err(&dev->v4l2_dev, "firmware request failed\n");
  1509. return;
  1510. }
  1511. /* allocate auxiliary per-device code buffer for the BIT processor */
  1512. dev->codebuf.size = fw->size;
  1513. dev->codebuf.vaddr = dma_alloc_coherent(&pdev->dev, fw->size,
  1514. &dev->codebuf.paddr,
  1515. GFP_KERNEL);
  1516. if (!dev->codebuf.vaddr) {
  1517. dev_err(&pdev->dev, "failed to allocate code buffer\n");
  1518. return;
  1519. }
  1520. /* Copy the whole firmware image to the code buffer */
  1521. memcpy(dev->codebuf.vaddr, fw->data, fw->size);
  1522. release_firmware(fw);
  1523. ret = coda_hw_init(dev);
  1524. if (ret) {
  1525. v4l2_err(&dev->v4l2_dev, "HW initialization failed\n");
  1526. return;
  1527. }
  1528. dev->vfd.fops = &coda_fops,
  1529. dev->vfd.ioctl_ops = &coda_ioctl_ops;
  1530. dev->vfd.release = video_device_release_empty,
  1531. dev->vfd.lock = &dev->dev_mutex;
  1532. dev->vfd.v4l2_dev = &dev->v4l2_dev;
  1533. dev->vfd.vfl_dir = VFL_DIR_M2M;
  1534. snprintf(dev->vfd.name, sizeof(dev->vfd.name), "%s", CODA_NAME);
  1535. video_set_drvdata(&dev->vfd, dev);
  1536. dev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
  1537. if (IS_ERR(dev->alloc_ctx)) {
  1538. v4l2_err(&dev->v4l2_dev, "Failed to alloc vb2 context\n");
  1539. return;
  1540. }
  1541. dev->m2m_dev = v4l2_m2m_init(&coda_m2m_ops);
  1542. if (IS_ERR(dev->m2m_dev)) {
  1543. v4l2_err(&dev->v4l2_dev, "Failed to init mem2mem device\n");
  1544. goto rel_ctx;
  1545. }
  1546. ret = video_register_device(&dev->vfd, VFL_TYPE_GRABBER, 0);
  1547. if (ret) {
  1548. v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
  1549. goto rel_m2m;
  1550. }
  1551. v4l2_info(&dev->v4l2_dev, "codec registered as /dev/video%d\n",
  1552. dev->vfd.num);
  1553. return;
  1554. rel_m2m:
  1555. v4l2_m2m_release(dev->m2m_dev);
  1556. rel_ctx:
  1557. vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
  1558. }
  1559. static int coda_firmware_request(struct coda_dev *dev)
  1560. {
  1561. char *fw = dev->devtype->firmware;
  1562. dev_dbg(&dev->plat_dev->dev, "requesting firmware '%s' for %s\n", fw,
  1563. coda_product_name(dev->devtype->product));
  1564. return request_firmware_nowait(THIS_MODULE, true,
  1565. fw, &dev->plat_dev->dev, GFP_KERNEL, dev, coda_fw_callback);
  1566. }
  1567. enum coda_platform {
  1568. CODA_IMX27,
  1569. CODA_IMX53,
  1570. };
  1571. static const struct coda_devtype coda_devdata[] = {
  1572. [CODA_IMX27] = {
  1573. .firmware = "v4l-codadx6-imx27.bin",
  1574. .product = CODA_DX6,
  1575. .formats = codadx6_formats,
  1576. .num_formats = ARRAY_SIZE(codadx6_formats),
  1577. },
  1578. [CODA_IMX53] = {
  1579. .firmware = "v4l-coda7541-imx53.bin",
  1580. .product = CODA_7541,
  1581. .formats = coda7_formats,
  1582. .num_formats = ARRAY_SIZE(coda7_formats),
  1583. },
  1584. };
  1585. static struct platform_device_id coda_platform_ids[] = {
  1586. { .name = "coda-imx27", .driver_data = CODA_IMX27 },
  1587. { .name = "coda-imx53", .driver_data = CODA_IMX53 },
  1588. { /* sentinel */ }
  1589. };
  1590. MODULE_DEVICE_TABLE(platform, coda_platform_ids);
  1591. #ifdef CONFIG_OF
  1592. static const struct of_device_id coda_dt_ids[] = {
  1593. { .compatible = "fsl,imx27-vpu", .data = &coda_platform_ids[CODA_IMX27] },
  1594. { .compatible = "fsl,imx53-vpu", .data = &coda_devdata[CODA_IMX53] },
  1595. { /* sentinel */ }
  1596. };
  1597. MODULE_DEVICE_TABLE(of, coda_dt_ids);
  1598. #endif
  1599. static int coda_probe(struct platform_device *pdev)
  1600. {
  1601. const struct of_device_id *of_id =
  1602. of_match_device(of_match_ptr(coda_dt_ids), &pdev->dev);
  1603. const struct platform_device_id *pdev_id;
  1604. struct coda_dev *dev;
  1605. struct resource *res;
  1606. int ret, irq;
  1607. dev = devm_kzalloc(&pdev->dev, sizeof *dev, GFP_KERNEL);
  1608. if (!dev) {
  1609. dev_err(&pdev->dev, "Not enough memory for %s\n",
  1610. CODA_NAME);
  1611. return -ENOMEM;
  1612. }
  1613. spin_lock_init(&dev->irqlock);
  1614. INIT_LIST_HEAD(&dev->instances);
  1615. INIT_DELAYED_WORK(&dev->timeout, coda_timeout);
  1616. init_completion(&dev->done);
  1617. complete(&dev->done);
  1618. dev->plat_dev = pdev;
  1619. dev->clk_per = devm_clk_get(&pdev->dev, "per");
  1620. if (IS_ERR(dev->clk_per)) {
  1621. dev_err(&pdev->dev, "Could not get per clock\n");
  1622. return PTR_ERR(dev->clk_per);
  1623. }
  1624. dev->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
  1625. if (IS_ERR(dev->clk_ahb)) {
  1626. dev_err(&pdev->dev, "Could not get ahb clock\n");
  1627. return PTR_ERR(dev->clk_ahb);
  1628. }
  1629. /* Get memory for physical registers */
  1630. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1631. if (res == NULL) {
  1632. dev_err(&pdev->dev, "failed to get memory region resource\n");
  1633. return -ENOENT;
  1634. }
  1635. if (devm_request_mem_region(&pdev->dev, res->start,
  1636. resource_size(res), CODA_NAME) == NULL) {
  1637. dev_err(&pdev->dev, "failed to request memory region\n");
  1638. return -ENOENT;
  1639. }
  1640. dev->regs_base = devm_ioremap(&pdev->dev, res->start,
  1641. resource_size(res));
  1642. if (!dev->regs_base) {
  1643. dev_err(&pdev->dev, "failed to ioremap address region\n");
  1644. return -ENOENT;
  1645. }
  1646. /* IRQ */
  1647. irq = platform_get_irq(pdev, 0);
  1648. if (irq < 0) {
  1649. dev_err(&pdev->dev, "failed to get irq resource\n");
  1650. return -ENOENT;
  1651. }
  1652. if (devm_request_irq(&pdev->dev, irq, coda_irq_handler,
  1653. 0, CODA_NAME, dev) < 0) {
  1654. dev_err(&pdev->dev, "failed to request irq\n");
  1655. return -ENOENT;
  1656. }
  1657. ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
  1658. if (ret)
  1659. return ret;
  1660. mutex_init(&dev->dev_mutex);
  1661. pdev_id = of_id ? of_id->data : platform_get_device_id(pdev);
  1662. if (of_id) {
  1663. dev->devtype = of_id->data;
  1664. } else if (pdev_id) {
  1665. dev->devtype = &coda_devdata[pdev_id->driver_data];
  1666. } else {
  1667. v4l2_device_unregister(&dev->v4l2_dev);
  1668. return -EINVAL;
  1669. }
  1670. /* allocate auxiliary per-device buffers for the BIT processor */
  1671. switch (dev->devtype->product) {
  1672. case CODA_DX6:
  1673. dev->workbuf.size = CODADX6_WORK_BUF_SIZE;
  1674. break;
  1675. default:
  1676. dev->workbuf.size = CODA7_WORK_BUF_SIZE;
  1677. }
  1678. dev->workbuf.vaddr = dma_alloc_coherent(&pdev->dev, dev->workbuf.size,
  1679. &dev->workbuf.paddr,
  1680. GFP_KERNEL);
  1681. if (!dev->workbuf.vaddr) {
  1682. dev_err(&pdev->dev, "failed to allocate work buffer\n");
  1683. v4l2_device_unregister(&dev->v4l2_dev);
  1684. return -ENOMEM;
  1685. }
  1686. if (dev->devtype->product == CODA_DX6) {
  1687. dev->iram_paddr = 0xffff4c00;
  1688. } else {
  1689. void __iomem *iram_vaddr;
  1690. iram_vaddr = iram_alloc(CODA7_IRAM_SIZE,
  1691. &dev->iram_paddr);
  1692. if (!iram_vaddr) {
  1693. dev_err(&pdev->dev, "unable to alloc iram\n");
  1694. return -ENOMEM;
  1695. }
  1696. }
  1697. platform_set_drvdata(pdev, dev);
  1698. return coda_firmware_request(dev);
  1699. }
  1700. static int coda_remove(struct platform_device *pdev)
  1701. {
  1702. struct coda_dev *dev = platform_get_drvdata(pdev);
  1703. video_unregister_device(&dev->vfd);
  1704. if (dev->m2m_dev)
  1705. v4l2_m2m_release(dev->m2m_dev);
  1706. if (dev->alloc_ctx)
  1707. vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
  1708. v4l2_device_unregister(&dev->v4l2_dev);
  1709. if (dev->iram_paddr)
  1710. iram_free(dev->iram_paddr, CODA7_IRAM_SIZE);
  1711. if (dev->codebuf.vaddr)
  1712. dma_free_coherent(&pdev->dev, dev->codebuf.size,
  1713. &dev->codebuf.vaddr, dev->codebuf.paddr);
  1714. if (dev->workbuf.vaddr)
  1715. dma_free_coherent(&pdev->dev, dev->workbuf.size, &dev->workbuf.vaddr,
  1716. dev->workbuf.paddr);
  1717. return 0;
  1718. }
  1719. static struct platform_driver coda_driver = {
  1720. .probe = coda_probe,
  1721. .remove = coda_remove,
  1722. .driver = {
  1723. .name = CODA_NAME,
  1724. .owner = THIS_MODULE,
  1725. .of_match_table = of_match_ptr(coda_dt_ids),
  1726. },
  1727. .id_table = coda_platform_ids,
  1728. };
  1729. module_platform_driver(coda_driver);
  1730. MODULE_LICENSE("GPL");
  1731. MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
  1732. MODULE_DESCRIPTION("Coda multi-standard codec V4L2 driver");