cx23885-dvb.c 38 KB

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  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/module.h>
  22. #include <linux/init.h>
  23. #include <linux/device.h>
  24. #include <linux/fs.h>
  25. #include <linux/kthread.h>
  26. #include <linux/file.h>
  27. #include <linux/suspend.h>
  28. #include "cx23885.h"
  29. #include <media/v4l2-common.h>
  30. #include "dvb_ca_en50221.h"
  31. #include "s5h1409.h"
  32. #include "s5h1411.h"
  33. #include "mt2131.h"
  34. #include "tda8290.h"
  35. #include "tda18271.h"
  36. #include "lgdt330x.h"
  37. #include "xc4000.h"
  38. #include "xc5000.h"
  39. #include "max2165.h"
  40. #include "tda10048.h"
  41. #include "tuner-xc2028.h"
  42. #include "tuner-simple.h"
  43. #include "dib7000p.h"
  44. #include "dibx000_common.h"
  45. #include "zl10353.h"
  46. #include "stv0900.h"
  47. #include "stv0900_reg.h"
  48. #include "stv6110.h"
  49. #include "lnbh24.h"
  50. #include "cx24116.h"
  51. #include "cimax2.h"
  52. #include "lgs8gxx.h"
  53. #include "netup-eeprom.h"
  54. #include "netup-init.h"
  55. #include "lgdt3305.h"
  56. #include "atbm8830.h"
  57. #include "ds3000.h"
  58. #include "cx23885-f300.h"
  59. #include "altera-ci.h"
  60. #include "stv0367.h"
  61. #include "drxk.h"
  62. #include "mt2063.h"
  63. #include "stv090x.h"
  64. #include "stb6100.h"
  65. #include "stb6100_cfg.h"
  66. static unsigned int debug;
  67. #define dprintk(level, fmt, arg...)\
  68. do { if (debug >= level)\
  69. printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
  70. } while (0)
  71. /* ------------------------------------------------------------------ */
  72. static unsigned int alt_tuner;
  73. module_param(alt_tuner, int, 0644);
  74. MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
  75. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  76. /* ------------------------------------------------------------------ */
  77. static int dvb_buf_setup(struct videobuf_queue *q,
  78. unsigned int *count, unsigned int *size)
  79. {
  80. struct cx23885_tsport *port = q->priv_data;
  81. port->ts_packet_size = 188 * 4;
  82. port->ts_packet_count = 32;
  83. *size = port->ts_packet_size * port->ts_packet_count;
  84. *count = 32;
  85. return 0;
  86. }
  87. static int dvb_buf_prepare(struct videobuf_queue *q,
  88. struct videobuf_buffer *vb, enum v4l2_field field)
  89. {
  90. struct cx23885_tsport *port = q->priv_data;
  91. return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
  92. }
  93. static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
  94. {
  95. struct cx23885_tsport *port = q->priv_data;
  96. cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
  97. }
  98. static void dvb_buf_release(struct videobuf_queue *q,
  99. struct videobuf_buffer *vb)
  100. {
  101. cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
  102. }
  103. static int cx23885_dvb_set_frontend(struct dvb_frontend *fe);
  104. static void cx23885_dvb_gate_ctrl(struct cx23885_tsport *port, int open)
  105. {
  106. struct videobuf_dvb_frontends *f;
  107. struct videobuf_dvb_frontend *fe;
  108. f = &port->frontends;
  109. if (f->gate <= 1) /* undefined or fe0 */
  110. fe = videobuf_dvb_get_frontend(f, 1);
  111. else
  112. fe = videobuf_dvb_get_frontend(f, f->gate);
  113. if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl)
  114. fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open);
  115. /*
  116. * FIXME: Improve this path to avoid calling the
  117. * cx23885_dvb_set_frontend() every time it passes here.
  118. */
  119. cx23885_dvb_set_frontend(fe->dvb.frontend);
  120. }
  121. static struct videobuf_queue_ops dvb_qops = {
  122. .buf_setup = dvb_buf_setup,
  123. .buf_prepare = dvb_buf_prepare,
  124. .buf_queue = dvb_buf_queue,
  125. .buf_release = dvb_buf_release,
  126. };
  127. static struct s5h1409_config hauppauge_generic_config = {
  128. .demod_address = 0x32 >> 1,
  129. .output_mode = S5H1409_SERIAL_OUTPUT,
  130. .gpio = S5H1409_GPIO_ON,
  131. .qam_if = 44000,
  132. .inversion = S5H1409_INVERSION_OFF,
  133. .status_mode = S5H1409_DEMODLOCKING,
  134. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  135. };
  136. static struct tda10048_config hauppauge_hvr1200_config = {
  137. .demod_address = 0x10 >> 1,
  138. .output_mode = TDA10048_SERIAL_OUTPUT,
  139. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  140. .inversion = TDA10048_INVERSION_ON,
  141. .dtv6_if_freq_khz = TDA10048_IF_3300,
  142. .dtv7_if_freq_khz = TDA10048_IF_3800,
  143. .dtv8_if_freq_khz = TDA10048_IF_4300,
  144. .clk_freq_khz = TDA10048_CLK_16000,
  145. };
  146. static struct tda10048_config hauppauge_hvr1210_config = {
  147. .demod_address = 0x10 >> 1,
  148. .output_mode = TDA10048_SERIAL_OUTPUT,
  149. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  150. .inversion = TDA10048_INVERSION_ON,
  151. .dtv6_if_freq_khz = TDA10048_IF_3300,
  152. .dtv7_if_freq_khz = TDA10048_IF_3500,
  153. .dtv8_if_freq_khz = TDA10048_IF_4000,
  154. .clk_freq_khz = TDA10048_CLK_16000,
  155. };
  156. static struct s5h1409_config hauppauge_ezqam_config = {
  157. .demod_address = 0x32 >> 1,
  158. .output_mode = S5H1409_SERIAL_OUTPUT,
  159. .gpio = S5H1409_GPIO_OFF,
  160. .qam_if = 4000,
  161. .inversion = S5H1409_INVERSION_ON,
  162. .status_mode = S5H1409_DEMODLOCKING,
  163. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  164. };
  165. static struct s5h1409_config hauppauge_hvr1800lp_config = {
  166. .demod_address = 0x32 >> 1,
  167. .output_mode = S5H1409_SERIAL_OUTPUT,
  168. .gpio = S5H1409_GPIO_OFF,
  169. .qam_if = 44000,
  170. .inversion = S5H1409_INVERSION_OFF,
  171. .status_mode = S5H1409_DEMODLOCKING,
  172. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  173. };
  174. static struct s5h1409_config hauppauge_hvr1500_config = {
  175. .demod_address = 0x32 >> 1,
  176. .output_mode = S5H1409_SERIAL_OUTPUT,
  177. .gpio = S5H1409_GPIO_OFF,
  178. .inversion = S5H1409_INVERSION_OFF,
  179. .status_mode = S5H1409_DEMODLOCKING,
  180. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  181. };
  182. static struct mt2131_config hauppauge_generic_tunerconfig = {
  183. 0x61
  184. };
  185. static struct lgdt330x_config fusionhdtv_5_express = {
  186. .demod_address = 0x0e,
  187. .demod_chip = LGDT3303,
  188. .serial_mpeg = 0x40,
  189. };
  190. static struct s5h1409_config hauppauge_hvr1500q_config = {
  191. .demod_address = 0x32 >> 1,
  192. .output_mode = S5H1409_SERIAL_OUTPUT,
  193. .gpio = S5H1409_GPIO_ON,
  194. .qam_if = 44000,
  195. .inversion = S5H1409_INVERSION_OFF,
  196. .status_mode = S5H1409_DEMODLOCKING,
  197. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  198. };
  199. static struct s5h1409_config dvico_s5h1409_config = {
  200. .demod_address = 0x32 >> 1,
  201. .output_mode = S5H1409_SERIAL_OUTPUT,
  202. .gpio = S5H1409_GPIO_ON,
  203. .qam_if = 44000,
  204. .inversion = S5H1409_INVERSION_OFF,
  205. .status_mode = S5H1409_DEMODLOCKING,
  206. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  207. };
  208. static struct s5h1411_config dvico_s5h1411_config = {
  209. .output_mode = S5H1411_SERIAL_OUTPUT,
  210. .gpio = S5H1411_GPIO_ON,
  211. .qam_if = S5H1411_IF_44000,
  212. .vsb_if = S5H1411_IF_44000,
  213. .inversion = S5H1411_INVERSION_OFF,
  214. .status_mode = S5H1411_DEMODLOCKING,
  215. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  216. };
  217. static struct s5h1411_config hcw_s5h1411_config = {
  218. .output_mode = S5H1411_SERIAL_OUTPUT,
  219. .gpio = S5H1411_GPIO_OFF,
  220. .vsb_if = S5H1411_IF_44000,
  221. .qam_if = S5H1411_IF_4000,
  222. .inversion = S5H1411_INVERSION_ON,
  223. .status_mode = S5H1411_DEMODLOCKING,
  224. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  225. };
  226. static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
  227. .i2c_address = 0x61,
  228. .if_khz = 5380,
  229. };
  230. static struct xc5000_config dvico_xc5000_tunerconfig = {
  231. .i2c_address = 0x64,
  232. .if_khz = 5380,
  233. };
  234. static struct tda829x_config tda829x_no_probe = {
  235. .probe_tuner = TDA829X_DONT_PROBE,
  236. };
  237. static struct tda18271_std_map hauppauge_tda18271_std_map = {
  238. .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
  239. .if_lvl = 6, .rfagc_top = 0x37 },
  240. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
  241. .if_lvl = 6, .rfagc_top = 0x37 },
  242. };
  243. static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
  244. .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
  245. .if_lvl = 1, .rfagc_top = 0x37, },
  246. .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
  247. .if_lvl = 1, .rfagc_top = 0x37, },
  248. .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
  249. .if_lvl = 1, .rfagc_top = 0x37, },
  250. };
  251. static struct tda18271_config hauppauge_tda18271_config = {
  252. .std_map = &hauppauge_tda18271_std_map,
  253. .gate = TDA18271_GATE_ANALOG,
  254. .output_opt = TDA18271_OUTPUT_LT_OFF,
  255. };
  256. static struct tda18271_config hauppauge_hvr1200_tuner_config = {
  257. .std_map = &hauppauge_hvr1200_tda18271_std_map,
  258. .gate = TDA18271_GATE_ANALOG,
  259. .output_opt = TDA18271_OUTPUT_LT_OFF,
  260. };
  261. static struct tda18271_config hauppauge_hvr1210_tuner_config = {
  262. .gate = TDA18271_GATE_DIGITAL,
  263. .output_opt = TDA18271_OUTPUT_LT_OFF,
  264. };
  265. static struct tda18271_std_map hauppauge_hvr127x_std_map = {
  266. .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
  267. .if_lvl = 1, .rfagc_top = 0x58 },
  268. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
  269. .if_lvl = 1, .rfagc_top = 0x58 },
  270. };
  271. static struct tda18271_config hauppauge_hvr127x_config = {
  272. .std_map = &hauppauge_hvr127x_std_map,
  273. .output_opt = TDA18271_OUTPUT_LT_OFF,
  274. };
  275. static struct lgdt3305_config hauppauge_lgdt3305_config = {
  276. .i2c_addr = 0x0e,
  277. .mpeg_mode = LGDT3305_MPEG_SERIAL,
  278. .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
  279. .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
  280. .deny_i2c_rptr = 1,
  281. .spectral_inversion = 1,
  282. .qam_if_khz = 4000,
  283. .vsb_if_khz = 3250,
  284. };
  285. static struct dibx000_agc_config xc3028_agc_config = {
  286. BAND_VHF | BAND_UHF, /* band_caps */
  287. /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
  288. * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
  289. * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
  290. * P_agc_nb_est=2, P_agc_write=0
  291. */
  292. (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
  293. (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
  294. 712, /* inv_gain */
  295. 21, /* time_stabiliz */
  296. 0, /* alpha_level */
  297. 118, /* thlock */
  298. 0, /* wbd_inv */
  299. 2867, /* wbd_ref */
  300. 0, /* wbd_sel */
  301. 2, /* wbd_alpha */
  302. 0, /* agc1_max */
  303. 0, /* agc1_min */
  304. 39718, /* agc2_max */
  305. 9930, /* agc2_min */
  306. 0, /* agc1_pt1 */
  307. 0, /* agc1_pt2 */
  308. 0, /* agc1_pt3 */
  309. 0, /* agc1_slope1 */
  310. 0, /* agc1_slope2 */
  311. 0, /* agc2_pt1 */
  312. 128, /* agc2_pt2 */
  313. 29, /* agc2_slope1 */
  314. 29, /* agc2_slope2 */
  315. 17, /* alpha_mant */
  316. 27, /* alpha_exp */
  317. 23, /* beta_mant */
  318. 51, /* beta_exp */
  319. 1, /* perform_agc_softsplit */
  320. };
  321. /* PLL Configuration for COFDM BW_MHz = 8.000000
  322. * With external clock = 30.000000 */
  323. static struct dibx000_bandwidth_config xc3028_bw_config = {
  324. 60000, /* internal */
  325. 30000, /* sampling */
  326. 1, /* pll_cfg: prediv */
  327. 8, /* pll_cfg: ratio */
  328. 3, /* pll_cfg: range */
  329. 1, /* pll_cfg: reset */
  330. 0, /* pll_cfg: bypass */
  331. 0, /* misc: refdiv */
  332. 0, /* misc: bypclk_div */
  333. 1, /* misc: IO_CLK_en_core */
  334. 1, /* misc: ADClkSrc */
  335. 0, /* misc: modulo */
  336. (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
  337. (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
  338. 20452225, /* timf */
  339. 30000000 /* xtal_hz */
  340. };
  341. static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
  342. .output_mpeg2_in_188_bytes = 1,
  343. .hostbus_diversity = 1,
  344. .tuner_is_baseband = 0,
  345. .update_lna = NULL,
  346. .agc_config_count = 1,
  347. .agc = &xc3028_agc_config,
  348. .bw = &xc3028_bw_config,
  349. .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
  350. .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
  351. .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
  352. .pwm_freq_div = 0,
  353. .agc_control = NULL,
  354. .spur_protect = 0,
  355. .output_mode = OUTMODE_MPEG2_SERIAL,
  356. };
  357. static struct zl10353_config dvico_fusionhdtv_xc3028 = {
  358. .demod_address = 0x0f,
  359. .if2 = 45600,
  360. .no_tuner = 1,
  361. .disable_i2c_gate_ctrl = 1,
  362. };
  363. static struct stv0900_reg stv0900_ts_regs[] = {
  364. { R0900_TSGENERAL, 0x00 },
  365. { R0900_P1_TSSPEED, 0x40 },
  366. { R0900_P2_TSSPEED, 0x40 },
  367. { R0900_P1_TSCFGM, 0xc0 },
  368. { R0900_P2_TSCFGM, 0xc0 },
  369. { R0900_P1_TSCFGH, 0xe0 },
  370. { R0900_P2_TSCFGH, 0xe0 },
  371. { R0900_P1_TSCFGL, 0x20 },
  372. { R0900_P2_TSCFGL, 0x20 },
  373. { 0xffff, 0xff }, /* terminate */
  374. };
  375. static struct stv0900_config netup_stv0900_config = {
  376. .demod_address = 0x68,
  377. .demod_mode = 1, /* dual */
  378. .xtal = 8000000,
  379. .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
  380. .diseqc_mode = 2,/* 2/3 PWM */
  381. .ts_config_regs = stv0900_ts_regs,
  382. .tun1_maddress = 0,/* 0x60 */
  383. .tun2_maddress = 3,/* 0x63 */
  384. .tun1_adc = 1,/* 1 Vpp */
  385. .tun2_adc = 1,/* 1 Vpp */
  386. };
  387. static struct stv6110_config netup_stv6110_tunerconfig_a = {
  388. .i2c_address = 0x60,
  389. .mclk = 16000000,
  390. .clk_div = 1,
  391. .gain = 8, /* +16 dB - maximum gain */
  392. };
  393. static struct stv6110_config netup_stv6110_tunerconfig_b = {
  394. .i2c_address = 0x63,
  395. .mclk = 16000000,
  396. .clk_div = 1,
  397. .gain = 8, /* +16 dB - maximum gain */
  398. };
  399. static struct cx24116_config tbs_cx24116_config = {
  400. .demod_address = 0x55,
  401. };
  402. static struct ds3000_config tevii_ds3000_config = {
  403. .demod_address = 0x68,
  404. };
  405. static struct cx24116_config dvbworld_cx24116_config = {
  406. .demod_address = 0x05,
  407. };
  408. static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
  409. .prod = LGS8GXX_PROD_LGS8GL5,
  410. .demod_address = 0x19,
  411. .serial_ts = 0,
  412. .ts_clk_pol = 1,
  413. .ts_clk_gated = 1,
  414. .if_clk_freq = 30400, /* 30.4 MHz */
  415. .if_freq = 5380, /* 5.38 MHz */
  416. .if_neg_center = 1,
  417. .ext_adc = 0,
  418. .adc_signed = 0,
  419. .if_neg_edge = 0,
  420. };
  421. static struct xc5000_config mygica_x8506_xc5000_config = {
  422. .i2c_address = 0x61,
  423. .if_khz = 5380,
  424. };
  425. static struct stv090x_config prof_8000_stv090x_config = {
  426. .device = STV0903,
  427. .demod_mode = STV090x_SINGLE,
  428. .clk_mode = STV090x_CLK_EXT,
  429. .xtal = 27000000,
  430. .address = 0x6A,
  431. .ts1_mode = STV090x_TSMODE_PARALLEL_PUNCTURED,
  432. .repeater_level = STV090x_RPTLEVEL_64,
  433. .adc1_range = STV090x_ADC_2Vpp,
  434. .diseqc_envelope_mode = false,
  435. .tuner_get_frequency = stb6100_get_frequency,
  436. .tuner_set_frequency = stb6100_set_frequency,
  437. .tuner_set_bandwidth = stb6100_set_bandwidth,
  438. .tuner_get_bandwidth = stb6100_get_bandwidth,
  439. };
  440. static struct stb6100_config prof_8000_stb6100_config = {
  441. .tuner_address = 0x60,
  442. .refclock = 27000000,
  443. };
  444. static int p8000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
  445. {
  446. struct cx23885_tsport *port = fe->dvb->priv;
  447. struct cx23885_dev *dev = port->dev;
  448. if (voltage == SEC_VOLTAGE_18)
  449. cx_write(MC417_RWD, 0x00001e00);
  450. else if (voltage == SEC_VOLTAGE_13)
  451. cx_write(MC417_RWD, 0x00001a00);
  452. else
  453. cx_write(MC417_RWD, 0x00001800);
  454. return 0;
  455. }
  456. static int cx23885_dvb_set_frontend(struct dvb_frontend *fe)
  457. {
  458. struct dtv_frontend_properties *p = &fe->dtv_property_cache;
  459. struct cx23885_tsport *port = fe->dvb->priv;
  460. struct cx23885_dev *dev = port->dev;
  461. switch (dev->board) {
  462. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  463. switch (p->modulation) {
  464. case VSB_8:
  465. cx23885_gpio_clear(dev, GPIO_5);
  466. break;
  467. case QAM_64:
  468. case QAM_256:
  469. default:
  470. cx23885_gpio_set(dev, GPIO_5);
  471. break;
  472. }
  473. break;
  474. case CX23885_BOARD_MYGICA_X8506:
  475. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  476. /* Select Digital TV */
  477. cx23885_gpio_set(dev, GPIO_0);
  478. break;
  479. }
  480. return 0;
  481. }
  482. static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
  483. .prod = LGS8GXX_PROD_LGS8G75,
  484. .demod_address = 0x19,
  485. .serial_ts = 0,
  486. .ts_clk_pol = 1,
  487. .ts_clk_gated = 1,
  488. .if_clk_freq = 30400, /* 30.4 MHz */
  489. .if_freq = 6500, /* 6.50 MHz */
  490. .if_neg_center = 1,
  491. .ext_adc = 0,
  492. .adc_signed = 1,
  493. .adc_vpp = 2, /* 1.6 Vpp */
  494. .if_neg_edge = 1,
  495. };
  496. static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
  497. .i2c_address = 0x61,
  498. .if_khz = 6500,
  499. };
  500. static struct atbm8830_config mygica_x8558pro_atbm8830_cfg1 = {
  501. .prod = ATBM8830_PROD_8830,
  502. .demod_address = 0x44,
  503. .serial_ts = 0,
  504. .ts_sampling_edge = 1,
  505. .ts_clk_gated = 0,
  506. .osc_clk_freq = 30400, /* in kHz */
  507. .if_freq = 0, /* zero IF */
  508. .zif_swap_iq = 1,
  509. .agc_min = 0x2E,
  510. .agc_max = 0xFF,
  511. .agc_hold_loop = 0,
  512. };
  513. static struct max2165_config mygic_x8558pro_max2165_cfg1 = {
  514. .i2c_address = 0x60,
  515. .osc_clk = 20
  516. };
  517. static struct atbm8830_config mygica_x8558pro_atbm8830_cfg2 = {
  518. .prod = ATBM8830_PROD_8830,
  519. .demod_address = 0x44,
  520. .serial_ts = 1,
  521. .ts_sampling_edge = 1,
  522. .ts_clk_gated = 0,
  523. .osc_clk_freq = 30400, /* in kHz */
  524. .if_freq = 0, /* zero IF */
  525. .zif_swap_iq = 1,
  526. .agc_min = 0x2E,
  527. .agc_max = 0xFF,
  528. .agc_hold_loop = 0,
  529. };
  530. static struct max2165_config mygic_x8558pro_max2165_cfg2 = {
  531. .i2c_address = 0x60,
  532. .osc_clk = 20
  533. };
  534. static struct stv0367_config netup_stv0367_config[] = {
  535. {
  536. .demod_address = 0x1c,
  537. .xtal = 27000000,
  538. .if_khz = 4500,
  539. .if_iq_mode = 0,
  540. .ts_mode = 1,
  541. .clk_pol = 0,
  542. }, {
  543. .demod_address = 0x1d,
  544. .xtal = 27000000,
  545. .if_khz = 4500,
  546. .if_iq_mode = 0,
  547. .ts_mode = 1,
  548. .clk_pol = 0,
  549. },
  550. };
  551. static struct xc5000_config netup_xc5000_config[] = {
  552. {
  553. .i2c_address = 0x61,
  554. .if_khz = 4500,
  555. }, {
  556. .i2c_address = 0x64,
  557. .if_khz = 4500,
  558. },
  559. };
  560. static struct drxk_config terratec_drxk_config[] = {
  561. {
  562. .adr = 0x29,
  563. .no_i2c_bridge = 1,
  564. }, {
  565. .adr = 0x2a,
  566. .no_i2c_bridge = 1,
  567. },
  568. };
  569. static struct mt2063_config terratec_mt2063_config[] = {
  570. {
  571. .tuner_address = 0x60,
  572. }, {
  573. .tuner_address = 0x67,
  574. },
  575. };
  576. static int netup_altera_fpga_rw(void *device, int flag, int data, int read)
  577. {
  578. struct cx23885_dev *dev = (struct cx23885_dev *)device;
  579. unsigned long timeout = jiffies + msecs_to_jiffies(1);
  580. uint32_t mem = 0;
  581. mem = cx_read(MC417_RWD);
  582. if (read)
  583. cx_set(MC417_OEN, ALT_DATA);
  584. else {
  585. cx_clear(MC417_OEN, ALT_DATA);/* D0-D7 out */
  586. mem &= ~ALT_DATA;
  587. mem |= (data & ALT_DATA);
  588. }
  589. if (flag)
  590. mem |= ALT_AD_RG;
  591. else
  592. mem &= ~ALT_AD_RG;
  593. mem &= ~ALT_CS;
  594. if (read)
  595. mem = (mem & ~ALT_RD) | ALT_WR;
  596. else
  597. mem = (mem & ~ALT_WR) | ALT_RD;
  598. cx_write(MC417_RWD, mem); /* start RW cycle */
  599. for (;;) {
  600. mem = cx_read(MC417_RWD);
  601. if ((mem & ALT_RDY) == 0)
  602. break;
  603. if (time_after(jiffies, timeout))
  604. break;
  605. udelay(1);
  606. }
  607. cx_set(MC417_RWD, ALT_RD | ALT_WR | ALT_CS);
  608. if (read)
  609. return mem & ALT_DATA;
  610. return 0;
  611. };
  612. static int dvb_register(struct cx23885_tsport *port)
  613. {
  614. struct cx23885_dev *dev = port->dev;
  615. struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
  616. struct videobuf_dvb_frontend *fe0, *fe1 = NULL;
  617. int mfe_shared = 0; /* bus not shared by default */
  618. int ret;
  619. /* Get the first frontend */
  620. fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
  621. if (!fe0)
  622. return -EINVAL;
  623. /* init struct videobuf_dvb */
  624. fe0->dvb.name = dev->name;
  625. /* multi-frontend gate control is undefined or defaults to fe0 */
  626. port->frontends.gate = 0;
  627. /* Sets the gate control callback to be used by i2c command calls */
  628. port->gate_ctrl = cx23885_dvb_gate_ctrl;
  629. /* init frontend */
  630. switch (dev->board) {
  631. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  632. i2c_bus = &dev->i2c_bus[0];
  633. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  634. &hauppauge_generic_config,
  635. &i2c_bus->i2c_adap);
  636. if (fe0->dvb.frontend != NULL) {
  637. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  638. &i2c_bus->i2c_adap,
  639. &hauppauge_generic_tunerconfig, 0);
  640. }
  641. break;
  642. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  643. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  644. i2c_bus = &dev->i2c_bus[0];
  645. fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
  646. &hauppauge_lgdt3305_config,
  647. &i2c_bus->i2c_adap);
  648. if (fe0->dvb.frontend != NULL) {
  649. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  650. 0x60, &dev->i2c_bus[1].i2c_adap,
  651. &hauppauge_hvr127x_config);
  652. }
  653. break;
  654. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  655. case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
  656. i2c_bus = &dev->i2c_bus[0];
  657. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  658. &hcw_s5h1411_config,
  659. &i2c_bus->i2c_adap);
  660. if (fe0->dvb.frontend != NULL) {
  661. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  662. 0x60, &dev->i2c_bus[1].i2c_adap,
  663. &hauppauge_tda18271_config);
  664. }
  665. tda18271_attach(&dev->ts1.analog_fe,
  666. 0x60, &dev->i2c_bus[1].i2c_adap,
  667. &hauppauge_tda18271_config);
  668. break;
  669. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  670. i2c_bus = &dev->i2c_bus[0];
  671. switch (alt_tuner) {
  672. case 1:
  673. fe0->dvb.frontend =
  674. dvb_attach(s5h1409_attach,
  675. &hauppauge_ezqam_config,
  676. &i2c_bus->i2c_adap);
  677. if (fe0->dvb.frontend != NULL) {
  678. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  679. &dev->i2c_bus[1].i2c_adap, 0x42,
  680. &tda829x_no_probe);
  681. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  682. 0x60, &dev->i2c_bus[1].i2c_adap,
  683. &hauppauge_tda18271_config);
  684. }
  685. break;
  686. case 0:
  687. default:
  688. fe0->dvb.frontend =
  689. dvb_attach(s5h1409_attach,
  690. &hauppauge_generic_config,
  691. &i2c_bus->i2c_adap);
  692. if (fe0->dvb.frontend != NULL)
  693. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  694. &i2c_bus->i2c_adap,
  695. &hauppauge_generic_tunerconfig, 0);
  696. break;
  697. }
  698. break;
  699. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  700. i2c_bus = &dev->i2c_bus[0];
  701. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  702. &hauppauge_hvr1800lp_config,
  703. &i2c_bus->i2c_adap);
  704. if (fe0->dvb.frontend != NULL) {
  705. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  706. &i2c_bus->i2c_adap,
  707. &hauppauge_generic_tunerconfig, 0);
  708. }
  709. break;
  710. case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
  711. i2c_bus = &dev->i2c_bus[0];
  712. fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
  713. &fusionhdtv_5_express,
  714. &i2c_bus->i2c_adap);
  715. if (fe0->dvb.frontend != NULL) {
  716. dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  717. &i2c_bus->i2c_adap, 0x61,
  718. TUNER_LG_TDVS_H06XF);
  719. }
  720. break;
  721. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  722. i2c_bus = &dev->i2c_bus[1];
  723. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  724. &hauppauge_hvr1500q_config,
  725. &dev->i2c_bus[0].i2c_adap);
  726. if (fe0->dvb.frontend != NULL)
  727. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  728. &i2c_bus->i2c_adap,
  729. &hauppauge_hvr1500q_tunerconfig);
  730. break;
  731. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  732. i2c_bus = &dev->i2c_bus[1];
  733. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  734. &hauppauge_hvr1500_config,
  735. &dev->i2c_bus[0].i2c_adap);
  736. if (fe0->dvb.frontend != NULL) {
  737. struct dvb_frontend *fe;
  738. struct xc2028_config cfg = {
  739. .i2c_adap = &i2c_bus->i2c_adap,
  740. .i2c_addr = 0x61,
  741. };
  742. static struct xc2028_ctrl ctl = {
  743. .fname = XC2028_DEFAULT_FIRMWARE,
  744. .max_len = 64,
  745. .demod = XC3028_FE_OREN538,
  746. };
  747. fe = dvb_attach(xc2028_attach,
  748. fe0->dvb.frontend, &cfg);
  749. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  750. fe->ops.tuner_ops.set_config(fe, &ctl);
  751. }
  752. break;
  753. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  754. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  755. i2c_bus = &dev->i2c_bus[0];
  756. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  757. &hauppauge_hvr1200_config,
  758. &i2c_bus->i2c_adap);
  759. if (fe0->dvb.frontend != NULL) {
  760. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  761. &dev->i2c_bus[1].i2c_adap, 0x42,
  762. &tda829x_no_probe);
  763. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  764. 0x60, &dev->i2c_bus[1].i2c_adap,
  765. &hauppauge_hvr1200_tuner_config);
  766. }
  767. break;
  768. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  769. i2c_bus = &dev->i2c_bus[0];
  770. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  771. &hauppauge_hvr1210_config,
  772. &i2c_bus->i2c_adap);
  773. if (fe0->dvb.frontend != NULL) {
  774. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  775. 0x60, &dev->i2c_bus[1].i2c_adap,
  776. &hauppauge_hvr1210_tuner_config);
  777. }
  778. break;
  779. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  780. i2c_bus = &dev->i2c_bus[0];
  781. fe0->dvb.frontend = dvb_attach(dib7000p_attach,
  782. &i2c_bus->i2c_adap,
  783. 0x12, &hauppauge_hvr1400_dib7000_config);
  784. if (fe0->dvb.frontend != NULL) {
  785. struct dvb_frontend *fe;
  786. struct xc2028_config cfg = {
  787. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  788. .i2c_addr = 0x64,
  789. };
  790. static struct xc2028_ctrl ctl = {
  791. .fname = XC3028L_DEFAULT_FIRMWARE,
  792. .max_len = 64,
  793. .demod = XC3028_FE_DIBCOM52,
  794. /* This is true for all demods with
  795. v36 firmware? */
  796. .type = XC2028_D2633,
  797. };
  798. fe = dvb_attach(xc2028_attach,
  799. fe0->dvb.frontend, &cfg);
  800. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  801. fe->ops.tuner_ops.set_config(fe, &ctl);
  802. }
  803. break;
  804. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  805. i2c_bus = &dev->i2c_bus[port->nr - 1];
  806. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  807. &dvico_s5h1409_config,
  808. &i2c_bus->i2c_adap);
  809. if (fe0->dvb.frontend == NULL)
  810. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  811. &dvico_s5h1411_config,
  812. &i2c_bus->i2c_adap);
  813. if (fe0->dvb.frontend != NULL)
  814. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  815. &i2c_bus->i2c_adap,
  816. &dvico_xc5000_tunerconfig);
  817. break;
  818. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
  819. i2c_bus = &dev->i2c_bus[port->nr - 1];
  820. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  821. &dvico_fusionhdtv_xc3028,
  822. &i2c_bus->i2c_adap);
  823. if (fe0->dvb.frontend != NULL) {
  824. struct dvb_frontend *fe;
  825. struct xc2028_config cfg = {
  826. .i2c_adap = &i2c_bus->i2c_adap,
  827. .i2c_addr = 0x61,
  828. };
  829. static struct xc2028_ctrl ctl = {
  830. .fname = XC2028_DEFAULT_FIRMWARE,
  831. .max_len = 64,
  832. .demod = XC3028_FE_ZARLINK456,
  833. };
  834. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  835. &cfg);
  836. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  837. fe->ops.tuner_ops.set_config(fe, &ctl);
  838. }
  839. break;
  840. }
  841. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  842. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  843. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  844. i2c_bus = &dev->i2c_bus[0];
  845. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  846. &dvico_fusionhdtv_xc3028,
  847. &i2c_bus->i2c_adap);
  848. if (fe0->dvb.frontend != NULL) {
  849. struct dvb_frontend *fe;
  850. struct xc2028_config cfg = {
  851. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  852. .i2c_addr = 0x61,
  853. };
  854. static struct xc2028_ctrl ctl = {
  855. .fname = XC2028_DEFAULT_FIRMWARE,
  856. .max_len = 64,
  857. .demod = XC3028_FE_ZARLINK456,
  858. };
  859. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  860. &cfg);
  861. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  862. fe->ops.tuner_ops.set_config(fe, &ctl);
  863. }
  864. break;
  865. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
  866. i2c_bus = &dev->i2c_bus[0];
  867. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  868. &dvico_fusionhdtv_xc3028,
  869. &i2c_bus->i2c_adap);
  870. if (fe0->dvb.frontend != NULL) {
  871. struct dvb_frontend *fe;
  872. struct xc4000_config cfg = {
  873. .i2c_address = 0x61,
  874. .default_pm = 0,
  875. .dvb_amplitude = 134,
  876. .set_smoothedcvbs = 1,
  877. .if_khz = 4560
  878. };
  879. fe = dvb_attach(xc4000_attach, fe0->dvb.frontend,
  880. &dev->i2c_bus[1].i2c_adap, &cfg);
  881. if (!fe) {
  882. printk(KERN_ERR "%s/2: xc4000 attach failed\n",
  883. dev->name);
  884. goto frontend_detach;
  885. }
  886. }
  887. break;
  888. case CX23885_BOARD_TBS_6920:
  889. i2c_bus = &dev->i2c_bus[1];
  890. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  891. &tbs_cx24116_config,
  892. &i2c_bus->i2c_adap);
  893. if (fe0->dvb.frontend != NULL)
  894. fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
  895. break;
  896. case CX23885_BOARD_TEVII_S470:
  897. i2c_bus = &dev->i2c_bus[1];
  898. fe0->dvb.frontend = dvb_attach(ds3000_attach,
  899. &tevii_ds3000_config,
  900. &i2c_bus->i2c_adap);
  901. if (fe0->dvb.frontend != NULL)
  902. fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
  903. break;
  904. case CX23885_BOARD_DVBWORLD_2005:
  905. i2c_bus = &dev->i2c_bus[1];
  906. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  907. &dvbworld_cx24116_config,
  908. &i2c_bus->i2c_adap);
  909. break;
  910. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  911. i2c_bus = &dev->i2c_bus[0];
  912. switch (port->nr) {
  913. /* port B */
  914. case 1:
  915. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  916. &netup_stv0900_config,
  917. &i2c_bus->i2c_adap, 0);
  918. if (fe0->dvb.frontend != NULL) {
  919. if (dvb_attach(stv6110_attach,
  920. fe0->dvb.frontend,
  921. &netup_stv6110_tunerconfig_a,
  922. &i2c_bus->i2c_adap)) {
  923. if (!dvb_attach(lnbh24_attach,
  924. fe0->dvb.frontend,
  925. &i2c_bus->i2c_adap,
  926. LNBH24_PCL | LNBH24_TTX,
  927. LNBH24_TEN, 0x09))
  928. printk(KERN_ERR
  929. "No LNBH24 found!\n");
  930. }
  931. }
  932. break;
  933. /* port C */
  934. case 2:
  935. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  936. &netup_stv0900_config,
  937. &i2c_bus->i2c_adap, 1);
  938. if (fe0->dvb.frontend != NULL) {
  939. if (dvb_attach(stv6110_attach,
  940. fe0->dvb.frontend,
  941. &netup_stv6110_tunerconfig_b,
  942. &i2c_bus->i2c_adap)) {
  943. if (!dvb_attach(lnbh24_attach,
  944. fe0->dvb.frontend,
  945. &i2c_bus->i2c_adap,
  946. LNBH24_PCL | LNBH24_TTX,
  947. LNBH24_TEN, 0x0a))
  948. printk(KERN_ERR
  949. "No LNBH24 found!\n");
  950. }
  951. }
  952. break;
  953. }
  954. break;
  955. case CX23885_BOARD_MYGICA_X8506:
  956. i2c_bus = &dev->i2c_bus[0];
  957. i2c_bus2 = &dev->i2c_bus[1];
  958. fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
  959. &mygica_x8506_lgs8gl5_config,
  960. &i2c_bus->i2c_adap);
  961. if (fe0->dvb.frontend != NULL) {
  962. dvb_attach(xc5000_attach,
  963. fe0->dvb.frontend,
  964. &i2c_bus2->i2c_adap,
  965. &mygica_x8506_xc5000_config);
  966. }
  967. break;
  968. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  969. i2c_bus = &dev->i2c_bus[0];
  970. i2c_bus2 = &dev->i2c_bus[1];
  971. fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
  972. &magicpro_prohdtve2_lgs8g75_config,
  973. &i2c_bus->i2c_adap);
  974. if (fe0->dvb.frontend != NULL) {
  975. dvb_attach(xc5000_attach,
  976. fe0->dvb.frontend,
  977. &i2c_bus2->i2c_adap,
  978. &magicpro_prohdtve2_xc5000_config);
  979. }
  980. break;
  981. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  982. i2c_bus = &dev->i2c_bus[0];
  983. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  984. &hcw_s5h1411_config,
  985. &i2c_bus->i2c_adap);
  986. if (fe0->dvb.frontend != NULL)
  987. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  988. 0x60, &dev->i2c_bus[0].i2c_adap,
  989. &hauppauge_tda18271_config);
  990. tda18271_attach(&dev->ts1.analog_fe,
  991. 0x60, &dev->i2c_bus[1].i2c_adap,
  992. &hauppauge_tda18271_config);
  993. break;
  994. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  995. i2c_bus = &dev->i2c_bus[0];
  996. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  997. &hcw_s5h1411_config,
  998. &i2c_bus->i2c_adap);
  999. if (fe0->dvb.frontend != NULL)
  1000. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  1001. 0x60, &dev->i2c_bus[0].i2c_adap,
  1002. &hauppauge_tda18271_config);
  1003. break;
  1004. case CX23885_BOARD_MYGICA_X8558PRO:
  1005. switch (port->nr) {
  1006. /* port B */
  1007. case 1:
  1008. i2c_bus = &dev->i2c_bus[0];
  1009. fe0->dvb.frontend = dvb_attach(atbm8830_attach,
  1010. &mygica_x8558pro_atbm8830_cfg1,
  1011. &i2c_bus->i2c_adap);
  1012. if (fe0->dvb.frontend != NULL) {
  1013. dvb_attach(max2165_attach,
  1014. fe0->dvb.frontend,
  1015. &i2c_bus->i2c_adap,
  1016. &mygic_x8558pro_max2165_cfg1);
  1017. }
  1018. break;
  1019. /* port C */
  1020. case 2:
  1021. i2c_bus = &dev->i2c_bus[1];
  1022. fe0->dvb.frontend = dvb_attach(atbm8830_attach,
  1023. &mygica_x8558pro_atbm8830_cfg2,
  1024. &i2c_bus->i2c_adap);
  1025. if (fe0->dvb.frontend != NULL) {
  1026. dvb_attach(max2165_attach,
  1027. fe0->dvb.frontend,
  1028. &i2c_bus->i2c_adap,
  1029. &mygic_x8558pro_max2165_cfg2);
  1030. }
  1031. break;
  1032. }
  1033. break;
  1034. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1035. i2c_bus = &dev->i2c_bus[0];
  1036. mfe_shared = 1;/* MFE */
  1037. port->frontends.gate = 0;/* not clear for me yet */
  1038. /* ports B, C */
  1039. /* MFE frontend 1 DVB-T */
  1040. fe0->dvb.frontend = dvb_attach(stv0367ter_attach,
  1041. &netup_stv0367_config[port->nr - 1],
  1042. &i2c_bus->i2c_adap);
  1043. if (fe0->dvb.frontend != NULL) {
  1044. if (NULL == dvb_attach(xc5000_attach,
  1045. fe0->dvb.frontend,
  1046. &i2c_bus->i2c_adap,
  1047. &netup_xc5000_config[port->nr - 1]))
  1048. goto frontend_detach;
  1049. /* load xc5000 firmware */
  1050. fe0->dvb.frontend->ops.tuner_ops.init(fe0->dvb.frontend);
  1051. }
  1052. /* MFE frontend 2 */
  1053. fe1 = videobuf_dvb_get_frontend(&port->frontends, 2);
  1054. if (fe1 == NULL)
  1055. goto frontend_detach;
  1056. /* DVB-C init */
  1057. fe1->dvb.frontend = dvb_attach(stv0367cab_attach,
  1058. &netup_stv0367_config[port->nr - 1],
  1059. &i2c_bus->i2c_adap);
  1060. if (fe1->dvb.frontend != NULL) {
  1061. fe1->dvb.frontend->id = 1;
  1062. if (NULL == dvb_attach(xc5000_attach,
  1063. fe1->dvb.frontend,
  1064. &i2c_bus->i2c_adap,
  1065. &netup_xc5000_config[port->nr - 1]))
  1066. goto frontend_detach;
  1067. }
  1068. break;
  1069. case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
  1070. i2c_bus = &dev->i2c_bus[0];
  1071. i2c_bus2 = &dev->i2c_bus[1];
  1072. switch (port->nr) {
  1073. /* port b */
  1074. case 1:
  1075. fe0->dvb.frontend = dvb_attach(drxk_attach,
  1076. &terratec_drxk_config[0],
  1077. &i2c_bus->i2c_adap);
  1078. if (fe0->dvb.frontend != NULL) {
  1079. if (!dvb_attach(mt2063_attach,
  1080. fe0->dvb.frontend,
  1081. &terratec_mt2063_config[0],
  1082. &i2c_bus2->i2c_adap))
  1083. goto frontend_detach;
  1084. }
  1085. break;
  1086. /* port c */
  1087. case 2:
  1088. fe0->dvb.frontend = dvb_attach(drxk_attach,
  1089. &terratec_drxk_config[1],
  1090. &i2c_bus->i2c_adap);
  1091. if (fe0->dvb.frontend != NULL) {
  1092. if (!dvb_attach(mt2063_attach,
  1093. fe0->dvb.frontend,
  1094. &terratec_mt2063_config[1],
  1095. &i2c_bus2->i2c_adap))
  1096. goto frontend_detach;
  1097. }
  1098. break;
  1099. }
  1100. break;
  1101. case CX23885_BOARD_TEVII_S471:
  1102. i2c_bus = &dev->i2c_bus[1];
  1103. fe0->dvb.frontend = dvb_attach(ds3000_attach,
  1104. &tevii_ds3000_config,
  1105. &i2c_bus->i2c_adap);
  1106. break;
  1107. case CX23885_BOARD_PROF_8000:
  1108. i2c_bus = &dev->i2c_bus[0];
  1109. fe0->dvb.frontend = dvb_attach(stv090x_attach,
  1110. &prof_8000_stv090x_config,
  1111. &i2c_bus->i2c_adap,
  1112. STV090x_DEMODULATOR_0);
  1113. if (fe0->dvb.frontend != NULL) {
  1114. if (!dvb_attach(stb6100_attach,
  1115. fe0->dvb.frontend,
  1116. &prof_8000_stb6100_config,
  1117. &i2c_bus->i2c_adap))
  1118. goto frontend_detach;
  1119. fe0->dvb.frontend->ops.set_voltage = p8000_set_voltage;
  1120. }
  1121. break;
  1122. default:
  1123. printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
  1124. " isn't supported yet\n",
  1125. dev->name);
  1126. break;
  1127. }
  1128. if ((NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend)) {
  1129. printk(KERN_ERR "%s: frontend initialization failed\n",
  1130. dev->name);
  1131. goto frontend_detach;
  1132. }
  1133. /* define general-purpose callback pointer */
  1134. fe0->dvb.frontend->callback = cx23885_tuner_callback;
  1135. if (fe1)
  1136. fe1->dvb.frontend->callback = cx23885_tuner_callback;
  1137. #if 0
  1138. /* Ensure all frontends negotiate bus access */
  1139. fe0->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
  1140. if (fe1)
  1141. fe1->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
  1142. #endif
  1143. /* Put the analog decoder in standby to keep it quiet */
  1144. call_all(dev, core, s_power, 0);
  1145. if (fe0->dvb.frontend->ops.analog_ops.standby)
  1146. fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
  1147. /* register everything */
  1148. ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
  1149. &dev->pci->dev, adapter_nr, mfe_shared);
  1150. if (ret)
  1151. goto frontend_detach;
  1152. /* init CI & MAC */
  1153. switch (dev->board) {
  1154. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
  1155. static struct netup_card_info cinfo;
  1156. netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
  1157. memcpy(port->frontends.adapter.proposed_mac,
  1158. cinfo.port[port->nr - 1].mac, 6);
  1159. printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC=%pM\n",
  1160. port->nr, port->frontends.adapter.proposed_mac);
  1161. netup_ci_init(port);
  1162. break;
  1163. }
  1164. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
  1165. struct altera_ci_config netup_ci_cfg = {
  1166. .dev = dev,/* magic number to identify*/
  1167. .adapter = &port->frontends.adapter,/* for CI */
  1168. .demux = &fe0->dvb.demux,/* for hw pid filter */
  1169. .fpga_rw = netup_altera_fpga_rw,
  1170. };
  1171. altera_ci_init(&netup_ci_cfg, port->nr);
  1172. break;
  1173. }
  1174. case CX23885_BOARD_TEVII_S470: {
  1175. u8 eeprom[256]; /* 24C02 i2c eeprom */
  1176. if (port->nr != 1)
  1177. break;
  1178. /* Read entire EEPROM */
  1179. dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
  1180. tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom, sizeof(eeprom));
  1181. printk(KERN_INFO "TeVii S470 MAC= %pM\n", eeprom + 0xa0);
  1182. memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xa0, 6);
  1183. break;
  1184. }
  1185. }
  1186. return ret;
  1187. frontend_detach:
  1188. port->gate_ctrl = NULL;
  1189. videobuf_dvb_dealloc_frontends(&port->frontends);
  1190. return -EINVAL;
  1191. }
  1192. int cx23885_dvb_register(struct cx23885_tsport *port)
  1193. {
  1194. struct videobuf_dvb_frontend *fe0;
  1195. struct cx23885_dev *dev = port->dev;
  1196. int err, i;
  1197. /* Here we need to allocate the correct number of frontends,
  1198. * as reflected in the cards struct. The reality is that currently
  1199. * no cx23885 boards support this - yet. But, if we don't modify this
  1200. * code then the second frontend would never be allocated (later)
  1201. * and fail with error before the attach in dvb_register().
  1202. * Without these changes we risk an OOPS later. The changes here
  1203. * are for safety, and should provide a good foundation for the
  1204. * future addition of any multi-frontend cx23885 based boards.
  1205. */
  1206. printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
  1207. port->num_frontends);
  1208. for (i = 1; i <= port->num_frontends; i++) {
  1209. if (videobuf_dvb_alloc_frontend(
  1210. &port->frontends, i) == NULL) {
  1211. printk(KERN_ERR "%s() failed to alloc\n", __func__);
  1212. return -ENOMEM;
  1213. }
  1214. fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
  1215. if (!fe0)
  1216. err = -EINVAL;
  1217. dprintk(1, "%s\n", __func__);
  1218. dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
  1219. dev->board,
  1220. dev->name,
  1221. dev->pci_bus,
  1222. dev->pci_slot);
  1223. err = -ENODEV;
  1224. /* dvb stuff */
  1225. /* We have to init the queue for each frontend on a port. */
  1226. printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
  1227. videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
  1228. &dev->pci->dev, &port->slock,
  1229. V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
  1230. sizeof(struct cx23885_buffer), port, NULL);
  1231. }
  1232. err = dvb_register(port);
  1233. if (err != 0)
  1234. printk(KERN_ERR "%s() dvb_register failed err = %d\n",
  1235. __func__, err);
  1236. return err;
  1237. }
  1238. int cx23885_dvb_unregister(struct cx23885_tsport *port)
  1239. {
  1240. struct videobuf_dvb_frontend *fe0;
  1241. /* FIXME: in an error condition where the we have
  1242. * an expected number of frontends (attach problem)
  1243. * then this might not clean up correctly, if 1
  1244. * is invalid.
  1245. * This comment only applies to future boards IF they
  1246. * implement MFE support.
  1247. */
  1248. fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
  1249. if (fe0 && fe0->dvb.frontend)
  1250. videobuf_dvb_unregister_bus(&port->frontends);
  1251. switch (port->dev->board) {
  1252. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1253. netup_ci_exit(port);
  1254. break;
  1255. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1256. altera_ci_release(port->dev, port->nr);
  1257. break;
  1258. }
  1259. port->gate_ctrl = NULL;
  1260. return 0;
  1261. }