edac_mc_sysfs.c 29 KB

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  1. /*
  2. * edac_mc kernel module
  3. * (C) 2005-2007 Linux Networx (http://lnxi.com)
  4. *
  5. * This file may be distributed under the terms of the
  6. * GNU General Public License.
  7. *
  8. * Written Doug Thompson <norsk5@xmission.com> www.softwarebitmaker.com
  9. *
  10. * (c) 2012 - Mauro Carvalho Chehab <mchehab@redhat.com>
  11. * The entire API were re-written, and ported to use struct device
  12. *
  13. */
  14. #include <linux/ctype.h>
  15. #include <linux/slab.h>
  16. #include <linux/edac.h>
  17. #include <linux/bug.h>
  18. #include <linux/pm_runtime.h>
  19. #include <linux/uaccess.h>
  20. #include "edac_core.h"
  21. #include "edac_module.h"
  22. /* MC EDAC Controls, setable by module parameter, and sysfs */
  23. static int edac_mc_log_ue = 1;
  24. static int edac_mc_log_ce = 1;
  25. static int edac_mc_panic_on_ue;
  26. static int edac_mc_poll_msec = 1000;
  27. /* Getter functions for above */
  28. int edac_mc_get_log_ue(void)
  29. {
  30. return edac_mc_log_ue;
  31. }
  32. int edac_mc_get_log_ce(void)
  33. {
  34. return edac_mc_log_ce;
  35. }
  36. int edac_mc_get_panic_on_ue(void)
  37. {
  38. return edac_mc_panic_on_ue;
  39. }
  40. /* this is temporary */
  41. int edac_mc_get_poll_msec(void)
  42. {
  43. return edac_mc_poll_msec;
  44. }
  45. static int edac_set_poll_msec(const char *val, struct kernel_param *kp)
  46. {
  47. long l;
  48. int ret;
  49. if (!val)
  50. return -EINVAL;
  51. ret = strict_strtol(val, 0, &l);
  52. if (ret == -EINVAL || ((int)l != l))
  53. return -EINVAL;
  54. *((int *)kp->arg) = l;
  55. /* notify edac_mc engine to reset the poll period */
  56. edac_mc_reset_delay_period(l);
  57. return 0;
  58. }
  59. /* Parameter declarations for above */
  60. module_param(edac_mc_panic_on_ue, int, 0644);
  61. MODULE_PARM_DESC(edac_mc_panic_on_ue, "Panic on uncorrected error: 0=off 1=on");
  62. module_param(edac_mc_log_ue, int, 0644);
  63. MODULE_PARM_DESC(edac_mc_log_ue,
  64. "Log uncorrectable error to console: 0=off 1=on");
  65. module_param(edac_mc_log_ce, int, 0644);
  66. MODULE_PARM_DESC(edac_mc_log_ce,
  67. "Log correctable error to console: 0=off 1=on");
  68. module_param_call(edac_mc_poll_msec, edac_set_poll_msec, param_get_int,
  69. &edac_mc_poll_msec, 0644);
  70. MODULE_PARM_DESC(edac_mc_poll_msec, "Polling period in milliseconds");
  71. static struct device *mci_pdev;
  72. /*
  73. * various constants for Memory Controllers
  74. */
  75. static const char *mem_types[] = {
  76. [MEM_EMPTY] = "Empty",
  77. [MEM_RESERVED] = "Reserved",
  78. [MEM_UNKNOWN] = "Unknown",
  79. [MEM_FPM] = "FPM",
  80. [MEM_EDO] = "EDO",
  81. [MEM_BEDO] = "BEDO",
  82. [MEM_SDR] = "Unbuffered-SDR",
  83. [MEM_RDR] = "Registered-SDR",
  84. [MEM_DDR] = "Unbuffered-DDR",
  85. [MEM_RDDR] = "Registered-DDR",
  86. [MEM_RMBS] = "RMBS",
  87. [MEM_DDR2] = "Unbuffered-DDR2",
  88. [MEM_FB_DDR2] = "FullyBuffered-DDR2",
  89. [MEM_RDDR2] = "Registered-DDR2",
  90. [MEM_XDR] = "XDR",
  91. [MEM_DDR3] = "Unbuffered-DDR3",
  92. [MEM_RDDR3] = "Registered-DDR3"
  93. };
  94. static const char *dev_types[] = {
  95. [DEV_UNKNOWN] = "Unknown",
  96. [DEV_X1] = "x1",
  97. [DEV_X2] = "x2",
  98. [DEV_X4] = "x4",
  99. [DEV_X8] = "x8",
  100. [DEV_X16] = "x16",
  101. [DEV_X32] = "x32",
  102. [DEV_X64] = "x64"
  103. };
  104. static const char *edac_caps[] = {
  105. [EDAC_UNKNOWN] = "Unknown",
  106. [EDAC_NONE] = "None",
  107. [EDAC_RESERVED] = "Reserved",
  108. [EDAC_PARITY] = "PARITY",
  109. [EDAC_EC] = "EC",
  110. [EDAC_SECDED] = "SECDED",
  111. [EDAC_S2ECD2ED] = "S2ECD2ED",
  112. [EDAC_S4ECD4ED] = "S4ECD4ED",
  113. [EDAC_S8ECD8ED] = "S8ECD8ED",
  114. [EDAC_S16ECD16ED] = "S16ECD16ED"
  115. };
  116. #ifdef CONFIG_EDAC_LEGACY_SYSFS
  117. /*
  118. * EDAC sysfs CSROW data structures and methods
  119. */
  120. #define to_csrow(k) container_of(k, struct csrow_info, dev)
  121. /*
  122. * We need it to avoid namespace conflicts between the legacy API
  123. * and the per-dimm/per-rank one
  124. */
  125. #define DEVICE_ATTR_LEGACY(_name, _mode, _show, _store) \
  126. struct device_attribute dev_attr_legacy_##_name = __ATTR(_name, _mode, _show, _store)
  127. struct dev_ch_attribute {
  128. struct device_attribute attr;
  129. int channel;
  130. };
  131. #define DEVICE_CHANNEL(_name, _mode, _show, _store, _var) \
  132. struct dev_ch_attribute dev_attr_legacy_##_name = \
  133. { __ATTR(_name, _mode, _show, _store), (_var) }
  134. #define to_channel(k) (container_of(k, struct dev_ch_attribute, attr)->channel)
  135. /* Set of more default csrow<id> attribute show/store functions */
  136. static ssize_t csrow_ue_count_show(struct device *dev,
  137. struct device_attribute *mattr, char *data)
  138. {
  139. struct csrow_info *csrow = to_csrow(dev);
  140. return sprintf(data, "%u\n", csrow->ue_count);
  141. }
  142. static ssize_t csrow_ce_count_show(struct device *dev,
  143. struct device_attribute *mattr, char *data)
  144. {
  145. struct csrow_info *csrow = to_csrow(dev);
  146. return sprintf(data, "%u\n", csrow->ce_count);
  147. }
  148. static ssize_t csrow_size_show(struct device *dev,
  149. struct device_attribute *mattr, char *data)
  150. {
  151. struct csrow_info *csrow = to_csrow(dev);
  152. int i;
  153. u32 nr_pages = 0;
  154. if (csrow->mci->csbased)
  155. return sprintf(data, "%u\n", PAGES_TO_MiB(csrow->nr_pages));
  156. for (i = 0; i < csrow->nr_channels; i++)
  157. nr_pages += csrow->channels[i]->dimm->nr_pages;
  158. return sprintf(data, "%u\n", PAGES_TO_MiB(nr_pages));
  159. }
  160. static ssize_t csrow_mem_type_show(struct device *dev,
  161. struct device_attribute *mattr, char *data)
  162. {
  163. struct csrow_info *csrow = to_csrow(dev);
  164. return sprintf(data, "%s\n", mem_types[csrow->channels[0]->dimm->mtype]);
  165. }
  166. static ssize_t csrow_dev_type_show(struct device *dev,
  167. struct device_attribute *mattr, char *data)
  168. {
  169. struct csrow_info *csrow = to_csrow(dev);
  170. return sprintf(data, "%s\n", dev_types[csrow->channels[0]->dimm->dtype]);
  171. }
  172. static ssize_t csrow_edac_mode_show(struct device *dev,
  173. struct device_attribute *mattr,
  174. char *data)
  175. {
  176. struct csrow_info *csrow = to_csrow(dev);
  177. return sprintf(data, "%s\n", edac_caps[csrow->channels[0]->dimm->edac_mode]);
  178. }
  179. /* show/store functions for DIMM Label attributes */
  180. static ssize_t channel_dimm_label_show(struct device *dev,
  181. struct device_attribute *mattr,
  182. char *data)
  183. {
  184. struct csrow_info *csrow = to_csrow(dev);
  185. unsigned chan = to_channel(mattr);
  186. struct rank_info *rank = csrow->channels[chan];
  187. /* if field has not been initialized, there is nothing to send */
  188. if (!rank->dimm->label[0])
  189. return 0;
  190. return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n",
  191. rank->dimm->label);
  192. }
  193. static ssize_t channel_dimm_label_store(struct device *dev,
  194. struct device_attribute *mattr,
  195. const char *data, size_t count)
  196. {
  197. struct csrow_info *csrow = to_csrow(dev);
  198. unsigned chan = to_channel(mattr);
  199. struct rank_info *rank = csrow->channels[chan];
  200. ssize_t max_size = 0;
  201. max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1);
  202. strncpy(rank->dimm->label, data, max_size);
  203. rank->dimm->label[max_size] = '\0';
  204. return max_size;
  205. }
  206. /* show function for dynamic chX_ce_count attribute */
  207. static ssize_t channel_ce_count_show(struct device *dev,
  208. struct device_attribute *mattr, char *data)
  209. {
  210. struct csrow_info *csrow = to_csrow(dev);
  211. unsigned chan = to_channel(mattr);
  212. struct rank_info *rank = csrow->channels[chan];
  213. return sprintf(data, "%u\n", rank->ce_count);
  214. }
  215. /* cwrow<id>/attribute files */
  216. DEVICE_ATTR_LEGACY(size_mb, S_IRUGO, csrow_size_show, NULL);
  217. DEVICE_ATTR_LEGACY(dev_type, S_IRUGO, csrow_dev_type_show, NULL);
  218. DEVICE_ATTR_LEGACY(mem_type, S_IRUGO, csrow_mem_type_show, NULL);
  219. DEVICE_ATTR_LEGACY(edac_mode, S_IRUGO, csrow_edac_mode_show, NULL);
  220. DEVICE_ATTR_LEGACY(ue_count, S_IRUGO, csrow_ue_count_show, NULL);
  221. DEVICE_ATTR_LEGACY(ce_count, S_IRUGO, csrow_ce_count_show, NULL);
  222. /* default attributes of the CSROW<id> object */
  223. static struct attribute *csrow_attrs[] = {
  224. &dev_attr_legacy_dev_type.attr,
  225. &dev_attr_legacy_mem_type.attr,
  226. &dev_attr_legacy_edac_mode.attr,
  227. &dev_attr_legacy_size_mb.attr,
  228. &dev_attr_legacy_ue_count.attr,
  229. &dev_attr_legacy_ce_count.attr,
  230. NULL,
  231. };
  232. static struct attribute_group csrow_attr_grp = {
  233. .attrs = csrow_attrs,
  234. };
  235. static const struct attribute_group *csrow_attr_groups[] = {
  236. &csrow_attr_grp,
  237. NULL
  238. };
  239. static void csrow_attr_release(struct device *dev)
  240. {
  241. struct csrow_info *csrow = container_of(dev, struct csrow_info, dev);
  242. edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev));
  243. kfree(csrow);
  244. }
  245. static struct device_type csrow_attr_type = {
  246. .groups = csrow_attr_groups,
  247. .release = csrow_attr_release,
  248. };
  249. /*
  250. * possible dynamic channel DIMM Label attribute files
  251. *
  252. */
  253. #define EDAC_NR_CHANNELS 6
  254. DEVICE_CHANNEL(ch0_dimm_label, S_IRUGO | S_IWUSR,
  255. channel_dimm_label_show, channel_dimm_label_store, 0);
  256. DEVICE_CHANNEL(ch1_dimm_label, S_IRUGO | S_IWUSR,
  257. channel_dimm_label_show, channel_dimm_label_store, 1);
  258. DEVICE_CHANNEL(ch2_dimm_label, S_IRUGO | S_IWUSR,
  259. channel_dimm_label_show, channel_dimm_label_store, 2);
  260. DEVICE_CHANNEL(ch3_dimm_label, S_IRUGO | S_IWUSR,
  261. channel_dimm_label_show, channel_dimm_label_store, 3);
  262. DEVICE_CHANNEL(ch4_dimm_label, S_IRUGO | S_IWUSR,
  263. channel_dimm_label_show, channel_dimm_label_store, 4);
  264. DEVICE_CHANNEL(ch5_dimm_label, S_IRUGO | S_IWUSR,
  265. channel_dimm_label_show, channel_dimm_label_store, 5);
  266. /* Total possible dynamic DIMM Label attribute file table */
  267. static struct device_attribute *dynamic_csrow_dimm_attr[] = {
  268. &dev_attr_legacy_ch0_dimm_label.attr,
  269. &dev_attr_legacy_ch1_dimm_label.attr,
  270. &dev_attr_legacy_ch2_dimm_label.attr,
  271. &dev_attr_legacy_ch3_dimm_label.attr,
  272. &dev_attr_legacy_ch4_dimm_label.attr,
  273. &dev_attr_legacy_ch5_dimm_label.attr
  274. };
  275. /* possible dynamic channel ce_count attribute files */
  276. DEVICE_CHANNEL(ch0_ce_count, S_IRUGO | S_IWUSR,
  277. channel_ce_count_show, NULL, 0);
  278. DEVICE_CHANNEL(ch1_ce_count, S_IRUGO | S_IWUSR,
  279. channel_ce_count_show, NULL, 1);
  280. DEVICE_CHANNEL(ch2_ce_count, S_IRUGO | S_IWUSR,
  281. channel_ce_count_show, NULL, 2);
  282. DEVICE_CHANNEL(ch3_ce_count, S_IRUGO | S_IWUSR,
  283. channel_ce_count_show, NULL, 3);
  284. DEVICE_CHANNEL(ch4_ce_count, S_IRUGO | S_IWUSR,
  285. channel_ce_count_show, NULL, 4);
  286. DEVICE_CHANNEL(ch5_ce_count, S_IRUGO | S_IWUSR,
  287. channel_ce_count_show, NULL, 5);
  288. /* Total possible dynamic ce_count attribute file table */
  289. static struct device_attribute *dynamic_csrow_ce_count_attr[] = {
  290. &dev_attr_legacy_ch0_ce_count.attr,
  291. &dev_attr_legacy_ch1_ce_count.attr,
  292. &dev_attr_legacy_ch2_ce_count.attr,
  293. &dev_attr_legacy_ch3_ce_count.attr,
  294. &dev_attr_legacy_ch4_ce_count.attr,
  295. &dev_attr_legacy_ch5_ce_count.attr
  296. };
  297. static inline int nr_pages_per_csrow(struct csrow_info *csrow)
  298. {
  299. int chan, nr_pages = 0;
  300. for (chan = 0; chan < csrow->nr_channels; chan++)
  301. nr_pages += csrow->channels[chan]->dimm->nr_pages;
  302. return nr_pages;
  303. }
  304. /* Create a CSROW object under specifed edac_mc_device */
  305. static int edac_create_csrow_object(struct mem_ctl_info *mci,
  306. struct csrow_info *csrow, int index)
  307. {
  308. int err, chan;
  309. if (csrow->nr_channels >= EDAC_NR_CHANNELS)
  310. return -ENODEV;
  311. csrow->dev.type = &csrow_attr_type;
  312. csrow->dev.bus = &mci->bus;
  313. device_initialize(&csrow->dev);
  314. csrow->dev.parent = &mci->dev;
  315. csrow->mci = mci;
  316. dev_set_name(&csrow->dev, "csrow%d", index);
  317. dev_set_drvdata(&csrow->dev, csrow);
  318. edac_dbg(0, "creating (virtual) csrow node %s\n",
  319. dev_name(&csrow->dev));
  320. err = device_add(&csrow->dev);
  321. if (err < 0)
  322. return err;
  323. for (chan = 0; chan < csrow->nr_channels; chan++) {
  324. /* Only expose populated DIMMs */
  325. if (!csrow->channels[chan]->dimm->nr_pages)
  326. continue;
  327. err = device_create_file(&csrow->dev,
  328. dynamic_csrow_dimm_attr[chan]);
  329. if (err < 0)
  330. goto error;
  331. err = device_create_file(&csrow->dev,
  332. dynamic_csrow_ce_count_attr[chan]);
  333. if (err < 0) {
  334. device_remove_file(&csrow->dev,
  335. dynamic_csrow_dimm_attr[chan]);
  336. goto error;
  337. }
  338. }
  339. return 0;
  340. error:
  341. for (--chan; chan >= 0; chan--) {
  342. device_remove_file(&csrow->dev,
  343. dynamic_csrow_dimm_attr[chan]);
  344. device_remove_file(&csrow->dev,
  345. dynamic_csrow_ce_count_attr[chan]);
  346. }
  347. put_device(&csrow->dev);
  348. return err;
  349. }
  350. /* Create a CSROW object under specifed edac_mc_device */
  351. static int edac_create_csrow_objects(struct mem_ctl_info *mci)
  352. {
  353. int err, i, chan;
  354. struct csrow_info *csrow;
  355. for (i = 0; i < mci->nr_csrows; i++) {
  356. csrow = mci->csrows[i];
  357. if (!nr_pages_per_csrow(csrow))
  358. continue;
  359. err = edac_create_csrow_object(mci, mci->csrows[i], i);
  360. if (err < 0)
  361. goto error;
  362. }
  363. return 0;
  364. error:
  365. for (--i; i >= 0; i--) {
  366. csrow = mci->csrows[i];
  367. if (!nr_pages_per_csrow(csrow))
  368. continue;
  369. for (chan = csrow->nr_channels - 1; chan >= 0; chan--) {
  370. if (!csrow->channels[chan]->dimm->nr_pages)
  371. continue;
  372. device_remove_file(&csrow->dev,
  373. dynamic_csrow_dimm_attr[chan]);
  374. device_remove_file(&csrow->dev,
  375. dynamic_csrow_ce_count_attr[chan]);
  376. }
  377. put_device(&mci->csrows[i]->dev);
  378. }
  379. return err;
  380. }
  381. static void edac_delete_csrow_objects(struct mem_ctl_info *mci)
  382. {
  383. int i, chan;
  384. struct csrow_info *csrow;
  385. for (i = mci->nr_csrows - 1; i >= 0; i--) {
  386. csrow = mci->csrows[i];
  387. if (!nr_pages_per_csrow(csrow))
  388. continue;
  389. for (chan = csrow->nr_channels - 1; chan >= 0; chan--) {
  390. if (!csrow->channels[chan]->dimm->nr_pages)
  391. continue;
  392. edac_dbg(1, "Removing csrow %d channel %d sysfs nodes\n",
  393. i, chan);
  394. device_remove_file(&csrow->dev,
  395. dynamic_csrow_dimm_attr[chan]);
  396. device_remove_file(&csrow->dev,
  397. dynamic_csrow_ce_count_attr[chan]);
  398. }
  399. device_unregister(&mci->csrows[i]->dev);
  400. }
  401. }
  402. #endif
  403. /*
  404. * Per-dimm (or per-rank) devices
  405. */
  406. #define to_dimm(k) container_of(k, struct dimm_info, dev)
  407. /* show/store functions for DIMM Label attributes */
  408. static ssize_t dimmdev_location_show(struct device *dev,
  409. struct device_attribute *mattr, char *data)
  410. {
  411. struct dimm_info *dimm = to_dimm(dev);
  412. return edac_dimm_info_location(dimm, data, PAGE_SIZE);
  413. }
  414. static ssize_t dimmdev_label_show(struct device *dev,
  415. struct device_attribute *mattr, char *data)
  416. {
  417. struct dimm_info *dimm = to_dimm(dev);
  418. /* if field has not been initialized, there is nothing to send */
  419. if (!dimm->label[0])
  420. return 0;
  421. return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n", dimm->label);
  422. }
  423. static ssize_t dimmdev_label_store(struct device *dev,
  424. struct device_attribute *mattr,
  425. const char *data,
  426. size_t count)
  427. {
  428. struct dimm_info *dimm = to_dimm(dev);
  429. ssize_t max_size = 0;
  430. max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1);
  431. strncpy(dimm->label, data, max_size);
  432. dimm->label[max_size] = '\0';
  433. return max_size;
  434. }
  435. static ssize_t dimmdev_size_show(struct device *dev,
  436. struct device_attribute *mattr, char *data)
  437. {
  438. struct dimm_info *dimm = to_dimm(dev);
  439. return sprintf(data, "%u\n", PAGES_TO_MiB(dimm->nr_pages));
  440. }
  441. static ssize_t dimmdev_mem_type_show(struct device *dev,
  442. struct device_attribute *mattr, char *data)
  443. {
  444. struct dimm_info *dimm = to_dimm(dev);
  445. return sprintf(data, "%s\n", mem_types[dimm->mtype]);
  446. }
  447. static ssize_t dimmdev_dev_type_show(struct device *dev,
  448. struct device_attribute *mattr, char *data)
  449. {
  450. struct dimm_info *dimm = to_dimm(dev);
  451. return sprintf(data, "%s\n", dev_types[dimm->dtype]);
  452. }
  453. static ssize_t dimmdev_edac_mode_show(struct device *dev,
  454. struct device_attribute *mattr,
  455. char *data)
  456. {
  457. struct dimm_info *dimm = to_dimm(dev);
  458. return sprintf(data, "%s\n", edac_caps[dimm->edac_mode]);
  459. }
  460. /* dimm/rank attribute files */
  461. static DEVICE_ATTR(dimm_label, S_IRUGO | S_IWUSR,
  462. dimmdev_label_show, dimmdev_label_store);
  463. static DEVICE_ATTR(dimm_location, S_IRUGO, dimmdev_location_show, NULL);
  464. static DEVICE_ATTR(size, S_IRUGO, dimmdev_size_show, NULL);
  465. static DEVICE_ATTR(dimm_mem_type, S_IRUGO, dimmdev_mem_type_show, NULL);
  466. static DEVICE_ATTR(dimm_dev_type, S_IRUGO, dimmdev_dev_type_show, NULL);
  467. static DEVICE_ATTR(dimm_edac_mode, S_IRUGO, dimmdev_edac_mode_show, NULL);
  468. /* attributes of the dimm<id>/rank<id> object */
  469. static struct attribute *dimm_attrs[] = {
  470. &dev_attr_dimm_label.attr,
  471. &dev_attr_dimm_location.attr,
  472. &dev_attr_size.attr,
  473. &dev_attr_dimm_mem_type.attr,
  474. &dev_attr_dimm_dev_type.attr,
  475. &dev_attr_dimm_edac_mode.attr,
  476. NULL,
  477. };
  478. static struct attribute_group dimm_attr_grp = {
  479. .attrs = dimm_attrs,
  480. };
  481. static const struct attribute_group *dimm_attr_groups[] = {
  482. &dimm_attr_grp,
  483. NULL
  484. };
  485. static void dimm_attr_release(struct device *dev)
  486. {
  487. struct dimm_info *dimm = container_of(dev, struct dimm_info, dev);
  488. edac_dbg(1, "Releasing dimm device %s\n", dev_name(dev));
  489. kfree(dimm);
  490. }
  491. static struct device_type dimm_attr_type = {
  492. .groups = dimm_attr_groups,
  493. .release = dimm_attr_release,
  494. };
  495. /* Create a DIMM object under specifed memory controller device */
  496. static int edac_create_dimm_object(struct mem_ctl_info *mci,
  497. struct dimm_info *dimm,
  498. int index)
  499. {
  500. int err;
  501. dimm->mci = mci;
  502. dimm->dev.type = &dimm_attr_type;
  503. dimm->dev.bus = &mci->bus;
  504. device_initialize(&dimm->dev);
  505. dimm->dev.parent = &mci->dev;
  506. if (mci->mem_is_per_rank)
  507. dev_set_name(&dimm->dev, "rank%d", index);
  508. else
  509. dev_set_name(&dimm->dev, "dimm%d", index);
  510. dev_set_drvdata(&dimm->dev, dimm);
  511. pm_runtime_forbid(&mci->dev);
  512. err = device_add(&dimm->dev);
  513. edac_dbg(0, "creating rank/dimm device %s\n", dev_name(&dimm->dev));
  514. return err;
  515. }
  516. /*
  517. * Memory controller device
  518. */
  519. #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
  520. static ssize_t mci_reset_counters_store(struct device *dev,
  521. struct device_attribute *mattr,
  522. const char *data, size_t count)
  523. {
  524. struct mem_ctl_info *mci = to_mci(dev);
  525. int cnt, row, chan, i;
  526. mci->ue_mc = 0;
  527. mci->ce_mc = 0;
  528. mci->ue_noinfo_count = 0;
  529. mci->ce_noinfo_count = 0;
  530. for (row = 0; row < mci->nr_csrows; row++) {
  531. struct csrow_info *ri = mci->csrows[row];
  532. ri->ue_count = 0;
  533. ri->ce_count = 0;
  534. for (chan = 0; chan < ri->nr_channels; chan++)
  535. ri->channels[chan]->ce_count = 0;
  536. }
  537. cnt = 1;
  538. for (i = 0; i < mci->n_layers; i++) {
  539. cnt *= mci->layers[i].size;
  540. memset(mci->ce_per_layer[i], 0, cnt * sizeof(u32));
  541. memset(mci->ue_per_layer[i], 0, cnt * sizeof(u32));
  542. }
  543. mci->start_time = jiffies;
  544. return count;
  545. }
  546. /* Memory scrubbing interface:
  547. *
  548. * A MC driver can limit the scrubbing bandwidth based on the CPU type.
  549. * Therefore, ->set_sdram_scrub_rate should be made to return the actual
  550. * bandwidth that is accepted or 0 when scrubbing is to be disabled.
  551. *
  552. * Negative value still means that an error has occurred while setting
  553. * the scrub rate.
  554. */
  555. static ssize_t mci_sdram_scrub_rate_store(struct device *dev,
  556. struct device_attribute *mattr,
  557. const char *data, size_t count)
  558. {
  559. struct mem_ctl_info *mci = to_mci(dev);
  560. unsigned long bandwidth = 0;
  561. int new_bw = 0;
  562. if (!mci->set_sdram_scrub_rate)
  563. return -ENODEV;
  564. if (strict_strtoul(data, 10, &bandwidth) < 0)
  565. return -EINVAL;
  566. new_bw = mci->set_sdram_scrub_rate(mci, bandwidth);
  567. if (new_bw < 0) {
  568. edac_printk(KERN_WARNING, EDAC_MC,
  569. "Error setting scrub rate to: %lu\n", bandwidth);
  570. return -EINVAL;
  571. }
  572. return count;
  573. }
  574. /*
  575. * ->get_sdram_scrub_rate() return value semantics same as above.
  576. */
  577. static ssize_t mci_sdram_scrub_rate_show(struct device *dev,
  578. struct device_attribute *mattr,
  579. char *data)
  580. {
  581. struct mem_ctl_info *mci = to_mci(dev);
  582. int bandwidth = 0;
  583. if (!mci->get_sdram_scrub_rate)
  584. return -ENODEV;
  585. bandwidth = mci->get_sdram_scrub_rate(mci);
  586. if (bandwidth < 0) {
  587. edac_printk(KERN_DEBUG, EDAC_MC, "Error reading scrub rate\n");
  588. return bandwidth;
  589. }
  590. return sprintf(data, "%d\n", bandwidth);
  591. }
  592. /* default attribute files for the MCI object */
  593. static ssize_t mci_ue_count_show(struct device *dev,
  594. struct device_attribute *mattr,
  595. char *data)
  596. {
  597. struct mem_ctl_info *mci = to_mci(dev);
  598. return sprintf(data, "%d\n", mci->ue_mc);
  599. }
  600. static ssize_t mci_ce_count_show(struct device *dev,
  601. struct device_attribute *mattr,
  602. char *data)
  603. {
  604. struct mem_ctl_info *mci = to_mci(dev);
  605. return sprintf(data, "%d\n", mci->ce_mc);
  606. }
  607. static ssize_t mci_ce_noinfo_show(struct device *dev,
  608. struct device_attribute *mattr,
  609. char *data)
  610. {
  611. struct mem_ctl_info *mci = to_mci(dev);
  612. return sprintf(data, "%d\n", mci->ce_noinfo_count);
  613. }
  614. static ssize_t mci_ue_noinfo_show(struct device *dev,
  615. struct device_attribute *mattr,
  616. char *data)
  617. {
  618. struct mem_ctl_info *mci = to_mci(dev);
  619. return sprintf(data, "%d\n", mci->ue_noinfo_count);
  620. }
  621. static ssize_t mci_seconds_show(struct device *dev,
  622. struct device_attribute *mattr,
  623. char *data)
  624. {
  625. struct mem_ctl_info *mci = to_mci(dev);
  626. return sprintf(data, "%ld\n", (jiffies - mci->start_time) / HZ);
  627. }
  628. static ssize_t mci_ctl_name_show(struct device *dev,
  629. struct device_attribute *mattr,
  630. char *data)
  631. {
  632. struct mem_ctl_info *mci = to_mci(dev);
  633. return sprintf(data, "%s\n", mci->ctl_name);
  634. }
  635. static ssize_t mci_size_mb_show(struct device *dev,
  636. struct device_attribute *mattr,
  637. char *data)
  638. {
  639. struct mem_ctl_info *mci = to_mci(dev);
  640. int total_pages = 0, csrow_idx, j;
  641. for (csrow_idx = 0; csrow_idx < mci->nr_csrows; csrow_idx++) {
  642. struct csrow_info *csrow = mci->csrows[csrow_idx];
  643. if (csrow->mci->csbased) {
  644. total_pages += csrow->nr_pages;
  645. } else {
  646. for (j = 0; j < csrow->nr_channels; j++) {
  647. struct dimm_info *dimm = csrow->channels[j]->dimm;
  648. total_pages += dimm->nr_pages;
  649. }
  650. }
  651. }
  652. return sprintf(data, "%u\n", PAGES_TO_MiB(total_pages));
  653. }
  654. static ssize_t mci_max_location_show(struct device *dev,
  655. struct device_attribute *mattr,
  656. char *data)
  657. {
  658. struct mem_ctl_info *mci = to_mci(dev);
  659. int i;
  660. char *p = data;
  661. for (i = 0; i < mci->n_layers; i++) {
  662. p += sprintf(p, "%s %d ",
  663. edac_layer_name[mci->layers[i].type],
  664. mci->layers[i].size - 1);
  665. }
  666. return p - data;
  667. }
  668. #ifdef CONFIG_EDAC_DEBUG
  669. static ssize_t edac_fake_inject_write(struct file *file,
  670. const char __user *data,
  671. size_t count, loff_t *ppos)
  672. {
  673. struct device *dev = file->private_data;
  674. struct mem_ctl_info *mci = to_mci(dev);
  675. static enum hw_event_mc_err_type type;
  676. u16 errcount = mci->fake_inject_count;
  677. if (!errcount)
  678. errcount = 1;
  679. type = mci->fake_inject_ue ? HW_EVENT_ERR_UNCORRECTED
  680. : HW_EVENT_ERR_CORRECTED;
  681. printk(KERN_DEBUG
  682. "Generating %d %s fake error%s to %d.%d.%d to test core handling. NOTE: this won't test the driver-specific decoding logic.\n",
  683. errcount,
  684. (type == HW_EVENT_ERR_UNCORRECTED) ? "UE" : "CE",
  685. errcount > 1 ? "s" : "",
  686. mci->fake_inject_layer[0],
  687. mci->fake_inject_layer[1],
  688. mci->fake_inject_layer[2]
  689. );
  690. edac_mc_handle_error(type, mci, errcount, 0, 0, 0,
  691. mci->fake_inject_layer[0],
  692. mci->fake_inject_layer[1],
  693. mci->fake_inject_layer[2],
  694. "FAKE ERROR", "for EDAC testing only");
  695. return count;
  696. }
  697. static const struct file_operations debug_fake_inject_fops = {
  698. .open = simple_open,
  699. .write = edac_fake_inject_write,
  700. .llseek = generic_file_llseek,
  701. };
  702. #endif
  703. /* default Control file */
  704. DEVICE_ATTR(reset_counters, S_IWUSR, NULL, mci_reset_counters_store);
  705. /* default Attribute files */
  706. DEVICE_ATTR(mc_name, S_IRUGO, mci_ctl_name_show, NULL);
  707. DEVICE_ATTR(size_mb, S_IRUGO, mci_size_mb_show, NULL);
  708. DEVICE_ATTR(seconds_since_reset, S_IRUGO, mci_seconds_show, NULL);
  709. DEVICE_ATTR(ue_noinfo_count, S_IRUGO, mci_ue_noinfo_show, NULL);
  710. DEVICE_ATTR(ce_noinfo_count, S_IRUGO, mci_ce_noinfo_show, NULL);
  711. DEVICE_ATTR(ue_count, S_IRUGO, mci_ue_count_show, NULL);
  712. DEVICE_ATTR(ce_count, S_IRUGO, mci_ce_count_show, NULL);
  713. DEVICE_ATTR(max_location, S_IRUGO, mci_max_location_show, NULL);
  714. /* memory scrubber attribute file */
  715. DEVICE_ATTR(sdram_scrub_rate, S_IRUGO | S_IWUSR, mci_sdram_scrub_rate_show,
  716. mci_sdram_scrub_rate_store);
  717. static struct attribute *mci_attrs[] = {
  718. &dev_attr_reset_counters.attr,
  719. &dev_attr_mc_name.attr,
  720. &dev_attr_size_mb.attr,
  721. &dev_attr_seconds_since_reset.attr,
  722. &dev_attr_ue_noinfo_count.attr,
  723. &dev_attr_ce_noinfo_count.attr,
  724. &dev_attr_ue_count.attr,
  725. &dev_attr_ce_count.attr,
  726. &dev_attr_sdram_scrub_rate.attr,
  727. &dev_attr_max_location.attr,
  728. NULL
  729. };
  730. static struct attribute_group mci_attr_grp = {
  731. .attrs = mci_attrs,
  732. };
  733. static const struct attribute_group *mci_attr_groups[] = {
  734. &mci_attr_grp,
  735. NULL
  736. };
  737. static void mci_attr_release(struct device *dev)
  738. {
  739. struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev);
  740. edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev));
  741. kfree(mci);
  742. }
  743. static struct device_type mci_attr_type = {
  744. .groups = mci_attr_groups,
  745. .release = mci_attr_release,
  746. };
  747. #ifdef CONFIG_EDAC_DEBUG
  748. static struct dentry *edac_debugfs;
  749. int __init edac_debugfs_init(void)
  750. {
  751. edac_debugfs = debugfs_create_dir("edac", NULL);
  752. if (IS_ERR(edac_debugfs)) {
  753. edac_debugfs = NULL;
  754. return -ENOMEM;
  755. }
  756. return 0;
  757. }
  758. void __exit edac_debugfs_exit(void)
  759. {
  760. debugfs_remove(edac_debugfs);
  761. }
  762. int edac_create_debug_nodes(struct mem_ctl_info *mci)
  763. {
  764. struct dentry *d, *parent;
  765. char name[80];
  766. int i;
  767. if (!edac_debugfs)
  768. return -ENODEV;
  769. d = debugfs_create_dir(mci->dev.kobj.name, edac_debugfs);
  770. if (!d)
  771. return -ENOMEM;
  772. parent = d;
  773. for (i = 0; i < mci->n_layers; i++) {
  774. sprintf(name, "fake_inject_%s",
  775. edac_layer_name[mci->layers[i].type]);
  776. d = debugfs_create_u8(name, S_IRUGO | S_IWUSR, parent,
  777. &mci->fake_inject_layer[i]);
  778. if (!d)
  779. goto nomem;
  780. }
  781. d = debugfs_create_bool("fake_inject_ue", S_IRUGO | S_IWUSR, parent,
  782. &mci->fake_inject_ue);
  783. if (!d)
  784. goto nomem;
  785. d = debugfs_create_u16("fake_inject_count", S_IRUGO | S_IWUSR, parent,
  786. &mci->fake_inject_count);
  787. if (!d)
  788. goto nomem;
  789. d = debugfs_create_file("fake_inject", S_IWUSR, parent,
  790. &mci->dev,
  791. &debug_fake_inject_fops);
  792. if (!d)
  793. goto nomem;
  794. mci->debugfs = parent;
  795. return 0;
  796. nomem:
  797. debugfs_remove(mci->debugfs);
  798. return -ENOMEM;
  799. }
  800. #endif
  801. /*
  802. * Create a new Memory Controller kobject instance,
  803. * mc<id> under the 'mc' directory
  804. *
  805. * Return:
  806. * 0 Success
  807. * !0 Failure
  808. */
  809. int edac_create_sysfs_mci_device(struct mem_ctl_info *mci)
  810. {
  811. int i, err;
  812. /*
  813. * The memory controller needs its own bus, in order to avoid
  814. * namespace conflicts at /sys/bus/edac.
  815. */
  816. mci->bus.name = kasprintf(GFP_KERNEL, "mc%d", mci->mc_idx);
  817. if (!mci->bus.name)
  818. return -ENOMEM;
  819. edac_dbg(0, "creating bus %s\n", mci->bus.name);
  820. err = bus_register(&mci->bus);
  821. if (err < 0)
  822. return err;
  823. /* get the /sys/devices/system/edac subsys reference */
  824. mci->dev.type = &mci_attr_type;
  825. device_initialize(&mci->dev);
  826. mci->dev.parent = mci_pdev;
  827. mci->dev.bus = &mci->bus;
  828. dev_set_name(&mci->dev, "mc%d", mci->mc_idx);
  829. dev_set_drvdata(&mci->dev, mci);
  830. pm_runtime_forbid(&mci->dev);
  831. edac_dbg(0, "creating device %s\n", dev_name(&mci->dev));
  832. err = device_add(&mci->dev);
  833. if (err < 0) {
  834. bus_unregister(&mci->bus);
  835. kfree(mci->bus.name);
  836. return err;
  837. }
  838. /*
  839. * Create the dimm/rank devices
  840. */
  841. for (i = 0; i < mci->tot_dimms; i++) {
  842. struct dimm_info *dimm = mci->dimms[i];
  843. /* Only expose populated DIMMs */
  844. if (dimm->nr_pages == 0)
  845. continue;
  846. #ifdef CONFIG_EDAC_DEBUG
  847. edac_dbg(1, "creating dimm%d, located at ", i);
  848. if (edac_debug_level >= 1) {
  849. int lay;
  850. for (lay = 0; lay < mci->n_layers; lay++)
  851. printk(KERN_CONT "%s %d ",
  852. edac_layer_name[mci->layers[lay].type],
  853. dimm->location[lay]);
  854. printk(KERN_CONT "\n");
  855. }
  856. #endif
  857. err = edac_create_dimm_object(mci, dimm, i);
  858. if (err) {
  859. edac_dbg(1, "failure: create dimm %d obj\n", i);
  860. goto fail;
  861. }
  862. }
  863. #ifdef CONFIG_EDAC_LEGACY_SYSFS
  864. err = edac_create_csrow_objects(mci);
  865. if (err < 0)
  866. goto fail;
  867. #endif
  868. #ifdef CONFIG_EDAC_DEBUG
  869. edac_create_debug_nodes(mci);
  870. #endif
  871. return 0;
  872. fail:
  873. for (i--; i >= 0; i--) {
  874. struct dimm_info *dimm = mci->dimms[i];
  875. if (dimm->nr_pages == 0)
  876. continue;
  877. device_unregister(&dimm->dev);
  878. }
  879. device_unregister(&mci->dev);
  880. bus_unregister(&mci->bus);
  881. kfree(mci->bus.name);
  882. return err;
  883. }
  884. /*
  885. * remove a Memory Controller instance
  886. */
  887. void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci)
  888. {
  889. int i;
  890. edac_dbg(0, "\n");
  891. #ifdef CONFIG_EDAC_DEBUG
  892. debugfs_remove(mci->debugfs);
  893. #endif
  894. #ifdef CONFIG_EDAC_LEGACY_SYSFS
  895. edac_delete_csrow_objects(mci);
  896. #endif
  897. for (i = 0; i < mci->tot_dimms; i++) {
  898. struct dimm_info *dimm = mci->dimms[i];
  899. if (dimm->nr_pages == 0)
  900. continue;
  901. edac_dbg(0, "removing device %s\n", dev_name(&dimm->dev));
  902. device_unregister(&dimm->dev);
  903. }
  904. }
  905. void edac_unregister_sysfs(struct mem_ctl_info *mci)
  906. {
  907. edac_dbg(1, "Unregistering device %s\n", dev_name(&mci->dev));
  908. device_unregister(&mci->dev);
  909. bus_unregister(&mci->bus);
  910. kfree(mci->bus.name);
  911. }
  912. static void mc_attr_release(struct device *dev)
  913. {
  914. /*
  915. * There's no container structure here, as this is just the mci
  916. * parent device, used to create the /sys/devices/mc sysfs node.
  917. * So, there are no attributes on it.
  918. */
  919. edac_dbg(1, "Releasing device %s\n", dev_name(dev));
  920. kfree(dev);
  921. }
  922. static struct device_type mc_attr_type = {
  923. .release = mc_attr_release,
  924. };
  925. /*
  926. * Init/exit code for the module. Basically, creates/removes /sys/class/rc
  927. */
  928. int __init edac_mc_sysfs_init(void)
  929. {
  930. struct bus_type *edac_subsys;
  931. int err;
  932. /* get the /sys/devices/system/edac subsys reference */
  933. edac_subsys = edac_get_sysfs_subsys();
  934. if (edac_subsys == NULL) {
  935. edac_dbg(1, "no edac_subsys\n");
  936. err = -EINVAL;
  937. goto out;
  938. }
  939. mci_pdev = kzalloc(sizeof(*mci_pdev), GFP_KERNEL);
  940. if (!mci_pdev) {
  941. err = -ENOMEM;
  942. goto out_put_sysfs;
  943. }
  944. mci_pdev->bus = edac_subsys;
  945. mci_pdev->type = &mc_attr_type;
  946. device_initialize(mci_pdev);
  947. dev_set_name(mci_pdev, "mc");
  948. err = device_add(mci_pdev);
  949. if (err < 0)
  950. goto out_dev_free;
  951. edac_dbg(0, "device %s created\n", dev_name(mci_pdev));
  952. return 0;
  953. out_dev_free:
  954. kfree(mci_pdev);
  955. out_put_sysfs:
  956. edac_put_sysfs_subsys();
  957. out:
  958. return err;
  959. }
  960. void __exit edac_mc_sysfs_exit(void)
  961. {
  962. device_unregister(mci_pdev);
  963. edac_put_sysfs_subsys();
  964. }