tsc.c 26 KB

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  1. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  2. #include <linux/kernel.h>
  3. #include <linux/sched.h>
  4. #include <linux/init.h>
  5. #include <linux/module.h>
  6. #include <linux/timer.h>
  7. #include <linux/acpi_pmtmr.h>
  8. #include <linux/cpufreq.h>
  9. #include <linux/delay.h>
  10. #include <linux/clocksource.h>
  11. #include <linux/percpu.h>
  12. #include <linux/timex.h>
  13. #include <asm/hpet.h>
  14. #include <asm/timer.h>
  15. #include <asm/vgtod.h>
  16. #include <asm/time.h>
  17. #include <asm/delay.h>
  18. #include <asm/hypervisor.h>
  19. #include <asm/nmi.h>
  20. #include <asm/x86_init.h>
  21. unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */
  22. EXPORT_SYMBOL(cpu_khz);
  23. unsigned int __read_mostly tsc_khz;
  24. EXPORT_SYMBOL(tsc_khz);
  25. /*
  26. * TSC can be unstable due to cpufreq or due to unsynced TSCs
  27. */
  28. static int __read_mostly tsc_unstable;
  29. /* native_sched_clock() is called before tsc_init(), so
  30. we must start with the TSC soft disabled to prevent
  31. erroneous rdtsc usage on !cpu_has_tsc processors */
  32. static int __read_mostly tsc_disabled = -1;
  33. int tsc_clocksource_reliable;
  34. /*
  35. * Scheduler clock - returns current time in nanosec units.
  36. */
  37. u64 native_sched_clock(void)
  38. {
  39. u64 this_offset;
  40. /*
  41. * Fall back to jiffies if there's no TSC available:
  42. * ( But note that we still use it if the TSC is marked
  43. * unstable. We do this because unlike Time Of Day,
  44. * the scheduler clock tolerates small errors and it's
  45. * very important for it to be as fast as the platform
  46. * can achieve it. )
  47. */
  48. if (unlikely(tsc_disabled)) {
  49. /* No locking but a rare wrong value is not a big deal: */
  50. return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
  51. }
  52. /* read the Time Stamp Counter: */
  53. rdtscll(this_offset);
  54. /* return the value in ns */
  55. return __cycles_2_ns(this_offset);
  56. }
  57. /* We need to define a real function for sched_clock, to override the
  58. weak default version */
  59. #ifdef CONFIG_PARAVIRT
  60. unsigned long long sched_clock(void)
  61. {
  62. return paravirt_sched_clock();
  63. }
  64. #else
  65. unsigned long long
  66. sched_clock(void) __attribute__((alias("native_sched_clock")));
  67. #endif
  68. unsigned long long native_read_tsc(void)
  69. {
  70. return __native_read_tsc();
  71. }
  72. EXPORT_SYMBOL(native_read_tsc);
  73. int check_tsc_unstable(void)
  74. {
  75. return tsc_unstable;
  76. }
  77. EXPORT_SYMBOL_GPL(check_tsc_unstable);
  78. #ifdef CONFIG_X86_TSC
  79. int __init notsc_setup(char *str)
  80. {
  81. pr_warn("Kernel compiled with CONFIG_X86_TSC, cannot disable TSC completely\n");
  82. tsc_disabled = 1;
  83. return 1;
  84. }
  85. #else
  86. /*
  87. * disable flag for tsc. Takes effect by clearing the TSC cpu flag
  88. * in cpu/common.c
  89. */
  90. int __init notsc_setup(char *str)
  91. {
  92. setup_clear_cpu_cap(X86_FEATURE_TSC);
  93. return 1;
  94. }
  95. #endif
  96. __setup("notsc", notsc_setup);
  97. static int no_sched_irq_time;
  98. static int __init tsc_setup(char *str)
  99. {
  100. if (!strcmp(str, "reliable"))
  101. tsc_clocksource_reliable = 1;
  102. if (!strncmp(str, "noirqtime", 9))
  103. no_sched_irq_time = 1;
  104. return 1;
  105. }
  106. __setup("tsc=", tsc_setup);
  107. #define MAX_RETRIES 5
  108. #define SMI_TRESHOLD 50000
  109. /*
  110. * Read TSC and the reference counters. Take care of SMI disturbance
  111. */
  112. static u64 tsc_read_refs(u64 *p, int hpet)
  113. {
  114. u64 t1, t2;
  115. int i;
  116. for (i = 0; i < MAX_RETRIES; i++) {
  117. t1 = get_cycles();
  118. if (hpet)
  119. *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
  120. else
  121. *p = acpi_pm_read_early();
  122. t2 = get_cycles();
  123. if ((t2 - t1) < SMI_TRESHOLD)
  124. return t2;
  125. }
  126. return ULLONG_MAX;
  127. }
  128. /*
  129. * Calculate the TSC frequency from HPET reference
  130. */
  131. static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2)
  132. {
  133. u64 tmp;
  134. if (hpet2 < hpet1)
  135. hpet2 += 0x100000000ULL;
  136. hpet2 -= hpet1;
  137. tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
  138. do_div(tmp, 1000000);
  139. do_div(deltatsc, tmp);
  140. return (unsigned long) deltatsc;
  141. }
  142. /*
  143. * Calculate the TSC frequency from PMTimer reference
  144. */
  145. static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2)
  146. {
  147. u64 tmp;
  148. if (!pm1 && !pm2)
  149. return ULONG_MAX;
  150. if (pm2 < pm1)
  151. pm2 += (u64)ACPI_PM_OVRRUN;
  152. pm2 -= pm1;
  153. tmp = pm2 * 1000000000LL;
  154. do_div(tmp, PMTMR_TICKS_PER_SEC);
  155. do_div(deltatsc, tmp);
  156. return (unsigned long) deltatsc;
  157. }
  158. #define CAL_MS 10
  159. #define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS))
  160. #define CAL_PIT_LOOPS 1000
  161. #define CAL2_MS 50
  162. #define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS))
  163. #define CAL2_PIT_LOOPS 5000
  164. /*
  165. * Try to calibrate the TSC against the Programmable
  166. * Interrupt Timer and return the frequency of the TSC
  167. * in kHz.
  168. *
  169. * Return ULONG_MAX on failure to calibrate.
  170. */
  171. static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin)
  172. {
  173. u64 tsc, t1, t2, delta;
  174. unsigned long tscmin, tscmax;
  175. int pitcnt;
  176. /* Set the Gate high, disable speaker */
  177. outb((inb(0x61) & ~0x02) | 0x01, 0x61);
  178. /*
  179. * Setup CTC channel 2* for mode 0, (interrupt on terminal
  180. * count mode), binary count. Set the latch register to 50ms
  181. * (LSB then MSB) to begin countdown.
  182. */
  183. outb(0xb0, 0x43);
  184. outb(latch & 0xff, 0x42);
  185. outb(latch >> 8, 0x42);
  186. tsc = t1 = t2 = get_cycles();
  187. pitcnt = 0;
  188. tscmax = 0;
  189. tscmin = ULONG_MAX;
  190. while ((inb(0x61) & 0x20) == 0) {
  191. t2 = get_cycles();
  192. delta = t2 - tsc;
  193. tsc = t2;
  194. if ((unsigned long) delta < tscmin)
  195. tscmin = (unsigned int) delta;
  196. if ((unsigned long) delta > tscmax)
  197. tscmax = (unsigned int) delta;
  198. pitcnt++;
  199. }
  200. /*
  201. * Sanity checks:
  202. *
  203. * If we were not able to read the PIT more than loopmin
  204. * times, then we have been hit by a massive SMI
  205. *
  206. * If the maximum is 10 times larger than the minimum,
  207. * then we got hit by an SMI as well.
  208. */
  209. if (pitcnt < loopmin || tscmax > 10 * tscmin)
  210. return ULONG_MAX;
  211. /* Calculate the PIT value */
  212. delta = t2 - t1;
  213. do_div(delta, ms);
  214. return delta;
  215. }
  216. /*
  217. * This reads the current MSB of the PIT counter, and
  218. * checks if we are running on sufficiently fast and
  219. * non-virtualized hardware.
  220. *
  221. * Our expectations are:
  222. *
  223. * - the PIT is running at roughly 1.19MHz
  224. *
  225. * - each IO is going to take about 1us on real hardware,
  226. * but we allow it to be much faster (by a factor of 10) or
  227. * _slightly_ slower (ie we allow up to a 2us read+counter
  228. * update - anything else implies a unacceptably slow CPU
  229. * or PIT for the fast calibration to work.
  230. *
  231. * - with 256 PIT ticks to read the value, we have 214us to
  232. * see the same MSB (and overhead like doing a single TSC
  233. * read per MSB value etc).
  234. *
  235. * - We're doing 2 reads per loop (LSB, MSB), and we expect
  236. * them each to take about a microsecond on real hardware.
  237. * So we expect a count value of around 100. But we'll be
  238. * generous, and accept anything over 50.
  239. *
  240. * - if the PIT is stuck, and we see *many* more reads, we
  241. * return early (and the next caller of pit_expect_msb()
  242. * then consider it a failure when they don't see the
  243. * next expected value).
  244. *
  245. * These expectations mean that we know that we have seen the
  246. * transition from one expected value to another with a fairly
  247. * high accuracy, and we didn't miss any events. We can thus
  248. * use the TSC value at the transitions to calculate a pretty
  249. * good value for the TSC frequencty.
  250. */
  251. static inline int pit_verify_msb(unsigned char val)
  252. {
  253. /* Ignore LSB */
  254. inb(0x42);
  255. return inb(0x42) == val;
  256. }
  257. static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap)
  258. {
  259. int count;
  260. u64 tsc = 0, prev_tsc = 0;
  261. for (count = 0; count < 50000; count++) {
  262. if (!pit_verify_msb(val))
  263. break;
  264. prev_tsc = tsc;
  265. tsc = get_cycles();
  266. }
  267. *deltap = get_cycles() - prev_tsc;
  268. *tscp = tsc;
  269. /*
  270. * We require _some_ success, but the quality control
  271. * will be based on the error terms on the TSC values.
  272. */
  273. return count > 5;
  274. }
  275. /*
  276. * How many MSB values do we want to see? We aim for
  277. * a maximum error rate of 500ppm (in practice the
  278. * real error is much smaller), but refuse to spend
  279. * more than 50ms on it.
  280. */
  281. #define MAX_QUICK_PIT_MS 50
  282. #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
  283. static unsigned long quick_pit_calibrate(void)
  284. {
  285. int i;
  286. u64 tsc, delta;
  287. unsigned long d1, d2;
  288. /* Set the Gate high, disable speaker */
  289. outb((inb(0x61) & ~0x02) | 0x01, 0x61);
  290. /*
  291. * Counter 2, mode 0 (one-shot), binary count
  292. *
  293. * NOTE! Mode 2 decrements by two (and then the
  294. * output is flipped each time, giving the same
  295. * final output frequency as a decrement-by-one),
  296. * so mode 0 is much better when looking at the
  297. * individual counts.
  298. */
  299. outb(0xb0, 0x43);
  300. /* Start at 0xffff */
  301. outb(0xff, 0x42);
  302. outb(0xff, 0x42);
  303. /*
  304. * The PIT starts counting at the next edge, so we
  305. * need to delay for a microsecond. The easiest way
  306. * to do that is to just read back the 16-bit counter
  307. * once from the PIT.
  308. */
  309. pit_verify_msb(0);
  310. if (pit_expect_msb(0xff, &tsc, &d1)) {
  311. for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
  312. if (!pit_expect_msb(0xff-i, &delta, &d2))
  313. break;
  314. /*
  315. * Iterate until the error is less than 500 ppm
  316. */
  317. delta -= tsc;
  318. if (d1+d2 >= delta >> 11)
  319. continue;
  320. /*
  321. * Check the PIT one more time to verify that
  322. * all TSC reads were stable wrt the PIT.
  323. *
  324. * This also guarantees serialization of the
  325. * last cycle read ('d2') in pit_expect_msb.
  326. */
  327. if (!pit_verify_msb(0xfe - i))
  328. break;
  329. goto success;
  330. }
  331. }
  332. pr_err("Fast TSC calibration failed\n");
  333. return 0;
  334. success:
  335. /*
  336. * Ok, if we get here, then we've seen the
  337. * MSB of the PIT decrement 'i' times, and the
  338. * error has shrunk to less than 500 ppm.
  339. *
  340. * As a result, we can depend on there not being
  341. * any odd delays anywhere, and the TSC reads are
  342. * reliable (within the error).
  343. *
  344. * kHz = ticks / time-in-seconds / 1000;
  345. * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
  346. * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
  347. */
  348. delta *= PIT_TICK_RATE;
  349. do_div(delta, i*256*1000);
  350. pr_info("Fast TSC calibration using PIT\n");
  351. return delta;
  352. }
  353. /**
  354. * native_calibrate_tsc - calibrate the tsc on boot
  355. */
  356. unsigned long native_calibrate_tsc(void)
  357. {
  358. u64 tsc1, tsc2, delta, ref1, ref2;
  359. unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
  360. unsigned long flags, latch, ms, fast_calibrate;
  361. int hpet = is_hpet_enabled(), i, loopmin;
  362. local_irq_save(flags);
  363. fast_calibrate = quick_pit_calibrate();
  364. local_irq_restore(flags);
  365. if (fast_calibrate)
  366. return fast_calibrate;
  367. /*
  368. * Run 5 calibration loops to get the lowest frequency value
  369. * (the best estimate). We use two different calibration modes
  370. * here:
  371. *
  372. * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
  373. * load a timeout of 50ms. We read the time right after we
  374. * started the timer and wait until the PIT count down reaches
  375. * zero. In each wait loop iteration we read the TSC and check
  376. * the delta to the previous read. We keep track of the min
  377. * and max values of that delta. The delta is mostly defined
  378. * by the IO time of the PIT access, so we can detect when a
  379. * SMI/SMM disturbance happened between the two reads. If the
  380. * maximum time is significantly larger than the minimum time,
  381. * then we discard the result and have another try.
  382. *
  383. * 2) Reference counter. If available we use the HPET or the
  384. * PMTIMER as a reference to check the sanity of that value.
  385. * We use separate TSC readouts and check inside of the
  386. * reference read for a SMI/SMM disturbance. We dicard
  387. * disturbed values here as well. We do that around the PIT
  388. * calibration delay loop as we have to wait for a certain
  389. * amount of time anyway.
  390. */
  391. /* Preset PIT loop values */
  392. latch = CAL_LATCH;
  393. ms = CAL_MS;
  394. loopmin = CAL_PIT_LOOPS;
  395. for (i = 0; i < 3; i++) {
  396. unsigned long tsc_pit_khz;
  397. /*
  398. * Read the start value and the reference count of
  399. * hpet/pmtimer when available. Then do the PIT
  400. * calibration, which will take at least 50ms, and
  401. * read the end value.
  402. */
  403. local_irq_save(flags);
  404. tsc1 = tsc_read_refs(&ref1, hpet);
  405. tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin);
  406. tsc2 = tsc_read_refs(&ref2, hpet);
  407. local_irq_restore(flags);
  408. /* Pick the lowest PIT TSC calibration so far */
  409. tsc_pit_min = min(tsc_pit_min, tsc_pit_khz);
  410. /* hpet or pmtimer available ? */
  411. if (ref1 == ref2)
  412. continue;
  413. /* Check, whether the sampling was disturbed by an SMI */
  414. if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
  415. continue;
  416. tsc2 = (tsc2 - tsc1) * 1000000LL;
  417. if (hpet)
  418. tsc2 = calc_hpet_ref(tsc2, ref1, ref2);
  419. else
  420. tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2);
  421. tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
  422. /* Check the reference deviation */
  423. delta = ((u64) tsc_pit_min) * 100;
  424. do_div(delta, tsc_ref_min);
  425. /*
  426. * If both calibration results are inside a 10% window
  427. * then we can be sure, that the calibration
  428. * succeeded. We break out of the loop right away. We
  429. * use the reference value, as it is more precise.
  430. */
  431. if (delta >= 90 && delta <= 110) {
  432. pr_info("PIT calibration matches %s. %d loops\n",
  433. hpet ? "HPET" : "PMTIMER", i + 1);
  434. return tsc_ref_min;
  435. }
  436. /*
  437. * Check whether PIT failed more than once. This
  438. * happens in virtualized environments. We need to
  439. * give the virtual PC a slightly longer timeframe for
  440. * the HPET/PMTIMER to make the result precise.
  441. */
  442. if (i == 1 && tsc_pit_min == ULONG_MAX) {
  443. latch = CAL2_LATCH;
  444. ms = CAL2_MS;
  445. loopmin = CAL2_PIT_LOOPS;
  446. }
  447. }
  448. /*
  449. * Now check the results.
  450. */
  451. if (tsc_pit_min == ULONG_MAX) {
  452. /* PIT gave no useful value */
  453. pr_warn("Unable to calibrate against PIT\n");
  454. /* We don't have an alternative source, disable TSC */
  455. if (!hpet && !ref1 && !ref2) {
  456. pr_notice("No reference (HPET/PMTIMER) available\n");
  457. return 0;
  458. }
  459. /* The alternative source failed as well, disable TSC */
  460. if (tsc_ref_min == ULONG_MAX) {
  461. pr_warn("HPET/PMTIMER calibration failed\n");
  462. return 0;
  463. }
  464. /* Use the alternative source */
  465. pr_info("using %s reference calibration\n",
  466. hpet ? "HPET" : "PMTIMER");
  467. return tsc_ref_min;
  468. }
  469. /* We don't have an alternative source, use the PIT calibration value */
  470. if (!hpet && !ref1 && !ref2) {
  471. pr_info("Using PIT calibration value\n");
  472. return tsc_pit_min;
  473. }
  474. /* The alternative source failed, use the PIT calibration value */
  475. if (tsc_ref_min == ULONG_MAX) {
  476. pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n");
  477. return tsc_pit_min;
  478. }
  479. /*
  480. * The calibration values differ too much. In doubt, we use
  481. * the PIT value as we know that there are PMTIMERs around
  482. * running at double speed. At least we let the user know:
  483. */
  484. pr_warn("PIT calibration deviates from %s: %lu %lu\n",
  485. hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
  486. pr_info("Using PIT calibration value\n");
  487. return tsc_pit_min;
  488. }
  489. int recalibrate_cpu_khz(void)
  490. {
  491. #ifndef CONFIG_SMP
  492. unsigned long cpu_khz_old = cpu_khz;
  493. if (cpu_has_tsc) {
  494. tsc_khz = x86_platform.calibrate_tsc();
  495. cpu_khz = tsc_khz;
  496. cpu_data(0).loops_per_jiffy =
  497. cpufreq_scale(cpu_data(0).loops_per_jiffy,
  498. cpu_khz_old, cpu_khz);
  499. return 0;
  500. } else
  501. return -ENODEV;
  502. #else
  503. return -ENODEV;
  504. #endif
  505. }
  506. EXPORT_SYMBOL(recalibrate_cpu_khz);
  507. /* Accelerators for sched_clock()
  508. * convert from cycles(64bits) => nanoseconds (64bits)
  509. * basic equation:
  510. * ns = cycles / (freq / ns_per_sec)
  511. * ns = cycles * (ns_per_sec / freq)
  512. * ns = cycles * (10^9 / (cpu_khz * 10^3))
  513. * ns = cycles * (10^6 / cpu_khz)
  514. *
  515. * Then we use scaling math (suggested by george@mvista.com) to get:
  516. * ns = cycles * (10^6 * SC / cpu_khz) / SC
  517. * ns = cycles * cyc2ns_scale / SC
  518. *
  519. * And since SC is a constant power of two, we can convert the div
  520. * into a shift.
  521. *
  522. * We can use khz divisor instead of mhz to keep a better precision, since
  523. * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
  524. * (mathieu.desnoyers@polymtl.ca)
  525. *
  526. * -johnstul@us.ibm.com "math is hard, lets go shopping!"
  527. */
  528. DEFINE_PER_CPU(unsigned long, cyc2ns);
  529. DEFINE_PER_CPU(unsigned long long, cyc2ns_offset);
  530. static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
  531. {
  532. unsigned long long tsc_now, ns_now, *offset;
  533. unsigned long flags, *scale;
  534. local_irq_save(flags);
  535. sched_clock_idle_sleep_event();
  536. scale = &per_cpu(cyc2ns, cpu);
  537. offset = &per_cpu(cyc2ns_offset, cpu);
  538. rdtscll(tsc_now);
  539. ns_now = __cycles_2_ns(tsc_now);
  540. if (cpu_khz) {
  541. *scale = (NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR)/cpu_khz;
  542. *offset = ns_now - mult_frac(tsc_now, *scale,
  543. (1UL << CYC2NS_SCALE_FACTOR));
  544. }
  545. sched_clock_idle_wakeup_event(0);
  546. local_irq_restore(flags);
  547. }
  548. static unsigned long long cyc2ns_suspend;
  549. void tsc_save_sched_clock_state(void)
  550. {
  551. if (!sched_clock_stable)
  552. return;
  553. cyc2ns_suspend = sched_clock();
  554. }
  555. /*
  556. * Even on processors with invariant TSC, TSC gets reset in some the
  557. * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
  558. * arbitrary value (still sync'd across cpu's) during resume from such sleep
  559. * states. To cope up with this, recompute the cyc2ns_offset for each cpu so
  560. * that sched_clock() continues from the point where it was left off during
  561. * suspend.
  562. */
  563. void tsc_restore_sched_clock_state(void)
  564. {
  565. unsigned long long offset;
  566. unsigned long flags;
  567. int cpu;
  568. if (!sched_clock_stable)
  569. return;
  570. local_irq_save(flags);
  571. __this_cpu_write(cyc2ns_offset, 0);
  572. offset = cyc2ns_suspend - sched_clock();
  573. for_each_possible_cpu(cpu)
  574. per_cpu(cyc2ns_offset, cpu) = offset;
  575. local_irq_restore(flags);
  576. }
  577. #ifdef CONFIG_CPU_FREQ
  578. /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
  579. * changes.
  580. *
  581. * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
  582. * not that important because current Opteron setups do not support
  583. * scaling on SMP anyroads.
  584. *
  585. * Should fix up last_tsc too. Currently gettimeofday in the
  586. * first tick after the change will be slightly wrong.
  587. */
  588. static unsigned int ref_freq;
  589. static unsigned long loops_per_jiffy_ref;
  590. static unsigned long tsc_khz_ref;
  591. static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
  592. void *data)
  593. {
  594. struct cpufreq_freqs *freq = data;
  595. unsigned long *lpj;
  596. if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC))
  597. return 0;
  598. lpj = &boot_cpu_data.loops_per_jiffy;
  599. #ifdef CONFIG_SMP
  600. if (!(freq->flags & CPUFREQ_CONST_LOOPS))
  601. lpj = &cpu_data(freq->cpu).loops_per_jiffy;
  602. #endif
  603. if (!ref_freq) {
  604. ref_freq = freq->old;
  605. loops_per_jiffy_ref = *lpj;
  606. tsc_khz_ref = tsc_khz;
  607. }
  608. if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
  609. (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
  610. (val == CPUFREQ_RESUMECHANGE)) {
  611. *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
  612. tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
  613. if (!(freq->flags & CPUFREQ_CONST_LOOPS))
  614. mark_tsc_unstable("cpufreq changes");
  615. }
  616. set_cyc2ns_scale(tsc_khz, freq->cpu);
  617. return 0;
  618. }
  619. static struct notifier_block time_cpufreq_notifier_block = {
  620. .notifier_call = time_cpufreq_notifier
  621. };
  622. static int __init cpufreq_tsc(void)
  623. {
  624. if (!cpu_has_tsc)
  625. return 0;
  626. if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
  627. return 0;
  628. cpufreq_register_notifier(&time_cpufreq_notifier_block,
  629. CPUFREQ_TRANSITION_NOTIFIER);
  630. return 0;
  631. }
  632. core_initcall(cpufreq_tsc);
  633. #endif /* CONFIG_CPU_FREQ */
  634. /* clocksource code */
  635. static struct clocksource clocksource_tsc;
  636. /*
  637. * We compare the TSC to the cycle_last value in the clocksource
  638. * structure to avoid a nasty time-warp. This can be observed in a
  639. * very small window right after one CPU updated cycle_last under
  640. * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
  641. * is smaller than the cycle_last reference value due to a TSC which
  642. * is slighty behind. This delta is nowhere else observable, but in
  643. * that case it results in a forward time jump in the range of hours
  644. * due to the unsigned delta calculation of the time keeping core
  645. * code, which is necessary to support wrapping clocksources like pm
  646. * timer.
  647. */
  648. static cycle_t read_tsc(struct clocksource *cs)
  649. {
  650. cycle_t ret = (cycle_t)get_cycles();
  651. return ret >= clocksource_tsc.cycle_last ?
  652. ret : clocksource_tsc.cycle_last;
  653. }
  654. static void resume_tsc(struct clocksource *cs)
  655. {
  656. clocksource_tsc.cycle_last = 0;
  657. }
  658. static struct clocksource clocksource_tsc = {
  659. .name = "tsc",
  660. .rating = 300,
  661. .read = read_tsc,
  662. .resume = resume_tsc,
  663. .mask = CLOCKSOURCE_MASK(64),
  664. .flags = CLOCK_SOURCE_IS_CONTINUOUS |
  665. CLOCK_SOURCE_MUST_VERIFY,
  666. #ifdef CONFIG_X86_64
  667. .archdata = { .vclock_mode = VCLOCK_TSC },
  668. #endif
  669. };
  670. void mark_tsc_unstable(char *reason)
  671. {
  672. if (!tsc_unstable) {
  673. tsc_unstable = 1;
  674. sched_clock_stable = 0;
  675. disable_sched_clock_irqtime();
  676. pr_info("Marking TSC unstable due to %s\n", reason);
  677. /* Change only the rating, when not registered */
  678. if (clocksource_tsc.mult)
  679. clocksource_mark_unstable(&clocksource_tsc);
  680. else {
  681. clocksource_tsc.flags |= CLOCK_SOURCE_UNSTABLE;
  682. clocksource_tsc.rating = 0;
  683. }
  684. }
  685. }
  686. EXPORT_SYMBOL_GPL(mark_tsc_unstable);
  687. static void __init check_system_tsc_reliable(void)
  688. {
  689. #ifdef CONFIG_MGEODE_LX
  690. /* RTSC counts during suspend */
  691. #define RTSC_SUSP 0x100
  692. unsigned long res_low, res_high;
  693. rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
  694. /* Geode_LX - the OLPC CPU has a very reliable TSC */
  695. if (res_low & RTSC_SUSP)
  696. tsc_clocksource_reliable = 1;
  697. #endif
  698. if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE))
  699. tsc_clocksource_reliable = 1;
  700. }
  701. /*
  702. * Make an educated guess if the TSC is trustworthy and synchronized
  703. * over all CPUs.
  704. */
  705. __cpuinit int unsynchronized_tsc(void)
  706. {
  707. if (!cpu_has_tsc || tsc_unstable)
  708. return 1;
  709. #ifdef CONFIG_SMP
  710. if (apic_is_clustered_box())
  711. return 1;
  712. #endif
  713. if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
  714. return 0;
  715. if (tsc_clocksource_reliable)
  716. return 0;
  717. /*
  718. * Intel systems are normally all synchronized.
  719. * Exceptions must mark TSC as unstable:
  720. */
  721. if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
  722. /* assume multi socket systems are not synchronized: */
  723. if (num_possible_cpus() > 1)
  724. return 1;
  725. }
  726. return 0;
  727. }
  728. static void tsc_refine_calibration_work(struct work_struct *work);
  729. static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work);
  730. /**
  731. * tsc_refine_calibration_work - Further refine tsc freq calibration
  732. * @work - ignored.
  733. *
  734. * This functions uses delayed work over a period of a
  735. * second to further refine the TSC freq value. Since this is
  736. * timer based, instead of loop based, we don't block the boot
  737. * process while this longer calibration is done.
  738. *
  739. * If there are any calibration anomalies (too many SMIs, etc),
  740. * or the refined calibration is off by 1% of the fast early
  741. * calibration, we throw out the new calibration and use the
  742. * early calibration.
  743. */
  744. static void tsc_refine_calibration_work(struct work_struct *work)
  745. {
  746. static u64 tsc_start = -1, ref_start;
  747. static int hpet;
  748. u64 tsc_stop, ref_stop, delta;
  749. unsigned long freq;
  750. /* Don't bother refining TSC on unstable systems */
  751. if (check_tsc_unstable())
  752. goto out;
  753. /*
  754. * Since the work is started early in boot, we may be
  755. * delayed the first time we expire. So set the workqueue
  756. * again once we know timers are working.
  757. */
  758. if (tsc_start == -1) {
  759. /*
  760. * Only set hpet once, to avoid mixing hardware
  761. * if the hpet becomes enabled later.
  762. */
  763. hpet = is_hpet_enabled();
  764. schedule_delayed_work(&tsc_irqwork, HZ);
  765. tsc_start = tsc_read_refs(&ref_start, hpet);
  766. return;
  767. }
  768. tsc_stop = tsc_read_refs(&ref_stop, hpet);
  769. /* hpet or pmtimer available ? */
  770. if (ref_start == ref_stop)
  771. goto out;
  772. /* Check, whether the sampling was disturbed by an SMI */
  773. if (tsc_start == ULLONG_MAX || tsc_stop == ULLONG_MAX)
  774. goto out;
  775. delta = tsc_stop - tsc_start;
  776. delta *= 1000000LL;
  777. if (hpet)
  778. freq = calc_hpet_ref(delta, ref_start, ref_stop);
  779. else
  780. freq = calc_pmtimer_ref(delta, ref_start, ref_stop);
  781. /* Make sure we're within 1% */
  782. if (abs(tsc_khz - freq) > tsc_khz/100)
  783. goto out;
  784. tsc_khz = freq;
  785. pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n",
  786. (unsigned long)tsc_khz / 1000,
  787. (unsigned long)tsc_khz % 1000);
  788. out:
  789. clocksource_register_khz(&clocksource_tsc, tsc_khz);
  790. }
  791. static int __init init_tsc_clocksource(void)
  792. {
  793. if (!cpu_has_tsc || tsc_disabled > 0 || !tsc_khz)
  794. return 0;
  795. if (tsc_clocksource_reliable)
  796. clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
  797. /* lower the rating if we already know its unstable: */
  798. if (check_tsc_unstable()) {
  799. clocksource_tsc.rating = 0;
  800. clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
  801. }
  802. /*
  803. * Trust the results of the earlier calibration on systems
  804. * exporting a reliable TSC.
  805. */
  806. if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) {
  807. clocksource_register_khz(&clocksource_tsc, tsc_khz);
  808. return 0;
  809. }
  810. schedule_delayed_work(&tsc_irqwork, 0);
  811. return 0;
  812. }
  813. /*
  814. * We use device_initcall here, to ensure we run after the hpet
  815. * is fully initialized, which may occur at fs_initcall time.
  816. */
  817. device_initcall(init_tsc_clocksource);
  818. void __init tsc_init(void)
  819. {
  820. u64 lpj;
  821. int cpu;
  822. x86_init.timers.tsc_pre_init();
  823. if (!cpu_has_tsc)
  824. return;
  825. tsc_khz = x86_platform.calibrate_tsc();
  826. cpu_khz = tsc_khz;
  827. if (!tsc_khz) {
  828. mark_tsc_unstable("could not calculate TSC khz");
  829. return;
  830. }
  831. pr_info("Detected %lu.%03lu MHz processor\n",
  832. (unsigned long)cpu_khz / 1000,
  833. (unsigned long)cpu_khz % 1000);
  834. /*
  835. * Secondary CPUs do not run through tsc_init(), so set up
  836. * all the scale factors for all CPUs, assuming the same
  837. * speed as the bootup CPU. (cpufreq notifiers will fix this
  838. * up if their speed diverges)
  839. */
  840. for_each_possible_cpu(cpu)
  841. set_cyc2ns_scale(cpu_khz, cpu);
  842. if (tsc_disabled > 0)
  843. return;
  844. /* now allow native_sched_clock() to use rdtsc */
  845. tsc_disabled = 0;
  846. if (!no_sched_irq_time)
  847. enable_sched_clock_irqtime();
  848. lpj = ((u64)tsc_khz * 1000);
  849. do_div(lpj, HZ);
  850. lpj_fine = lpj;
  851. use_tsc_delay();
  852. if (unsynchronized_tsc())
  853. mark_tsc_unstable("TSCs unsynchronized");
  854. check_system_tsc_reliable();
  855. }
  856. #ifdef CONFIG_SMP
  857. /*
  858. * If we have a constant TSC and are using the TSC for the delay loop,
  859. * we can skip clock calibration if another cpu in the same socket has already
  860. * been calibrated. This assumes that CONSTANT_TSC applies to all
  861. * cpus in the socket - this should be a safe assumption.
  862. */
  863. unsigned long __cpuinit calibrate_delay_is_known(void)
  864. {
  865. int i, cpu = smp_processor_id();
  866. if (!tsc_disabled && !cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC))
  867. return 0;
  868. for_each_online_cpu(i)
  869. if (cpu_data(i).phys_proc_id == cpu_data(cpu).phys_proc_id)
  870. return cpu_data(i).loops_per_jiffy;
  871. return 0;
  872. }
  873. #endif