at91sam9263.dtsi 11 KB

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  1. /*
  2. * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC
  3. *
  4. * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  5. *
  6. * Licensed under GPLv2 only.
  7. */
  8. /include/ "skeleton.dtsi"
  9. / {
  10. model = "Atmel AT91SAM9263 family SoC";
  11. compatible = "atmel,at91sam9263";
  12. interrupt-parent = <&aic>;
  13. aliases {
  14. serial0 = &dbgu;
  15. serial1 = &usart0;
  16. serial2 = &usart1;
  17. serial3 = &usart2;
  18. gpio0 = &pioA;
  19. gpio1 = &pioB;
  20. gpio2 = &pioC;
  21. gpio3 = &pioD;
  22. gpio4 = &pioE;
  23. tcb0 = &tcb0;
  24. i2c0 = &i2c0;
  25. ssc0 = &ssc0;
  26. ssc1 = &ssc1;
  27. };
  28. cpus {
  29. cpu@0 {
  30. compatible = "arm,arm926ejs";
  31. };
  32. };
  33. memory {
  34. reg = <0x20000000 0x08000000>;
  35. };
  36. ahb {
  37. compatible = "simple-bus";
  38. #address-cells = <1>;
  39. #size-cells = <1>;
  40. ranges;
  41. apb {
  42. compatible = "simple-bus";
  43. #address-cells = <1>;
  44. #size-cells = <1>;
  45. ranges;
  46. aic: interrupt-controller@fffff000 {
  47. #interrupt-cells = <3>;
  48. compatible = "atmel,at91rm9200-aic";
  49. interrupt-controller;
  50. reg = <0xfffff000 0x200>;
  51. atmel,external-irqs = <30 31>;
  52. };
  53. pmc: pmc@fffffc00 {
  54. compatible = "atmel,at91rm9200-pmc";
  55. reg = <0xfffffc00 0x100>;
  56. };
  57. ramc: ramc@ffffe200 {
  58. compatible = "atmel,at91sam9260-sdramc";
  59. reg = <0xffffe200 0x200
  60. 0xffffe800 0x200>;
  61. };
  62. pit: timer@fffffd30 {
  63. compatible = "atmel,at91sam9260-pit";
  64. reg = <0xfffffd30 0xf>;
  65. interrupts = <1 4 7>;
  66. };
  67. tcb0: timer@fff7c000 {
  68. compatible = "atmel,at91rm9200-tcb";
  69. reg = <0xfff7c000 0x100>;
  70. interrupts = <19 4 0>;
  71. };
  72. rstc@fffffd00 {
  73. compatible = "atmel,at91sam9260-rstc";
  74. reg = <0xfffffd00 0x10>;
  75. };
  76. shdwc@fffffd10 {
  77. compatible = "atmel,at91sam9260-shdwc";
  78. reg = <0xfffffd10 0x10>;
  79. };
  80. pinctrl@fffff200 {
  81. #address-cells = <1>;
  82. #size-cells = <1>;
  83. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  84. ranges = <0xfffff200 0xfffff200 0xa00>;
  85. atmel,mux-mask = <
  86. /* A B */
  87. 0xfffffffb 0xffffe07f /* pioA */
  88. 0x0007ffff 0x39072fff /* pioB */
  89. 0xffffffff 0x3ffffff8 /* pioC */
  90. 0xfffffbff 0xffffffff /* pioD */
  91. 0xffe00fff 0xfbfcff00 /* pioE */
  92. >;
  93. /* shared pinctrl settings */
  94. dbgu {
  95. pinctrl_dbgu: dbgu-0 {
  96. atmel,pins =
  97. <2 30 0x1 0x0 /* PC30 periph A */
  98. 2 31 0x1 0x1>; /* PC31 periph with pullup */
  99. };
  100. };
  101. usart0 {
  102. pinctrl_usart0: usart0-0 {
  103. atmel,pins =
  104. <0 26 0x1 0x1 /* PA26 periph A with pullup */
  105. 0 27 0x1 0x0>; /* PA27 periph A */
  106. };
  107. pinctrl_usart0_rts: usart0_rts-0 {
  108. atmel,pins =
  109. <0 28 0x1 0x0>; /* PA28 periph A */
  110. };
  111. pinctrl_usart0_cts: usart0_cts-0 {
  112. atmel,pins =
  113. <0 29 0x1 0x0>; /* PA29 periph A */
  114. };
  115. };
  116. usart1 {
  117. pinctrl_usart1: usart1-0 {
  118. atmel,pins =
  119. <3 0 0x1 0x1 /* PD0 periph A with pullup */
  120. 3 1 0x1 0x0>; /* PD1 periph A */
  121. };
  122. pinctrl_usart1_rts: usart1_rts-0 {
  123. atmel,pins =
  124. <3 7 0x2 0x0>; /* PD7 periph B */
  125. };
  126. pinctrl_usart1_cts: usart1_cts-0 {
  127. atmel,pins =
  128. <3 8 0x2 0x0>; /* PD8 periph B */
  129. };
  130. };
  131. usart2 {
  132. pinctrl_usart2: usart2-0 {
  133. atmel,pins =
  134. <3 2 0x1 0x1 /* PD2 periph A with pullup */
  135. 3 3 0x1 0x0>; /* PD3 periph A */
  136. };
  137. pinctrl_usart2_rts: usart2_rts-0 {
  138. atmel,pins =
  139. <3 5 0x2 0x0>; /* PD5 periph B */
  140. };
  141. pinctrl_usart2_cts: usart2_cts-0 {
  142. atmel,pins =
  143. <4 6 0x2 0x0>; /* PD6 periph B */
  144. };
  145. };
  146. nand {
  147. pinctrl_nand: nand-0 {
  148. atmel,pins =
  149. <0 22 0x0 0x1 /* PA22 gpio RDY pin pull_up*/
  150. 3 15 0x0 0x1>; /* PD15 gpio enable pin pull_up */
  151. };
  152. };
  153. macb {
  154. pinctrl_macb_rmii: macb_rmii-0 {
  155. atmel,pins =
  156. <2 25 0x2 0x0 /* PC25 periph B */
  157. 4 21 0x1 0x0 /* PE21 periph A */
  158. 4 23 0x1 0x0 /* PE23 periph A */
  159. 4 24 0x1 0x0 /* PE24 periph A */
  160. 4 25 0x1 0x0 /* PE25 periph A */
  161. 4 26 0x1 0x0 /* PE26 periph A */
  162. 4 27 0x1 0x0 /* PE27 periph A */
  163. 4 28 0x1 0x0 /* PE28 periph A */
  164. 4 29 0x1 0x0 /* PE29 periph A */
  165. 4 30 0x1 0x0>; /* PE30 periph A */
  166. };
  167. pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
  168. atmel,pins =
  169. <2 20 0x2 0x0 /* PC20 periph B */
  170. 2 21 0x2 0x0 /* PC21 periph B */
  171. 2 22 0x2 0x0 /* PC22 periph B */
  172. 2 23 0x2 0x0 /* PC23 periph B */
  173. 2 24 0x2 0x0 /* PC24 periph B */
  174. 2 25 0x2 0x0 /* PC25 periph B */
  175. 2 27 0x2 0x0 /* PC27 periph B */
  176. 4 22 0x2 0x0>; /* PE22 periph B */
  177. };
  178. };
  179. mmc0 {
  180. pinctrl_mmc0_clk: mmc0_clk-0 {
  181. atmel,pins =
  182. <0 12 0x1 0x0>; /* PA12 periph A */
  183. };
  184. pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
  185. atmel,pins =
  186. <0 1 0x1 0x1 /* PA1 periph A with pullup */
  187. 0 0 0x1 0x1>; /* PA0 periph A with pullup */
  188. };
  189. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  190. atmel,pins =
  191. <0 3 0x1 0x1 /* PA3 periph A with pullup */
  192. 0 4 0x1 0x1 /* PA4 periph A with pullup */
  193. 0 5 0x1 0x1>; /* PA5 periph A with pullup */
  194. };
  195. pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
  196. atmel,pins =
  197. <0 16 0x1 0x1 /* PA16 periph A with pullup */
  198. 0 17 0x1 0x1>; /* PA17 periph A with pullup */
  199. };
  200. pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
  201. atmel,pins =
  202. <0 18 0x1 0x1 /* PA18 periph A with pullup */
  203. 0 19 0x1 0x1 /* PA19 periph A with pullup */
  204. 0 20 0x1 0x1>; /* PA20 periph A with pullup */
  205. };
  206. };
  207. mmc1 {
  208. pinctrl_mmc1_clk: mmc1_clk-0 {
  209. atmel,pins =
  210. <0 6 0x1 0x0>; /* PA6 periph A */
  211. };
  212. pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 {
  213. atmel,pins =
  214. <0 7 0x1 0x1 /* PA7 periph A with pullup */
  215. 0 8 0x1 0x1>; /* PA8 periph A with pullup */
  216. };
  217. pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
  218. atmel,pins =
  219. <0 9 0x1 0x1 /* PA9 periph A with pullup */
  220. 0 10 0x1 0x1 /* PA10 periph A with pullup */
  221. 0 11 0x1 0x1>; /* PA11 periph A with pullup */
  222. };
  223. pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 {
  224. atmel,pins =
  225. <0 21 0x1 0x1 /* PA21 periph A with pullup */
  226. 0 22 0x1 0x1>; /* PA22 periph A with pullup */
  227. };
  228. pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 {
  229. atmel,pins =
  230. <0 23 0x1 0x1 /* PA23 periph A with pullup */
  231. 0 24 0x1 0x1 /* PA24 periph A with pullup */
  232. 0 25 0x1 0x1>; /* PA25 periph A with pullup */
  233. };
  234. };
  235. pioA: gpio@fffff200 {
  236. compatible = "atmel,at91rm9200-gpio";
  237. reg = <0xfffff200 0x200>;
  238. interrupts = <2 4 1>;
  239. #gpio-cells = <2>;
  240. gpio-controller;
  241. interrupt-controller;
  242. #interrupt-cells = <2>;
  243. };
  244. pioB: gpio@fffff400 {
  245. compatible = "atmel,at91rm9200-gpio";
  246. reg = <0xfffff400 0x200>;
  247. interrupts = <3 4 1>;
  248. #gpio-cells = <2>;
  249. gpio-controller;
  250. interrupt-controller;
  251. #interrupt-cells = <2>;
  252. };
  253. pioC: gpio@fffff600 {
  254. compatible = "atmel,at91rm9200-gpio";
  255. reg = <0xfffff600 0x200>;
  256. interrupts = <4 4 1>;
  257. #gpio-cells = <2>;
  258. gpio-controller;
  259. interrupt-controller;
  260. #interrupt-cells = <2>;
  261. };
  262. pioD: gpio@fffff800 {
  263. compatible = "atmel,at91rm9200-gpio";
  264. reg = <0xfffff800 0x200>;
  265. interrupts = <4 4 1>;
  266. #gpio-cells = <2>;
  267. gpio-controller;
  268. interrupt-controller;
  269. #interrupt-cells = <2>;
  270. };
  271. pioE: gpio@fffffa00 {
  272. compatible = "atmel,at91rm9200-gpio";
  273. reg = <0xfffffa00 0x200>;
  274. interrupts = <4 4 1>;
  275. #gpio-cells = <2>;
  276. gpio-controller;
  277. interrupt-controller;
  278. #interrupt-cells = <2>;
  279. };
  280. };
  281. dbgu: serial@ffffee00 {
  282. compatible = "atmel,at91sam9260-usart";
  283. reg = <0xffffee00 0x200>;
  284. interrupts = <1 4 7>;
  285. pinctrl-names = "default";
  286. pinctrl-0 = <&pinctrl_dbgu>;
  287. status = "disabled";
  288. };
  289. usart0: serial@fff8c000 {
  290. compatible = "atmel,at91sam9260-usart";
  291. reg = <0xfff8c000 0x200>;
  292. interrupts = <7 4 5>;
  293. atmel,use-dma-rx;
  294. atmel,use-dma-tx;
  295. pinctrl-names = "default";
  296. pinctrl-0 = <&pinctrl_usart0>;
  297. status = "disabled";
  298. };
  299. usart1: serial@fff90000 {
  300. compatible = "atmel,at91sam9260-usart";
  301. reg = <0xfff90000 0x200>;
  302. interrupts = <8 4 5>;
  303. atmel,use-dma-rx;
  304. atmel,use-dma-tx;
  305. pinctrl-names = "default";
  306. pinctrl-0 = <&pinctrl_usart1>;
  307. status = "disabled";
  308. };
  309. usart2: serial@fff94000 {
  310. compatible = "atmel,at91sam9260-usart";
  311. reg = <0xfff94000 0x200>;
  312. interrupts = <9 4 5>;
  313. atmel,use-dma-rx;
  314. atmel,use-dma-tx;
  315. pinctrl-names = "default";
  316. pinctrl-0 = <&pinctrl_usart2>;
  317. status = "disabled";
  318. };
  319. ssc0: ssc@fff98000 {
  320. compatible = "atmel,at91rm9200-ssc";
  321. reg = <0xfff98000 0x4000>;
  322. interrupts = <16 4 5>;
  323. status = "disabled";
  324. };
  325. ssc1: ssc@fff9c000 {
  326. compatible = "atmel,at91rm9200-ssc";
  327. reg = <0xfff9c000 0x4000>;
  328. interrupts = <17 4 5>;
  329. status = "disabled";
  330. };
  331. macb0: ethernet@fffbc000 {
  332. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  333. reg = <0xfffbc000 0x100>;
  334. interrupts = <21 4 3>;
  335. pinctrl-names = "default";
  336. pinctrl-0 = <&pinctrl_macb_rmii>;
  337. status = "disabled";
  338. };
  339. usb1: gadget@fff78000 {
  340. compatible = "atmel,at91rm9200-udc";
  341. reg = <0xfff78000 0x4000>;
  342. interrupts = <24 4 2>;
  343. status = "disabled";
  344. };
  345. i2c0: i2c@fff88000 {
  346. compatible = "atmel,at91sam9263-i2c";
  347. reg = <0xfff88000 0x100>;
  348. interrupts = <13 4 6>;
  349. #address-cells = <1>;
  350. #size-cells = <0>;
  351. status = "disabled";
  352. };
  353. mmc0: mmc@fff80000 {
  354. compatible = "atmel,hsmci";
  355. reg = <0xfff80000 0x600>;
  356. interrupts = <10 4 0>;
  357. #address-cells = <1>;
  358. #size-cells = <0>;
  359. status = "disabled";
  360. };
  361. mmc1: mmc@fff84000 {
  362. compatible = "atmel,hsmci";
  363. reg = <0xfff84000 0x600>;
  364. interrupts = <11 4 0>;
  365. #address-cells = <1>;
  366. #size-cells = <0>;
  367. status = "disabled";
  368. };
  369. watchdog@fffffd40 {
  370. compatible = "atmel,at91sam9260-wdt";
  371. reg = <0xfffffd40 0x10>;
  372. status = "disabled";
  373. };
  374. };
  375. nand0: nand@40000000 {
  376. compatible = "atmel,at91rm9200-nand";
  377. #address-cells = <1>;
  378. #size-cells = <1>;
  379. reg = <0x40000000 0x10000000
  380. 0xffffe000 0x200
  381. >;
  382. atmel,nand-addr-offset = <21>;
  383. atmel,nand-cmd-offset = <22>;
  384. pinctrl-names = "default";
  385. pinctrl-0 = <&pinctrl_nand>;
  386. gpios = <&pioA 22 0
  387. &pioD 15 0
  388. 0
  389. >;
  390. status = "disabled";
  391. };
  392. usb0: ohci@00a00000 {
  393. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  394. reg = <0x00a00000 0x100000>;
  395. interrupts = <29 4 2>;
  396. status = "disabled";
  397. };
  398. };
  399. i2c@0 {
  400. compatible = "i2c-gpio";
  401. gpios = <&pioB 4 0 /* sda */
  402. &pioB 5 0 /* scl */
  403. >;
  404. i2c-gpio,sda-open-drain;
  405. i2c-gpio,scl-open-drain;
  406. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  407. #address-cells = <1>;
  408. #size-cells = <0>;
  409. status = "disabled";
  410. };
  411. };