hw_breakpoint.c 22 KB

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  1. /*
  2. * This program is free software; you can redistribute it and/or modify
  3. * it under the terms of the GNU General Public License version 2 as
  4. * published by the Free Software Foundation.
  5. *
  6. * This program is distributed in the hope that it will be useful,
  7. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  8. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  9. * GNU General Public License for more details.
  10. *
  11. * You should have received a copy of the GNU General Public License
  12. * along with this program; if not, write to the Free Software
  13. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  14. *
  15. * Copyright (C) 2009, 2010 ARM Limited
  16. *
  17. * Author: Will Deacon <will.deacon@arm.com>
  18. */
  19. /*
  20. * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
  21. * using the CPU's debug registers.
  22. */
  23. #define pr_fmt(fmt) "hw-breakpoint: " fmt
  24. #include <linux/errno.h>
  25. #include <linux/hardirq.h>
  26. #include <linux/perf_event.h>
  27. #include <linux/hw_breakpoint.h>
  28. #include <linux/smp.h>
  29. #include <asm/cacheflush.h>
  30. #include <asm/cputype.h>
  31. #include <asm/current.h>
  32. #include <asm/hw_breakpoint.h>
  33. #include <asm/kdebug.h>
  34. #include <asm/system.h>
  35. #include <asm/traps.h>
  36. /* Breakpoint currently in use for each BRP. */
  37. static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]);
  38. /* Watchpoint currently in use for each WRP. */
  39. static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]);
  40. /* Number of BRP/WRP registers on this CPU. */
  41. static int core_num_brps;
  42. static int core_num_reserved_brps;
  43. static int core_num_wrps;
  44. /* Debug architecture version. */
  45. static u8 debug_arch;
  46. /* Maximum supported watchpoint length. */
  47. static u8 max_watchpoint_len;
  48. #define READ_WB_REG_CASE(OP2, M, VAL) \
  49. case ((OP2 << 4) + M): \
  50. ARM_DBG_READ(c ## M, OP2, VAL); \
  51. break
  52. #define WRITE_WB_REG_CASE(OP2, M, VAL) \
  53. case ((OP2 << 4) + M): \
  54. ARM_DBG_WRITE(c ## M, OP2, VAL);\
  55. break
  56. #define GEN_READ_WB_REG_CASES(OP2, VAL) \
  57. READ_WB_REG_CASE(OP2, 0, VAL); \
  58. READ_WB_REG_CASE(OP2, 1, VAL); \
  59. READ_WB_REG_CASE(OP2, 2, VAL); \
  60. READ_WB_REG_CASE(OP2, 3, VAL); \
  61. READ_WB_REG_CASE(OP2, 4, VAL); \
  62. READ_WB_REG_CASE(OP2, 5, VAL); \
  63. READ_WB_REG_CASE(OP2, 6, VAL); \
  64. READ_WB_REG_CASE(OP2, 7, VAL); \
  65. READ_WB_REG_CASE(OP2, 8, VAL); \
  66. READ_WB_REG_CASE(OP2, 9, VAL); \
  67. READ_WB_REG_CASE(OP2, 10, VAL); \
  68. READ_WB_REG_CASE(OP2, 11, VAL); \
  69. READ_WB_REG_CASE(OP2, 12, VAL); \
  70. READ_WB_REG_CASE(OP2, 13, VAL); \
  71. READ_WB_REG_CASE(OP2, 14, VAL); \
  72. READ_WB_REG_CASE(OP2, 15, VAL)
  73. #define GEN_WRITE_WB_REG_CASES(OP2, VAL) \
  74. WRITE_WB_REG_CASE(OP2, 0, VAL); \
  75. WRITE_WB_REG_CASE(OP2, 1, VAL); \
  76. WRITE_WB_REG_CASE(OP2, 2, VAL); \
  77. WRITE_WB_REG_CASE(OP2, 3, VAL); \
  78. WRITE_WB_REG_CASE(OP2, 4, VAL); \
  79. WRITE_WB_REG_CASE(OP2, 5, VAL); \
  80. WRITE_WB_REG_CASE(OP2, 6, VAL); \
  81. WRITE_WB_REG_CASE(OP2, 7, VAL); \
  82. WRITE_WB_REG_CASE(OP2, 8, VAL); \
  83. WRITE_WB_REG_CASE(OP2, 9, VAL); \
  84. WRITE_WB_REG_CASE(OP2, 10, VAL); \
  85. WRITE_WB_REG_CASE(OP2, 11, VAL); \
  86. WRITE_WB_REG_CASE(OP2, 12, VAL); \
  87. WRITE_WB_REG_CASE(OP2, 13, VAL); \
  88. WRITE_WB_REG_CASE(OP2, 14, VAL); \
  89. WRITE_WB_REG_CASE(OP2, 15, VAL)
  90. static u32 read_wb_reg(int n)
  91. {
  92. u32 val = 0;
  93. switch (n) {
  94. GEN_READ_WB_REG_CASES(ARM_OP2_BVR, val);
  95. GEN_READ_WB_REG_CASES(ARM_OP2_BCR, val);
  96. GEN_READ_WB_REG_CASES(ARM_OP2_WVR, val);
  97. GEN_READ_WB_REG_CASES(ARM_OP2_WCR, val);
  98. default:
  99. pr_warning("attempt to read from unknown breakpoint "
  100. "register %d\n", n);
  101. }
  102. return val;
  103. }
  104. static void write_wb_reg(int n, u32 val)
  105. {
  106. switch (n) {
  107. GEN_WRITE_WB_REG_CASES(ARM_OP2_BVR, val);
  108. GEN_WRITE_WB_REG_CASES(ARM_OP2_BCR, val);
  109. GEN_WRITE_WB_REG_CASES(ARM_OP2_WVR, val);
  110. GEN_WRITE_WB_REG_CASES(ARM_OP2_WCR, val);
  111. default:
  112. pr_warning("attempt to write to unknown breakpoint "
  113. "register %d\n", n);
  114. }
  115. isb();
  116. }
  117. /* Determine debug architecture. */
  118. static u8 get_debug_arch(void)
  119. {
  120. u32 didr;
  121. /* Do we implement the extended CPUID interface? */
  122. if (((read_cpuid_id() >> 16) & 0xf) != 0xf) {
  123. pr_warning("CPUID feature registers not supported. "
  124. "Assuming v6 debug is present.\n");
  125. return ARM_DEBUG_ARCH_V6;
  126. }
  127. ARM_DBG_READ(c0, 0, didr);
  128. return (didr >> 16) & 0xf;
  129. }
  130. u8 arch_get_debug_arch(void)
  131. {
  132. return debug_arch;
  133. }
  134. /* Determine number of BRP register available. */
  135. static int get_num_brp_resources(void)
  136. {
  137. u32 didr;
  138. ARM_DBG_READ(c0, 0, didr);
  139. return ((didr >> 24) & 0xf) + 1;
  140. }
  141. /* Does this core support mismatch breakpoints? */
  142. static int core_has_mismatch_brps(void)
  143. {
  144. return (get_debug_arch() >= ARM_DEBUG_ARCH_V7_ECP14 &&
  145. get_num_brp_resources() > 1);
  146. }
  147. /* Determine number of usable WRPs available. */
  148. static int get_num_wrps(void)
  149. {
  150. /*
  151. * FIXME: When a watchpoint fires, the only way to work out which
  152. * watchpoint it was is by disassembling the faulting instruction
  153. * and working out the address of the memory access.
  154. *
  155. * Furthermore, we can only do this if the watchpoint was precise
  156. * since imprecise watchpoints prevent us from calculating register
  157. * based addresses.
  158. *
  159. * Providing we have more than 1 breakpoint register, we only report
  160. * a single watchpoint register for the time being. This way, we always
  161. * know which watchpoint fired. In the future we can either add a
  162. * disassembler and address generation emulator, or we can insert a
  163. * check to see if the DFAR is set on watchpoint exception entry
  164. * [the ARM ARM states that the DFAR is UNKNOWN, but experience shows
  165. * that it is set on some implementations].
  166. */
  167. #if 0
  168. int wrps;
  169. u32 didr;
  170. ARM_DBG_READ(c0, 0, didr);
  171. wrps = ((didr >> 28) & 0xf) + 1;
  172. #endif
  173. int wrps = 1;
  174. if (core_has_mismatch_brps() && wrps >= get_num_brp_resources())
  175. wrps = get_num_brp_resources() - 1;
  176. return wrps;
  177. }
  178. /* We reserve one breakpoint for each watchpoint. */
  179. static int get_num_reserved_brps(void)
  180. {
  181. if (core_has_mismatch_brps())
  182. return get_num_wrps();
  183. return 0;
  184. }
  185. /* Determine number of usable BRPs available. */
  186. static int get_num_brps(void)
  187. {
  188. int brps = get_num_brp_resources();
  189. if (core_has_mismatch_brps())
  190. brps -= get_num_reserved_brps();
  191. return brps;
  192. }
  193. int hw_breakpoint_slots(int type)
  194. {
  195. /*
  196. * We can be called early, so don't rely on
  197. * our static variables being initialised.
  198. */
  199. switch (type) {
  200. case TYPE_INST:
  201. return get_num_brps();
  202. case TYPE_DATA:
  203. return get_num_wrps();
  204. default:
  205. pr_warning("unknown slot type: %d\n", type);
  206. return 0;
  207. }
  208. }
  209. /*
  210. * In order to access the breakpoint/watchpoint control registers,
  211. * we must be running in debug monitor mode. Unfortunately, we can
  212. * be put into halting debug mode at any time by an external debugger
  213. * but there is nothing we can do to prevent that.
  214. */
  215. static int enable_monitor_mode(void)
  216. {
  217. u32 dscr;
  218. int ret = 0;
  219. ARM_DBG_READ(c1, 0, dscr);
  220. /* Ensure that halting mode is disabled. */
  221. if (WARN_ONCE(dscr & ARM_DSCR_HDBGEN, "halting debug mode enabled."
  222. "Unable to access hardware resources.")) {
  223. ret = -EPERM;
  224. goto out;
  225. }
  226. /* Write to the corresponding DSCR. */
  227. switch (debug_arch) {
  228. case ARM_DEBUG_ARCH_V6:
  229. case ARM_DEBUG_ARCH_V6_1:
  230. ARM_DBG_WRITE(c1, 0, (dscr | ARM_DSCR_MDBGEN));
  231. break;
  232. case ARM_DEBUG_ARCH_V7_ECP14:
  233. ARM_DBG_WRITE(c2, 2, (dscr | ARM_DSCR_MDBGEN));
  234. break;
  235. default:
  236. ret = -ENODEV;
  237. goto out;
  238. }
  239. /* Check that the write made it through. */
  240. ARM_DBG_READ(c1, 0, dscr);
  241. if (WARN_ONCE(!(dscr & ARM_DSCR_MDBGEN),
  242. "failed to enable monitor mode.")) {
  243. ret = -EPERM;
  244. }
  245. out:
  246. return ret;
  247. }
  248. /*
  249. * Check if 8-bit byte-address select is available.
  250. * This clobbers WRP 0.
  251. */
  252. static u8 get_max_wp_len(void)
  253. {
  254. u32 ctrl_reg;
  255. struct arch_hw_breakpoint_ctrl ctrl;
  256. u8 size = 4;
  257. if (debug_arch < ARM_DEBUG_ARCH_V7_ECP14)
  258. goto out;
  259. if (enable_monitor_mode())
  260. goto out;
  261. memset(&ctrl, 0, sizeof(ctrl));
  262. ctrl.len = ARM_BREAKPOINT_LEN_8;
  263. ctrl_reg = encode_ctrl_reg(ctrl);
  264. write_wb_reg(ARM_BASE_WVR, 0);
  265. write_wb_reg(ARM_BASE_WCR, ctrl_reg);
  266. if ((read_wb_reg(ARM_BASE_WCR) & ctrl_reg) == ctrl_reg)
  267. size = 8;
  268. out:
  269. return size;
  270. }
  271. u8 arch_get_max_wp_len(void)
  272. {
  273. return max_watchpoint_len;
  274. }
  275. /*
  276. * Handler for reactivating a suspended watchpoint when the single
  277. * step `mismatch' breakpoint is triggered.
  278. */
  279. static void wp_single_step_handler(struct perf_event *bp, int unused,
  280. struct perf_sample_data *data,
  281. struct pt_regs *regs)
  282. {
  283. perf_event_enable(counter_arch_bp(bp)->suspended_wp);
  284. unregister_hw_breakpoint(bp);
  285. }
  286. static int bp_is_single_step(struct perf_event *bp)
  287. {
  288. return bp->overflow_handler == wp_single_step_handler;
  289. }
  290. /*
  291. * Install a perf counter breakpoint.
  292. */
  293. int arch_install_hw_breakpoint(struct perf_event *bp)
  294. {
  295. struct arch_hw_breakpoint *info = counter_arch_bp(bp);
  296. struct perf_event **slot, **slots;
  297. int i, max_slots, ctrl_base, val_base, ret = 0;
  298. /* Ensure that we are in monitor mode and halting mode is disabled. */
  299. ret = enable_monitor_mode();
  300. if (ret)
  301. goto out;
  302. if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
  303. /* Breakpoint */
  304. ctrl_base = ARM_BASE_BCR;
  305. val_base = ARM_BASE_BVR;
  306. slots = __get_cpu_var(bp_on_reg);
  307. max_slots = core_num_brps;
  308. if (bp_is_single_step(bp)) {
  309. info->ctrl.mismatch = 1;
  310. i = max_slots;
  311. slots[i] = bp;
  312. goto setup;
  313. }
  314. } else {
  315. /* Watchpoint */
  316. ctrl_base = ARM_BASE_WCR;
  317. val_base = ARM_BASE_WVR;
  318. slots = __get_cpu_var(wp_on_reg);
  319. max_slots = core_num_wrps;
  320. }
  321. for (i = 0; i < max_slots; ++i) {
  322. slot = &slots[i];
  323. if (!*slot) {
  324. *slot = bp;
  325. break;
  326. }
  327. }
  328. if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot")) {
  329. ret = -EBUSY;
  330. goto out;
  331. }
  332. setup:
  333. /* Setup the address register. */
  334. write_wb_reg(val_base + i, info->address);
  335. /* Setup the control register. */
  336. write_wb_reg(ctrl_base + i, encode_ctrl_reg(info->ctrl) | 0x1);
  337. out:
  338. return ret;
  339. }
  340. void arch_uninstall_hw_breakpoint(struct perf_event *bp)
  341. {
  342. struct arch_hw_breakpoint *info = counter_arch_bp(bp);
  343. struct perf_event **slot, **slots;
  344. int i, max_slots, base;
  345. if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
  346. /* Breakpoint */
  347. base = ARM_BASE_BCR;
  348. slots = __get_cpu_var(bp_on_reg);
  349. max_slots = core_num_brps;
  350. if (bp_is_single_step(bp)) {
  351. i = max_slots;
  352. slots[i] = NULL;
  353. goto reset;
  354. }
  355. } else {
  356. /* Watchpoint */
  357. base = ARM_BASE_WCR;
  358. slots = __get_cpu_var(wp_on_reg);
  359. max_slots = core_num_wrps;
  360. }
  361. /* Remove the breakpoint. */
  362. for (i = 0; i < max_slots; ++i) {
  363. slot = &slots[i];
  364. if (*slot == bp) {
  365. *slot = NULL;
  366. break;
  367. }
  368. }
  369. if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot"))
  370. return;
  371. reset:
  372. /* Reset the control register. */
  373. write_wb_reg(base + i, 0);
  374. }
  375. static int get_hbp_len(u8 hbp_len)
  376. {
  377. unsigned int len_in_bytes = 0;
  378. switch (hbp_len) {
  379. case ARM_BREAKPOINT_LEN_1:
  380. len_in_bytes = 1;
  381. break;
  382. case ARM_BREAKPOINT_LEN_2:
  383. len_in_bytes = 2;
  384. break;
  385. case ARM_BREAKPOINT_LEN_4:
  386. len_in_bytes = 4;
  387. break;
  388. case ARM_BREAKPOINT_LEN_8:
  389. len_in_bytes = 8;
  390. break;
  391. }
  392. return len_in_bytes;
  393. }
  394. /*
  395. * Check whether bp virtual address is in kernel space.
  396. */
  397. int arch_check_bp_in_kernelspace(struct perf_event *bp)
  398. {
  399. unsigned int len;
  400. unsigned long va;
  401. struct arch_hw_breakpoint *info = counter_arch_bp(bp);
  402. va = info->address;
  403. len = get_hbp_len(info->ctrl.len);
  404. return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
  405. }
  406. /*
  407. * Extract generic type and length encodings from an arch_hw_breakpoint_ctrl.
  408. * Hopefully this will disappear when ptrace can bypass the conversion
  409. * to generic breakpoint descriptions.
  410. */
  411. int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
  412. int *gen_len, int *gen_type)
  413. {
  414. /* Type */
  415. switch (ctrl.type) {
  416. case ARM_BREAKPOINT_EXECUTE:
  417. *gen_type = HW_BREAKPOINT_X;
  418. break;
  419. case ARM_BREAKPOINT_LOAD:
  420. *gen_type = HW_BREAKPOINT_R;
  421. break;
  422. case ARM_BREAKPOINT_STORE:
  423. *gen_type = HW_BREAKPOINT_W;
  424. break;
  425. case ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE:
  426. *gen_type = HW_BREAKPOINT_RW;
  427. break;
  428. default:
  429. return -EINVAL;
  430. }
  431. /* Len */
  432. switch (ctrl.len) {
  433. case ARM_BREAKPOINT_LEN_1:
  434. *gen_len = HW_BREAKPOINT_LEN_1;
  435. break;
  436. case ARM_BREAKPOINT_LEN_2:
  437. *gen_len = HW_BREAKPOINT_LEN_2;
  438. break;
  439. case ARM_BREAKPOINT_LEN_4:
  440. *gen_len = HW_BREAKPOINT_LEN_4;
  441. break;
  442. case ARM_BREAKPOINT_LEN_8:
  443. *gen_len = HW_BREAKPOINT_LEN_8;
  444. break;
  445. default:
  446. return -EINVAL;
  447. }
  448. return 0;
  449. }
  450. /*
  451. * Construct an arch_hw_breakpoint from a perf_event.
  452. */
  453. static int arch_build_bp_info(struct perf_event *bp)
  454. {
  455. struct arch_hw_breakpoint *info = counter_arch_bp(bp);
  456. /* Type */
  457. switch (bp->attr.bp_type) {
  458. case HW_BREAKPOINT_X:
  459. info->ctrl.type = ARM_BREAKPOINT_EXECUTE;
  460. break;
  461. case HW_BREAKPOINT_R:
  462. info->ctrl.type = ARM_BREAKPOINT_LOAD;
  463. break;
  464. case HW_BREAKPOINT_W:
  465. info->ctrl.type = ARM_BREAKPOINT_STORE;
  466. break;
  467. case HW_BREAKPOINT_RW:
  468. info->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE;
  469. break;
  470. default:
  471. return -EINVAL;
  472. }
  473. /* Len */
  474. switch (bp->attr.bp_len) {
  475. case HW_BREAKPOINT_LEN_1:
  476. info->ctrl.len = ARM_BREAKPOINT_LEN_1;
  477. break;
  478. case HW_BREAKPOINT_LEN_2:
  479. info->ctrl.len = ARM_BREAKPOINT_LEN_2;
  480. break;
  481. case HW_BREAKPOINT_LEN_4:
  482. info->ctrl.len = ARM_BREAKPOINT_LEN_4;
  483. break;
  484. case HW_BREAKPOINT_LEN_8:
  485. info->ctrl.len = ARM_BREAKPOINT_LEN_8;
  486. if ((info->ctrl.type != ARM_BREAKPOINT_EXECUTE)
  487. && max_watchpoint_len >= 8)
  488. break;
  489. default:
  490. return -EINVAL;
  491. }
  492. /*
  493. * Breakpoints must be of length 2 (thumb) or 4 (ARM) bytes.
  494. * Watchpoints can be of length 1, 2, 4 or 8 bytes if supported
  495. * by the hardware and must be aligned to the appropriate number of
  496. * bytes.
  497. */
  498. if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE &&
  499. info->ctrl.len != ARM_BREAKPOINT_LEN_2 &&
  500. info->ctrl.len != ARM_BREAKPOINT_LEN_4)
  501. return -EINVAL;
  502. /* Address */
  503. info->address = bp->attr.bp_addr;
  504. /* Privilege */
  505. info->ctrl.privilege = ARM_BREAKPOINT_USER;
  506. if (arch_check_bp_in_kernelspace(bp) && !bp_is_single_step(bp))
  507. info->ctrl.privilege |= ARM_BREAKPOINT_PRIV;
  508. /* Enabled? */
  509. info->ctrl.enabled = !bp->attr.disabled;
  510. /* Mismatch */
  511. info->ctrl.mismatch = 0;
  512. return 0;
  513. }
  514. /*
  515. * Validate the arch-specific HW Breakpoint register settings.
  516. */
  517. int arch_validate_hwbkpt_settings(struct perf_event *bp)
  518. {
  519. struct arch_hw_breakpoint *info = counter_arch_bp(bp);
  520. int ret = 0;
  521. u32 offset, alignment_mask = 0x3;
  522. /* Build the arch_hw_breakpoint. */
  523. ret = arch_build_bp_info(bp);
  524. if (ret)
  525. goto out;
  526. /* Check address alignment. */
  527. if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
  528. alignment_mask = 0x7;
  529. offset = info->address & alignment_mask;
  530. switch (offset) {
  531. case 0:
  532. /* Aligned */
  533. break;
  534. case 1:
  535. /* Allow single byte watchpoint. */
  536. if (info->ctrl.len == ARM_BREAKPOINT_LEN_1)
  537. break;
  538. case 2:
  539. /* Allow halfword watchpoints and breakpoints. */
  540. if (info->ctrl.len == ARM_BREAKPOINT_LEN_2)
  541. break;
  542. default:
  543. ret = -EINVAL;
  544. goto out;
  545. }
  546. info->address &= ~alignment_mask;
  547. info->ctrl.len <<= offset;
  548. /*
  549. * Currently we rely on an overflow handler to take
  550. * care of single-stepping the breakpoint when it fires.
  551. * In the case of userspace breakpoints on a core with V7 debug,
  552. * we can use the mismatch feature as a poor-man's hardware single-step.
  553. */
  554. if (WARN_ONCE(!bp->overflow_handler &&
  555. (arch_check_bp_in_kernelspace(bp) || !core_has_mismatch_brps()),
  556. "overflow handler required but none found")) {
  557. ret = -EINVAL;
  558. }
  559. out:
  560. return ret;
  561. }
  562. static void update_mismatch_flag(int idx, int flag)
  563. {
  564. struct perf_event *bp = __get_cpu_var(bp_on_reg[idx]);
  565. struct arch_hw_breakpoint *info;
  566. if (bp == NULL)
  567. return;
  568. info = counter_arch_bp(bp);
  569. /* Update the mismatch field to enter/exit `single-step' mode */
  570. if (!bp->overflow_handler && info->ctrl.mismatch != flag) {
  571. info->ctrl.mismatch = flag;
  572. write_wb_reg(ARM_BASE_BCR + idx, encode_ctrl_reg(info->ctrl) | 0x1);
  573. }
  574. }
  575. static void watchpoint_handler(unsigned long unknown, struct pt_regs *regs)
  576. {
  577. int i;
  578. struct perf_event *bp, **slots = __get_cpu_var(wp_on_reg);
  579. struct arch_hw_breakpoint *info;
  580. struct perf_event_attr attr;
  581. /* Without a disassembler, we can only handle 1 watchpoint. */
  582. BUG_ON(core_num_wrps > 1);
  583. hw_breakpoint_init(&attr);
  584. attr.bp_addr = regs->ARM_pc & ~0x3;
  585. attr.bp_len = HW_BREAKPOINT_LEN_4;
  586. attr.bp_type = HW_BREAKPOINT_X;
  587. for (i = 0; i < core_num_wrps; ++i) {
  588. rcu_read_lock();
  589. if (slots[i] == NULL) {
  590. rcu_read_unlock();
  591. continue;
  592. }
  593. /*
  594. * The DFAR is an unknown value. Since we only allow a
  595. * single watchpoint, we can set the trigger to the lowest
  596. * possible faulting address.
  597. */
  598. info = counter_arch_bp(slots[i]);
  599. info->trigger = slots[i]->attr.bp_addr;
  600. pr_debug("watchpoint fired: address = 0x%x\n", info->trigger);
  601. perf_bp_event(slots[i], regs);
  602. /*
  603. * If no overflow handler is present, insert a temporary
  604. * mismatch breakpoint so we can single-step over the
  605. * watchpoint trigger.
  606. */
  607. if (!slots[i]->overflow_handler) {
  608. bp = register_user_hw_breakpoint(&attr,
  609. wp_single_step_handler,
  610. current);
  611. counter_arch_bp(bp)->suspended_wp = slots[i];
  612. perf_event_disable(slots[i]);
  613. }
  614. rcu_read_unlock();
  615. }
  616. }
  617. static void breakpoint_handler(unsigned long unknown, struct pt_regs *regs)
  618. {
  619. int i;
  620. int mismatch;
  621. u32 ctrl_reg, val, addr;
  622. struct perf_event *bp, **slots = __get_cpu_var(bp_on_reg);
  623. struct arch_hw_breakpoint *info;
  624. struct arch_hw_breakpoint_ctrl ctrl;
  625. /* The exception entry code places the amended lr in the PC. */
  626. addr = regs->ARM_pc;
  627. for (i = 0; i < core_num_brps + core_num_reserved_brps; ++i) {
  628. rcu_read_lock();
  629. bp = slots[i];
  630. if (bp == NULL) {
  631. rcu_read_unlock();
  632. continue;
  633. }
  634. mismatch = 0;
  635. /* Check if the breakpoint value matches. */
  636. val = read_wb_reg(ARM_BASE_BVR + i);
  637. if (val != (addr & ~0x3))
  638. goto unlock;
  639. /* Possible match, check the byte address select to confirm. */
  640. ctrl_reg = read_wb_reg(ARM_BASE_BCR + i);
  641. decode_ctrl_reg(ctrl_reg, &ctrl);
  642. if ((1 << (addr & 0x3)) & ctrl.len) {
  643. mismatch = 1;
  644. info = counter_arch_bp(bp);
  645. info->trigger = addr;
  646. }
  647. unlock:
  648. if ((mismatch && !info->ctrl.mismatch) || bp_is_single_step(bp)) {
  649. pr_debug("breakpoint fired: address = 0x%x\n", addr);
  650. perf_bp_event(bp, regs);
  651. }
  652. update_mismatch_flag(i, mismatch);
  653. rcu_read_unlock();
  654. }
  655. }
  656. /*
  657. * Called from either the Data Abort Handler [watchpoint] or the
  658. * Prefetch Abort Handler [breakpoint] with preemption disabled.
  659. */
  660. static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
  661. struct pt_regs *regs)
  662. {
  663. int ret = 0;
  664. u32 dscr;
  665. /* We must be called with preemption disabled. */
  666. WARN_ON(preemptible());
  667. /* We only handle watchpoints and hardware breakpoints. */
  668. ARM_DBG_READ(c1, 0, dscr);
  669. /* Perform perf callbacks. */
  670. switch (ARM_DSCR_MOE(dscr)) {
  671. case ARM_ENTRY_BREAKPOINT:
  672. breakpoint_handler(addr, regs);
  673. break;
  674. case ARM_ENTRY_ASYNC_WATCHPOINT:
  675. WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n");
  676. case ARM_ENTRY_SYNC_WATCHPOINT:
  677. watchpoint_handler(addr, regs);
  678. break;
  679. default:
  680. ret = 1; /* Unhandled fault. */
  681. }
  682. /*
  683. * Re-enable preemption after it was disabled in the
  684. * low-level exception handling code.
  685. */
  686. preempt_enable();
  687. return ret;
  688. }
  689. /*
  690. * One-time initialisation.
  691. */
  692. static void reset_ctrl_regs(void *unused)
  693. {
  694. int i;
  695. /*
  696. * v7 debug contains save and restore registers so that debug state
  697. * can be maintained across low-power modes without leaving
  698. * the debug logic powered up. It is IMPLEMENTATION DEFINED whether
  699. * we can write to the debug registers out of reset, so we must
  700. * unlock the OS Lock Access Register to avoid taking undefined
  701. * instruction exceptions later on.
  702. */
  703. if (debug_arch >= ARM_DEBUG_ARCH_V7_ECP14) {
  704. /*
  705. * Unconditionally clear the lock by writing a value
  706. * other than 0xC5ACCE55 to the access register.
  707. */
  708. asm volatile("mcr p14, 0, %0, c1, c0, 4" : : "r" (0));
  709. isb();
  710. }
  711. if (enable_monitor_mode())
  712. return;
  713. /* We must also reset any reserved registers. */
  714. for (i = 0; i < core_num_brps + core_num_reserved_brps; ++i) {
  715. write_wb_reg(ARM_BASE_BCR + i, 0UL);
  716. write_wb_reg(ARM_BASE_BVR + i, 0UL);
  717. }
  718. for (i = 0; i < core_num_wrps; ++i) {
  719. write_wb_reg(ARM_BASE_WCR + i, 0UL);
  720. write_wb_reg(ARM_BASE_WVR + i, 0UL);
  721. }
  722. }
  723. static int __cpuinit dbg_reset_notify(struct notifier_block *self,
  724. unsigned long action, void *cpu)
  725. {
  726. if (action == CPU_ONLINE)
  727. smp_call_function_single((int)cpu, reset_ctrl_regs, NULL, 1);
  728. return NOTIFY_OK;
  729. }
  730. static struct notifier_block __cpuinitdata dbg_reset_nb = {
  731. .notifier_call = dbg_reset_notify,
  732. };
  733. static int __init arch_hw_breakpoint_init(void)
  734. {
  735. int ret = 0;
  736. u32 dscr;
  737. debug_arch = get_debug_arch();
  738. if (debug_arch > ARM_DEBUG_ARCH_V7_ECP14) {
  739. pr_info("debug architecture 0x%x unsupported.\n", debug_arch);
  740. ret = -ENODEV;
  741. goto out;
  742. }
  743. /* Determine how many BRPs/WRPs are available. */
  744. core_num_brps = get_num_brps();
  745. core_num_reserved_brps = get_num_reserved_brps();
  746. core_num_wrps = get_num_wrps();
  747. pr_info("found %d breakpoint and %d watchpoint registers.\n",
  748. core_num_brps + core_num_reserved_brps, core_num_wrps);
  749. if (core_num_reserved_brps)
  750. pr_info("%d breakpoint(s) reserved for watchpoint "
  751. "single-step.\n", core_num_reserved_brps);
  752. ARM_DBG_READ(c1, 0, dscr);
  753. if (dscr & ARM_DSCR_HDBGEN) {
  754. pr_warning("halting debug mode enabled. Assuming maximum "
  755. "watchpoint size of 4 bytes.");
  756. } else {
  757. /*
  758. * Reset the breakpoint resources. We assume that a halting
  759. * debugger will leave the world in a nice state for us.
  760. */
  761. smp_call_function(reset_ctrl_regs, NULL, 1);
  762. reset_ctrl_regs(NULL);
  763. /* Work out the maximum supported watchpoint length. */
  764. max_watchpoint_len = get_max_wp_len();
  765. pr_info("maximum watchpoint size is %u bytes.\n",
  766. max_watchpoint_len);
  767. }
  768. /* Register debug fault handler. */
  769. hook_fault_code(2, hw_breakpoint_pending, SIGTRAP, TRAP_HWBKPT,
  770. "watchpoint debug exception");
  771. hook_ifault_code(2, hw_breakpoint_pending, SIGTRAP, TRAP_HWBKPT,
  772. "breakpoint debug exception");
  773. /* Register hotplug notifier. */
  774. register_cpu_notifier(&dbg_reset_nb);
  775. out:
  776. return ret;
  777. }
  778. arch_initcall(arch_hw_breakpoint_init);
  779. void hw_breakpoint_pmu_read(struct perf_event *bp)
  780. {
  781. }
  782. /*
  783. * Dummy function to register with die_notifier.
  784. */
  785. int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
  786. unsigned long val, void *data)
  787. {
  788. return NOTIFY_DONE;
  789. }