slb_low.S 4.2 KB

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  1. /*
  2. * arch/ppc64/mm/slb_low.S
  3. *
  4. * Low-level SLB routines
  5. *
  6. * Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM
  7. *
  8. * Based on earlier C version:
  9. * Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com
  10. * Copyright (c) 2001 Dave Engebretsen
  11. * Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM
  12. *
  13. * This program is free software; you can redistribute it and/or
  14. * modify it under the terms of the GNU General Public License
  15. * as published by the Free Software Foundation; either version
  16. * 2 of the License, or (at your option) any later version.
  17. */
  18. #include <linux/config.h>
  19. #include <asm/processor.h>
  20. #include <asm/page.h>
  21. #include <asm/mmu.h>
  22. #include <asm/ppc_asm.h>
  23. #include <asm/asm-offsets.h>
  24. #include <asm/cputable.h>
  25. /* void slb_allocate(unsigned long ea);
  26. *
  27. * Create an SLB entry for the given EA (user or kernel).
  28. * r3 = faulting address, r13 = PACA
  29. * r9, r10, r11 are clobbered by this function
  30. * No other registers are examined or changed.
  31. */
  32. _GLOBAL(slb_allocate)
  33. /*
  34. * First find a slot, round robin. Previously we tried to find
  35. * a free slot first but that took too long. Unfortunately we
  36. * dont have any LRU information to help us choose a slot.
  37. */
  38. #ifdef CONFIG_PPC_ISERIES
  39. /*
  40. * On iSeries, the "bolted" stack segment can be cast out on
  41. * shared processor switch so we need to check for a miss on
  42. * it and restore it to the right slot.
  43. */
  44. ld r9,PACAKSAVE(r13)
  45. clrrdi r9,r9,28
  46. clrrdi r11,r3,28
  47. li r10,SLB_NUM_BOLTED-1 /* Stack goes in last bolted slot */
  48. cmpld r9,r11
  49. beq 3f
  50. #endif /* CONFIG_PPC_ISERIES */
  51. ld r10,PACASTABRR(r13)
  52. addi r10,r10,1
  53. /* use a cpu feature mask if we ever change our slb size */
  54. cmpldi r10,SLB_NUM_ENTRIES
  55. blt+ 4f
  56. li r10,SLB_NUM_BOLTED
  57. 4:
  58. std r10,PACASTABRR(r13)
  59. 3:
  60. /* r3 = faulting address, r10 = entry */
  61. srdi r9,r3,60 /* get region */
  62. srdi r3,r3,28 /* get esid */
  63. cmpldi cr7,r9,0xc /* cmp KERNELBASE for later use */
  64. rldimi r10,r3,28,0 /* r10= ESID<<28 | entry */
  65. oris r10,r10,SLB_ESID_V@h /* r10 |= SLB_ESID_V */
  66. /* r3 = esid, r10 = esid_data, cr7 = <>KERNELBASE */
  67. blt cr7,0f /* user or kernel? */
  68. /* kernel address: proto-VSID = ESID */
  69. /* WARNING - MAGIC: we don't use the VSID 0xfffffffff, but
  70. * this code will generate the protoVSID 0xfffffffff for the
  71. * top segment. That's ok, the scramble below will translate
  72. * it to VSID 0, which is reserved as a bad VSID - one which
  73. * will never have any pages in it. */
  74. li r11,SLB_VSID_KERNEL
  75. BEGIN_FTR_SECTION
  76. bne cr7,9f
  77. li r11,(SLB_VSID_KERNEL|SLB_VSID_L)
  78. END_FTR_SECTION_IFSET(CPU_FTR_16M_PAGE)
  79. b 9f
  80. 0: /* user address: proto-VSID = context<<15 | ESID */
  81. srdi. r9,r3,USER_ESID_BITS
  82. bne- 8f /* invalid ea bits set */
  83. #ifdef CONFIG_HUGETLB_PAGE
  84. BEGIN_FTR_SECTION
  85. lhz r9,PACAHIGHHTLBAREAS(r13)
  86. srdi r11,r3,(HTLB_AREA_SHIFT-SID_SHIFT)
  87. srd r9,r9,r11
  88. lhz r11,PACALOWHTLBAREAS(r13)
  89. srd r11,r11,r3
  90. or r9,r9,r11
  91. END_FTR_SECTION_IFSET(CPU_FTR_16M_PAGE)
  92. #endif /* CONFIG_HUGETLB_PAGE */
  93. li r11,SLB_VSID_USER
  94. #ifdef CONFIG_HUGETLB_PAGE
  95. BEGIN_FTR_SECTION
  96. rldimi r11,r9,8,55 /* shift masked bit into SLB_VSID_L */
  97. END_FTR_SECTION_IFSET(CPU_FTR_16M_PAGE)
  98. #endif /* CONFIG_HUGETLB_PAGE */
  99. ld r9,PACACONTEXTID(r13)
  100. rldimi r3,r9,USER_ESID_BITS,0
  101. 9: /* r3 = protovsid, r11 = flags, r10 = esid_data, cr7 = <>KERNELBASE */
  102. ASM_VSID_SCRAMBLE(r3,r9)
  103. rldimi r11,r3,SLB_VSID_SHIFT,16 /* combine VSID and flags */
  104. /*
  105. * No need for an isync before or after this slbmte. The exception
  106. * we enter with and the rfid we exit with are context synchronizing.
  107. */
  108. slbmte r11,r10
  109. bgelr cr7 /* we're done for kernel addresses */
  110. /* Update the slb cache */
  111. lhz r3,PACASLBCACHEPTR(r13) /* offset = paca->slb_cache_ptr */
  112. cmpldi r3,SLB_CACHE_ENTRIES
  113. bge 1f
  114. /* still room in the slb cache */
  115. sldi r11,r3,1 /* r11 = offset * sizeof(u16) */
  116. rldicl r10,r10,36,28 /* get low 16 bits of the ESID */
  117. add r11,r11,r13 /* r11 = (u16 *)paca + offset */
  118. sth r10,PACASLBCACHE(r11) /* paca->slb_cache[offset] = esid */
  119. addi r3,r3,1 /* offset++ */
  120. b 2f
  121. 1: /* offset >= SLB_CACHE_ENTRIES */
  122. li r3,SLB_CACHE_ENTRIES+1
  123. 2:
  124. sth r3,PACASLBCACHEPTR(r13) /* paca->slb_cache_ptr = offset */
  125. blr
  126. 8: /* invalid EA */
  127. li r3,0 /* BAD_VSID */
  128. li r11,SLB_VSID_USER /* flags don't much matter */
  129. b 9b