 Yinghai Lu
|
4078c444cf
perf_counter, x86: Update x86_pmu after WARN()
|
16 years ago |
 Peter Zijlstra
|
194002b274
perf_counter, x86: Add mmap counter read support
|
16 years ago |
 Yong Wang
|
c14dab5c07
perf_counter, x86: Set global control MSR correctly
|
16 years ago |
 Jaswinder Singh Rajput
|
d9f2a5ecb2
perf_counter, x8: Fix L1-data-Cache-Store-Referencees for AMD
|
16 years ago |
|
Peter Zijlstra
|
f9188e023c
perf_counter: Make callchain samples extensible
|
16 years ago |
|
Peter Zijlstra
|
60f916dee6
perf_counter: x86: Set the period in the intel overflow handler
|
16 years ago |
|
Peter Zijlstra
|
74193ef0ec
perf_counter: x86: Fix call-chain support to use NMI-safe methods
|
16 years ago |
 Ingo Molnar
|
038e836e97
perf_counter, x86: Fix kernel-space call-chains
|
16 years ago |
|
Ingo Molnar
|
5a6cec3abb
perf_counter, x86: Fix call-chain walking
|
16 years ago |
|
Jaswinder Singh Rajput
|
f4db43a38f
perf_counter, x86: Update AMD hw caching related event table
|
16 years ago |
|
Jaswinder Singh Rajput
|
4d2be1267f
perf_counter, x86: Check old-AMD performance monitoring support
|
16 years ago |
|
Yong Wang
|
dff5da6d09
perf_counter/x86: Add a quirk for Atom processors
|
16 years ago |
|
Peter Zijlstra
|
8be6e8f3c3
perf_counter: Rename L2 to LL cache
|
16 years ago |
|
Peter Zijlstra
|
f4dbfa8f31
perf_counter: Standardize event names
|
16 years ago |
|
Peter Zijlstra
|
9e350de37a
perf_counter: Accurate period data
|
16 years ago |
|
Peter Zijlstra
|
df1a132bf3
perf_counter: Introduce struct for sample data
|
16 years ago |
|
Peter Zijlstra
|
bd2b5b1284
perf_counter: More aggressive frequency adjustment
|
16 years ago |
|
Yong Wang
|
dc81081b2d
perf_counter/x86: Fix the model number of Intel Core2 processors
|
16 years ago |
|
Yong Wang
|
fecc8ac849
perf_counter, x86: Correct some event and umask values for Intel processors
|
16 years ago |
 Thomas Gleixner
|
820a644211
perf_counter, x86: Clean up hw_cache_event ids copies
|
16 years ago |
|
Thomas Gleixner
|
f86748e91a
perf_counter, x86: Implement generalized cache event types, add AMD support
|
16 years ago |
|
Ingo Molnar
|
1123e3ad73
perf_counter: Clean up x86 boot messages
|
16 years ago |
|
Thomas Gleixner
|
ad68922061
perf_counter, x86: Implement generalized cache event types, add Atom support
|
16 years ago |
|
Thomas Gleixner
|
0312af8416
perf_counter, x86: Implement generalized cache event types, add Core2 support
|
16 years ago |
|
Ingo Molnar
|
8326f44da0
perf_counter: Implement generalized cache event types
|
16 years ago |
|
Ingo Molnar
|
a21ca2cac5
perf_counter: Separate out attr->type from attr->config
|
16 years ago |
|
Ingo Molnar
|
128f048f0f
perf_counter: Fix throttling lock-up
|
16 years ago |
|
Yong Wang
|
a32881066e
perf_counter/x86: Remove the IRQ (non-NMI) handling bits
|
16 years ago |
|
Peter Zijlstra
|
0d48696f87
perf_counter: Rename perf_counter_hw_event => perf_counter_attr
|
16 years ago |
|
Peter Zijlstra
|
e4abb5d4f7
perf_counter: x86: Emulate longer sample periods
|
16 years ago |
