 Ville Syrjälä
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86d3efce2c
drm/i915: Implement pipe CSC based limited range RGB output
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12 years ago |
|
Ville Syrjälä
|
b9e1faa763
drm/i915: Fix PIPE_CONTROL DW/QW write through global GTT on IVB+
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12 years ago |
 Damien Lespiau
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876a8cdf92
drm/i915: Preserve the DDI link reversal configuration
|
12 years ago |
|
Damien Lespiau
|
3e68320ef8
drm/i915: Preserve the FDI line reversal override bit on CPT
|
12 years ago |
 Daniel Vetter
|
1d7aaa0cfe
drm/i915: detect wrong MCH watermark values
|
12 years ago |
|
Daniel Vetter
|
26739f12cf
drm/i915: unify HDMI/DP hpd definitions
|
12 years ago |
 Ben Widawsky
|
7083e05072
drm/i915: Fix RC6VIDS encode/decode
|
12 years ago |
 Dave Airlie
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6dc1c49da6
Merge branch 'fbcon-locking-fixes' of ssh://people.freedesktop.org/~airlied/linux into drm-next
|
12 years ago |
|
Ville Syrjälä
|
766aa1c423
drm/i915: Introduce i915_vgacntrl_reg()
|
12 years ago |
|
Ben Widawsky
|
f82855d342
drm/i915: Fix CAGF for HSW
|
12 years ago |
|
Ben Widawsky
|
41c0b3a88c
drm/i915: Implement WaVSRefCountFullforceMissDisable
|
12 years ago |
 Paulo Zanoni
|
fa42e23c10
drm/i915: fix intel_init_power_wells
|
12 years ago |
|
Ville Syrjälä
|
80a75f7c44
drm/i915: SWF screatch registers need an offset on VLV
|
12 years ago |
|
Ville Syrjälä
|
56a12a5092
drm/i915: Include display_mmio_offset in sequencer index/data registers
|
12 years ago |
|
Ville Syrjälä
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fc2de40986
drm/i915: PLL registers need an offset on VLV
|
12 years ago |
|
Ville Syrjälä
|
54d9d493ce
drm/i915: DPIO registers are VLV only and need an offset
|
12 years ago |
|
Ville Syrjälä
|
ff76301099
drm/i915: Spell out VLV_DISPLAY_BASE for interrupt registers
|
12 years ago |
|
Ville Syrjälä
|
07ec7ec55b
drm/i915: Make VLV_GUNIT_CLOCK_GATE register value more readable
|
12 years ago |
|
Ville Syrjälä
|
d88b227086
drm/i915: FB_BLC_SELF_VLV is VLV only and needs an offset
|
12 years ago |
|
Ville Syrjälä
|
4b0599854b
drm/i915: Pipe palette registers need an offset on VLV
|
12 years ago |
|
Ville Syrjälä
|
4e8e7eb703
drm/i915: Pipe timing registers need an offset on VLV
|
12 years ago |
|
Ville Syrjälä
|
67d62c5746
drm/i915: PORT_HOTPLUG registers need an offset on VLV
|
12 years ago |
|
Ville Syrjälä
|
7e470abf54
drm/i915: Panel fitter registers need an offset on VLV
|
12 years ago |
|
Ville Syrjälä
|
b41fbda151
drm/i915: DPFLIPSTAT and DPINVGTT registers are VLV only and need an offset
|
12 years ago |
|
Ville Syrjälä
|
90f7da3fb5
drm/i915: DSPFW registers need an offset on VLV
|
12 years ago |
|
Ville Syrjälä
|
8f6d8ee9f6
drm/i915: VLV_DDL is VLV only and needs an offset
|
12 years ago |
|
Ville Syrjälä
|
9dc33f31f2
drm/i915: Cursor registers need an offset on VLV
|
12 years ago |
|
Ville Syrjälä
|
0c3870ee58
drm/i915: Pipe registers need an offset on VLV
|
12 years ago |
|
Ville Syrjälä
|
895abf0c3c
drm/i915: Primary plane registers need an offset on VLV
|
12 years ago |
|
Ville Syrjälä
|
aab17139a0
drm/i915: PIPE M/N registers need an offset on VLV
|
12 years ago |
