Commit History

Author SHA1 Message Date
  Vipul Kumar Samar 1249979242 CLK: SPEAr: Set CLK_SET_RATE_PARENT for few clocks 12 years ago
  Viresh Kumar 10d8935f46 Viresh has moved 13 years ago
  Viresh Kumar 5335a639ec SPEAr: clk: Add Auxiliary Synthesizer clock 13 years ago