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master
phyCORE-Vybrid-PD15.1-rc1
vphyCORE-Vybrid-PD15.1-rc1
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SHA1
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Vipul Kumar Samar
d4f513ff12
Clk: SPEAr1340: Update sys clock parent array
13 anni fa
Vipul Kumar Samar
d9ba8db215
clk: SPEAr1340: Fix clk enable register for uart1 and i2c1.
13 anni fa
Vipul Kumar Samar
5cb6a9bcca
clk:spear1340:Fix: Rename clk ids within predefined limit
13 anni fa
Viresh Kumar
10d8935f46
Viresh has moved
13 anni fa
Viresh Kumar
0b928af1f4
SPEAr13xx: Add common clock framework support
13 anni fa