提交歷史

作者 SHA1 備註 提交日期
  Ralf Baechle 36cfbaad81 [MIPS] Convert list of CPU types from #define to enum. 17 年之前
  Ralf Baechle 641e97f318 [MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code. 17 年之前
  Aurelien Jarno 1c0c13eb93 [MIPS] Add support for BCM47XX CPUs. 17 年之前
  Marc St-Jean 9267a30d1d [MIPS] PMC MSP71xx mips common 18 年之前
  Fuxin Zhang 2a21c7300b [MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2 18 年之前
  Ralf Baechle a36920200c [MIPS] Enable support for the userlocal hardware register 18 年之前
  Ralf Baechle fde97822a2 [MIPS] Add macros to encode processor revisions. 18 年之前
  Ralf Baechle fc5d2d279f [MIPS] Use the proper technical term for naming some of the cache macros. 19 年之前
  Kumba 44d921b246 [MIPS] Treat R14000 like R10000. 19 年之前
  Chris Dearman c620953c32 [MIPS] Fix detection and handling of the 74K processor. 19 年之前
  Maciej W. Rozycki 9cf8ff9644 [MIPS] Fix CPU type bitmasks for MIPS III, IV and V. 19 年之前
  Ralf Baechle 0401572a9b MIPS: Reorganize ISA constants strictly as bitmasks. 19 年之前
  Ralf Baechle b4672d3729 MIPS: Introduce machinery for testing for MIPSxxR1/2. 19 年之前
  Ralf Baechle e7958bb90d MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1. 19 年之前
  Andrew Isaacson 93ce2f524e Add support for SB1A CPU. 19 年之前
  Ralf Baechle 02cf211968 Cleanup the mess in cpu_cache_init. 19 年之前
  Maciej W. Rozycki 98e316d4b1 Move MIPS Technologies processor IDs to where they belong. 19 年之前
  Pete Popov bdf21b18b4 Philips PNX8550 support: MIPS32-like core with 2 Trimedias on it. 20 年之前
  Ralf Baechle 8f40611d2b Detect the MIPS R2 vectored interrupt, external interrupt controller 20 年之前
  Ralf Baechle bbc7f22f6d Detect the 34K. 20 年之前
  Ralf Baechle e50c0a8fa6 Support the MIPS32 / MIPS64 DSP ASE. 20 年之前
  Ralf Baechle 4194318c39 Cleanup decoding of MIPSxx config registers. 20 年之前
  Pete Popov e3ad1c23ba Base Au1200 2.6 support. 20 年之前
  Ralf Baechle 55a6feb671 Add a few more PrId vendor IDs. 20 年之前
  Linus Torvalds 1da177e4c3 Linux-2.6.12-rc2 20 年之前