 Ben Widawsky
|
26b1ff35c8
drm/i915: Move the remaining gtt code
|
13 years ago |
|
Ben Widawsky
|
0f9b91c754
drm/i915: flush system agent TLBs on SNB
|
13 years ago |
|
Ben Widawsky
|
03752f5b7b
drm/i915: Calculate correct stolen size for GEN7+
|
13 years ago |
|
Ben Widawsky
|
e76e9aebcd
drm/i915: Stop using AGP layer for GEN6+
|
13 years ago |
 Jesse Barnes
|
9a28977181
drm/i915: TLB invalidation with MI_FLUSH_DW requires a post-sync op v3
|
13 years ago |
|
Jesse Barnes
|
12f3382bc0
drm/i915: implement WaDisablePSDDualDispatchEnable on IVB & VLV
|
13 years ago |
|
Jesse Barnes
|
2d809570c8
drm/i915: implement WaDisableVLVClockGating_VBIIssue on VLV
|
13 years ago |
|
Jesse Barnes
|
8ab4397640
drm/i915: implement WaDisableDopClockGatingisable on VLV and IVB
|
13 years ago |
|
Jesse Barnes
|
d0cf5eadc0
drm/i915: implement WaDisableL3CacheAging on VLV
|
13 years ago |
 Paulo Zanoni
|
049456416f
drm/i915: fix Haswell FDI link training code
|
13 years ago |
 Daniel Vetter
|
ce40141f55
drm/i915: implement WADP0ClockGatingDisable
|
13 years ago |
|
Daniel Vetter
|
23670b322c
drm/i915: CPT+ pch transcoder workaround
|
13 years ago |
 Ville Syrjälä
|
32ae46bf01
drm/i915: Add SURFLIVE register definitions
|
13 years ago |
|
Ville Syrjälä
|
57779d0636
drm/i915: Fix display pixel format handling
|
13 years ago |
|
Daniel Vetter
|
4358a3748c
drm/i915: implement WaDisableRenderCachePipelinedFlush
|
13 years ago |
 Damien Lespiau
|
c54173a85d
drm/i915: Fix sprite offset on HSW
|
13 years ago |
|
Damien Lespiau
|
bc1c91ebe3
drm/i915: Fix primary plane offset on HSW
|
13 years ago |
|
Daniel Vetter
|
01a415fd02
drm/i915: check fdi B/C lane sharing constraint
|
13 years ago |
|
Paulo Zanoni
|
fe2b8f9dfb
drm/i915: convert pipe timing definitions to transcoder
|
13 years ago |
|
Paulo Zanoni
|
afe2fcf5e0
drm/i915: convert CPU M/N timings to transcoder
|
13 years ago |
|
Paulo Zanoni
|
c9809791ae
drm/i915: convert PIPE_MSA_MISC to transcoder
|
13 years ago |
|
Paulo Zanoni
|
702e7a56af
drm/i915: convert PIPECONF to use transcoder instead of pipe
|
13 years ago |
|
Paulo Zanoni
|
ad80a810ec
drm/i915: convert DDI_FUNC_CTL to transcoder
|
13 years ago |
|
Paulo Zanoni
|
bb523fc08d
drm/i915: convert PIPE_CLK_SEL to transcoder
|
13 years ago |
|
Paulo Zanoni
|
a5c961d1f3
drm/i915: add TRANSCODER_EDP
|
13 years ago |
|
Daniel Vetter
|
82ed61fa1a
drm/i915: make edp panel power sequence setup more robust
|
13 years ago |
|
Daniel Vetter
|
c2fb791692
Merge tag 'v3.7-rc2' into drm-intel-next-queued
|
13 years ago |
|
Damien Lespiau
|
231e54f639
drm/i915: Consolidate ILK_DSPCLK_GATE and PCH_DSPCLK_GATE
|
13 years ago |
|
Paulo Zanoni
|
d6c0d722ae
drm/i915: add basic Haswell DP link train bits
|
13 years ago |
|
Paulo Zanoni
|
dae847991a
drm/i915: add intel_ddi_set_pipe_settings
|
13 years ago |
