Cronologia Commit

Autore SHA1 Messaggio Data
  Ralf Baechle e0daad449c [MIPS] Whitespace cleanups. 18 anni fa
  Ralf Baechle c237923009 [MIPS] Don't print presence of WAIT instruction on bootup. 18 anni fa
  Ralf Baechle 441ee341ad [MIPS] Fix RM9000 wait instruction detection. 19 anni fa
  Atsushi Nemoto 60a6c3777e [MIPS] Reduce race between cpu_wait() and need_resched() checking 19 anni fa
  Thiemo Seufer c36cd4bab5 [MIPS] Save 2k text size in cpu-probe 19 anni fa
  Thiemo Seufer 3a01c49ad8 [MIPS] Uses MIPS_CONF_AR instead of magic constants. 19 anni fa
  Jörn Engel 6ab3d5624e Remove obsolete #include <linux/config.h> 19 anni fa
  Chris Dearman 9318c51acd [MIPS] MIPS32/MIPS64 secondary cache management 19 anni fa
  Ralf Baechle aa32374aaa [MIPS] SB1: Only pass1 FPUs are broken beyond recovery. 19 anni fa
  Kumba 44d921b246 [MIPS] Treat R14000 like R10000. 19 anni fa
  Chris Dearman c620953c32 [MIPS] Fix detection and handling of the 74K processor. 19 anni fa
  Ralf Baechle a3dddd560e [MIPS] War on whitespace: cleanup initial spaces followed by tabs. 19 anni fa
  Ralf Baechle 010b853b3a [MIPS] Get rid of CONFIG_SB1_PASS_1_WORKAROUNDS #ifdef crapola. 19 anni fa
  Ralf Baechle b4672d3729 MIPS: Introduce machinery for testing for MIPSxxR1/2. 19 anni fa
  Ralf Baechle e7958bb90d MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1. 19 anni fa
  Ralf Baechle 8b36612a23 [MIPS] R10000 and R12000 need to set MIPS_CPU_4K_CACHE ... 19 anni fa
  Andrew Isaacson 93ce2f524e Add support for SB1A CPU. 19 anni fa
  Andrew Isaacson d121ced21d Sibyte fixes 19 anni fa
  Ralf Baechle 8afcb5d829 Detect 4KSD and treat it like 4KSc. 19 anni fa
  Ralf Baechle 02cf211968 Cleanup the mess in cpu_cache_init. 19 anni fa
  Thiemo Seufer 075e7502d9 R4600 has 32 FPRs. 20 anni fa
  Pete Popov bdf21b18b4 Philips PNX8550 support: MIPS32-like core with 2 Trimedias on it. 20 anni fa
  Ralf Baechle 8f40611d2b Detect the MIPS R2 vectored interrupt, external interrupt controller 20 anni fa
  Ralf Baechle 55d04dff0f New kernel option nowait allows disabling the use of the wait instruction. 20 anni fa
  Ralf Baechle bbc7f22f6d Detect the 34K. 20 anni fa
  Maciej W. Rozycki d5b6f1db5d For MIPS32/MIPS64 cp0.config.mt == 1 implies a standard (R4k-style) 20 anni fa
  Ralf Baechle e50c0a8fa6 Support the MIPS32 / MIPS64 DSP ASE. 20 anni fa
  Ralf Baechle 10f650db1b 64-bit fixes for Alchemy code ;) 20 anni fa
  Ralf Baechle b382fe8483 No point in checking cpu_has_tlb before we've computed the CPU options. 20 anni fa
  Ralf Baechle 4194318c39 Cleanup decoding of MIPSxx config registers. 20 anni fa