Commit History

Author SHA1 Message Date
  Jesse Barnes ab2f9df10d drm/i915: fix color order for BGR formats on SNB 13 years ago
  Kenneth Graunke d71de14ddf drm/i915: gen7: Disable the RHWO optimization as it can cause GPU hangs. 13 years ago
  Eugeni Dodonov db099c8f96 drm/i915: gen7: work around a system hang on IVB 13 years ago
  Eugeni Dodonov e4e0c058a1 drm/i915: gen7: Implement an L3 caching workaround. 13 years ago
  Eugeni Dodonov eae66b50c7 drm/i915: gen7: implement rczunit workaround 13 years ago
  Eric Anholt ae662d3126 drm/i915: Add support for resetting the SO write pointers on gen7. 13 years ago
  Eric Anholt 116ac8d261 drm/i915: Set two chicken bits implicated in missed IRQs on Ivybridge. 13 years ago
  Jesse Barnes 8ea3086422 drm/i915: add color key support v4 13 years ago
  Jesse Barnes b840d907fc drm/i915: add SNB and IVB video sprite support v6 13 years ago
  Ben Widawsky 4d85529d58 drm/i915: drpc debugfs update for gen6 13 years ago
  Ben Widawsky 6ed55ee7da drm/i915: Update GEN6_RP_CONTROL definitions 13 years ago
  Ben Widawsky 84f9f938be drm/i915: Force sync command ordering (Gen6+) 13 years ago
  Dave Airlie 2318fcd65c Merge branch 'drm-intel-next' of git://people.freedesktop.org/~keithp/linux into drm-core-next 13 years ago
  Dave Airlie 1fbe6f625f Merge tag 'v3.2-rc6' of /home/airlied/devel/kernel/linux-2.6 into drm-core-next 13 years ago
  Christian Schmidt 59df7b1771 drm/intel: Fix initialization if startup happens in interlaced mode [v2] 13 years ago
  Wu Fengguang 1202b4c678 drm/i915: rename audio ELD registers 13 years ago
  Paulo Zanoni 3573c4103f drm/i915: set the right SDVO transcoder for CPT 13 years ago
  Keith Packard 1a2eb4604b drm/i915: Hook up Ivybridge eDP 13 years ago
  Keith Packard 8d715f0024 drm/i915: add multi-threaded forcewake support 13 years ago
  Keith Packard 99ea7127a3 drm/i915: Let panel power sequencing hardware do its job 13 years ago
  Eric Anholt 9ca1d10d74 drm/i915: Turn on another required clock gating bit on gen6. 13 years ago
  Eric Anholt 406478dc91 drm/i915: Turn on a required 3D clock gating bit on Sandybridge. 13 years ago
  Jesse Barnes d6c892df7e drm/i915: set watermarks for third pipe on IVB 13 years ago
  Jesse Barnes 65a21cd653 drm/i915: fix IVB cursor support 13 years ago
  Jesse Barnes 4c609cb890 drm/i915: PLL macro cleanup and pipe assertion check 14 years ago
  Jesse Barnes c4f9c4c2b3 drm/i915: always set FDI composite sync bit 13 years ago
  Jesse Barnes 8d31528703 drm/i915: Use PIPE_CONTROL for flushing on gen6+. 13 years ago
  Kenneth Graunke 9d971b3753 drm/i915: Rename PIPE_CONTROL bit defines to be less terse. 13 years ago
  Kenneth Graunke fcbc34e4dc drm/i915: Remove implied length of 2 from GFX_OP_PIPE_CONTROL #define. 13 years ago
  Keith Packard 86a3073e48 Merge branch 'edp-training-fixes' into drm-intel-next 13 years ago