Commit History

Autor SHA1 Mensaxe Data
  Atsushi Nemoto 3c68da798a [MIPS] Use __ffs() instead of ffs() for waybit calculation. %!s(int64=19) %!d(string=hai) anos
  Ralf Baechle 7e3bfc7cfc [MIPS] Handle IDE PIO cache aliases on SMP. %!s(int64=19) %!d(string=hai) anos
  Atsushi Nemoto 67a3f6de93 [MIPS] Fix tx49_blast_icache32_page_indexed. %!s(int64=19) %!d(string=hai) anos
  Atsushi Nemoto de862b488e [MIPS] TX49XX has prefetch. %!s(int64=19) %!d(string=hai) anos
  Atsushi Nemoto de62893bc0 [MIPS] local_r4k_flush_cache_page fix %!s(int64=19) %!d(string=hai) anos
  Ralf Baechle 4debe4f963 [MIPS] Initialize S-cache function pointers even on S-cache-less CPUs. %!s(int64=19) %!d(string=hai) anos
  Atsushi Nemoto 41700e7399 [MIPS] Add protected_blast_icache_range, blast_icache_range, etc. %!s(int64=19) %!d(string=hai) anos
  Atsushi Nemoto d4264f1839 [MIPS] Remove wrong __user tags. %!s(int64=19) %!d(string=hai) anos
  Ralf Baechle e7958bb90d MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1. %!s(int64=19) %!d(string=hai) anos
  Ralf Baechle 6ec25809c1 Rename page argument of flush_cache_page to something more descriptive. %!s(int64=19) %!d(string=hai) anos
  Ralf Baechle 02cf211968 Cleanup the mess in cpu_cache_init. %!s(int64=19) %!d(string=hai) anos
  Thiemo Seufer 10a3dabddd Add/Fix missing bit of R4600 hit cacheop workaround. %!s(int64=19) %!d(string=hai) anos
  Thiemo Seufer 02fe2c9ce3 Minor code cleanup. %!s(int64=19) %!d(string=hai) anos
  Thiemo Seufer d8748a3abf More .set push/pop. %!s(int64=19) %!d(string=hai) anos
  Thiemo Seufer 330cfe016b Let r4600 PRID detection match only legacy CPUs, cleanups. %!s(int64=19) %!d(string=hai) anos
  Ralf Baechle 1d40cfcd34 Avoid SMP cacheflushes. This is a minor optimization of startup but %!s(int64=20) %!d(string=hai) anos
  Ralf Baechle e01402b115 More AP / SP bits for the 34K, the Malta bits and things. Still wants %!s(int64=20) %!d(string=hai) anos
  Ralf Baechle ec74e361f1 Mark a few variables __read_mostly. %!s(int64=20) %!d(string=hai) anos
  Ralf Baechle cc61c1fede MIPS R2 instruction hazard handling. %!s(int64=20) %!d(string=hai) anos
  Thiemo Seufer ba5187dbb4 Better interface to run uncached cache setup code. %!s(int64=20) %!d(string=hai) anos
  Ralf Baechle fe00f943e0 Sparseify MIPS. %!s(int64=20) %!d(string=hai) anos
  Pete Popov e3ad1c23ba Base Au1200 2.6 support. %!s(int64=20) %!d(string=hai) anos
  Thiemo Seufer 26a51b270f Use intermediate variable. %!s(int64=20) %!d(string=hai) anos
  Ralf Baechle 79acf83e50 Moves a test which determines if we actually need to perform a %!s(int64=20) %!d(string=hai) anos
  Ralf Baechle c6e8b58771 Update MIPS to use the 4-level pagetable code thereby getting rid of %!s(int64=20) %!d(string=hai) anos
  Ralf Baechle 505403b6a0 25Kf is also physically indexed. %!s(int64=20) %!d(string=hai) anos
  Ralf Baechle a95970f323 20Kc and SB1 don't suffer from aliases. %!s(int64=20) %!d(string=hai) anos
  Ralf Baechle ae6aafe309 Move missplaced code line to the right place. %!s(int64=20) %!d(string=hai) anos
  Ralf Baechle d1e344e500 Use hardware mechanism to deal with cache aliases in the 24K. %!s(int64=20) %!d(string=hai) anos
  Ralf Baechle 28ecca4786 Remove old wrong bits of cache code. %!s(int64=20) %!d(string=hai) anos