 Wu Fengguang
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1202b4c678
drm/i915: rename audio ELD registers
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13 years ago |
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Wu Fengguang
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b3f33cbf7a
drm/i915: fix ELD writing for SandyBridge
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13 years ago |
 Adam Jackson
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3b5c78a35c
drm/i915/dp: Dither down to 6bpc if it makes the mode fit
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13 years ago |
 Jesse Barnes
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7317c75e66
drm/i915: don't set unpin_work if vblank_get fails
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14 years ago |
 Keith Packard
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c0f372b374
drm/i915: By default, enable RC6 on IVB and SNB when reasonable
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13 years ago |
|
Keith Packard
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8d715f0024
drm/i915: add multi-threaded forcewake support
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13 years ago |
|
Keith Packard
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417e822dee
drm/i915: Treat PCH eDP like DP in most places
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13 years ago |
 Eric Anholt
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9ca1d10d74
drm/i915: Turn on another required clock gating bit on gen6.
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13 years ago |
|
Eric Anholt
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406478dc91
drm/i915: Turn on a required 3D clock gating bit on Sandybridge.
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13 years ago |
|
Adam Jackson
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8282049039
drm/i915: intel_choose_pipe_bpp_dither messages should be DRM_DEBUG_KMS
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14 years ago |
 Daniel Vetter
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f74974c763
drm/i915: disable temporal dithering on the internal panel
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14 years ago |
|
Jesse Barnes
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a487928908
drm/i915: remove transcoder PLL mashing from mode_set per specs
|
13 years ago |
|
Jesse Barnes
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4c9c18c293
drm/i915: if transcoder disable fails, say which
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13 years ago |
|
Jesse Barnes
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d6c892df7e
drm/i915: set watermarks for third pipe on IVB
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13 years ago |
|
Jesse Barnes
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d4270e57ef
drm/i915: export a CPT mode set verification function
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14 years ago |
|
Jesse Barnes
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d64311ab4b
drm/i915: fix transcoder PLL select masking
|
13 years ago |
|
Jesse Barnes
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65a21cd653
drm/i915: fix IVB cursor support
|
13 years ago |
|
Jesse Barnes
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f7cb34d47d
drm/i915: fix debug output for 3 pipe configs
|
13 years ago |
|
Jesse Barnes
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4b645f1402
drm/i915: add PLL sharing support to handle 3 pipes
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13 years ago |
|
Jesse Barnes
|
d3ccbe8670
drm/i915: fix PCH PLL assertion check for 3 pipes
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13 years ago |
|
Jesse Barnes
|
d9d444cbc5
drm/i915: split refclk code out of ironlake_crtc_mode_set
|
14 years ago |
|
Jesse Barnes
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27f8227b1e
drm/i915: support 3 pipes on IVB+
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14 years ago |
|
Jesse Barnes
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4c609cb890
drm/i915: PLL macro cleanup and pipe assertion check
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14 years ago |
|
Jesse Barnes
|
c4f9c4c2b3
drm/i915: always set FDI composite sync bit
|
14 years ago |
|
Daniel Vetter
|
6fdd4d98e5
drm/i915: properly cancel rps_work on module unload v2
|
14 years ago |
|
Keith Packard
|
9a1f57808a
Merge branch 'fix-pch-refclk' into foo
|
13 years ago |
|
Keith Packard
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0ac225e569
Merge branch 'drm-intel-fixes' into drm-intel-next
|
14 years ago |
|
Keith Packard
|
9fb526db97
drm/i915: Initialize PCH refclks at modeset init time
|
14 years ago |
|
Keith Packard
|
afffb9dfb6
drm/i915: All PCH refclks are 120MHz
|
14 years ago |
|
Keith Packard
|
99eb6a01e5
drm/i915: Use CK505 as non-SSC source where available
|
14 years ago |
