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@@ -35,20 +35,20 @@ ENTRY(pxa_cpu_standby)
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#ifdef CONFIG_PXA3xx
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-#define MDCNFG 0x0000
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-#define MDCNFG_DMCEN (1 << 30)
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-#define DDR_HCAL 0x0060
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-#define DDR_HCAL_HCRNG 0x1f
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-#define DDR_HCAL_HCPROG (1 << 28)
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-#define DDR_HCAL_HCEN (1 << 31)
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-#define DMCIER 0x0070
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-#define DMCIER_EDLP (1 << 29)
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-#define DMCISR 0x0078
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-#define RCOMP 0x0100
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-#define RCOMP_SWEVAL (1 << 31)
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+#define PXA3_MDCNFG 0x0000
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+#define PXA3_MDCNFG_DMCEN (1 << 30)
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+#define PXA3_DDR_HCAL 0x0060
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+#define PXA3_DDR_HCAL_HCRNG 0x1f
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+#define PXA3_DDR_HCAL_HCPROG (1 << 28)
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+#define PXA3_DDR_HCAL_HCEN (1 << 31)
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+#define PXA3_DMCIER 0x0070
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+#define PXA3_DMCIER_EDLP (1 << 29)
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+#define PXA3_DMCISR 0x0078
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+#define PXA3_RCOMP 0x0100
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+#define PXA3_RCOMP_SWEVAL (1 << 31)
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ENTRY(pm_enter_standby_start)
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- mov r1, #0xf6000000 @ DMEMC_REG_BASE (MDCNFG)
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+ mov r1, #0xf6000000 @ DMEMC_REG_BASE (PXA3_MDCNFG)
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add r1, r1, #0x00100000
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/*
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@@ -59,54 +59,54 @@ ENTRY(pm_enter_standby_start)
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* This also means that only the dynamic memory controller
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* can be reliably accessed in the code following standby.
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*/
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- ldr r2, [r1] @ Dummy read MDCNFG
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+ ldr r2, [r1] @ Dummy read PXA3_MDCNFG
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mcr p14, 0, r0, c7, c0, 0
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.rept 8
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nop
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.endr
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- ldr r0, [r1, #DDR_HCAL] @ Clear (and wait for) HCEN
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- bic r0, r0, #DDR_HCAL_HCEN
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- str r0, [r1, #DDR_HCAL]
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-1: ldr r0, [r1, #DDR_HCAL]
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- tst r0, #DDR_HCAL_HCEN
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+ ldr r0, [r1, #PXA3_DDR_HCAL] @ Clear (and wait for) HCEN
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+ bic r0, r0, #PXA3_DDR_HCAL_HCEN
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+ str r0, [r1, #PXA3_DDR_HCAL]
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+1: ldr r0, [r1, #PXA3_DDR_HCAL]
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+ tst r0, #PXA3_DDR_HCAL_HCEN
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bne 1b
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- ldr r0, [r1, #RCOMP] @ Initiate RCOMP
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- orr r0, r0, #RCOMP_SWEVAL
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- str r0, [r1, #RCOMP]
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+ ldr r0, [r1, #PXA3_RCOMP] @ Initiate RCOMP
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+ orr r0, r0, #PXA3_RCOMP_SWEVAL
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+ str r0, [r1, #PXA3_RCOMP]
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- mov r0, #~0 @ Clear interrupts
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- str r0, [r1, #DMCISR]
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+ mov r0, #~0 @ Clear interrupts
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+ str r0, [r1, #PXA3_DMCISR]
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- ldr r0, [r1, #DMCIER] @ set DMIER[EDLP]
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- orr r0, r0, #DMCIER_EDLP
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- str r0, [r1, #DMCIER]
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+ ldr r0, [r1, #PXA3_DMCIER] @ set DMIER[EDLP]
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+ orr r0, r0, #PXA3_DMCIER_EDLP
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+ str r0, [r1, #PXA3_DMCIER]
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- ldr r0, [r1, #DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN
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- bic r0, r0, #DDR_HCAL_HCRNG
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- orr r0, r0, #DDR_HCAL_HCEN | DDR_HCAL_HCPROG
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- str r0, [r1, #DDR_HCAL]
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+ ldr r0, [r1, #PXA3_DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN
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+ bic r0, r0, #PXA3_DDR_HCAL_HCRNG
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+ orr r0, r0, #PXA3_DDR_HCAL_HCEN | PXA3_DDR_HCAL_HCPROG
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+ str r0, [r1, #PXA3_DDR_HCAL]
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-1: ldr r0, [r1, #DMCISR]
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- tst r0, #DMCIER_EDLP
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+1: ldr r0, [r1, #PXA3_DMCISR]
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+ tst r0, #PXA3_DMCIER_EDLP
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beq 1b
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- ldr r0, [r1, #MDCNFG] @ set MDCNFG[DMCEN]
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- orr r0, r0, #MDCNFG_DMCEN
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- str r0, [r1, #MDCNFG]
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-1: ldr r0, [r1, #MDCNFG]
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- tst r0, #MDCNFG_DMCEN
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+ ldr r0, [r1, #PXA3_MDCNFG] @ set PXA3_MDCNFG[DMCEN]
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+ orr r0, r0, #PXA3_MDCNFG_DMCEN
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+ str r0, [r1, #PXA3_MDCNFG]
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+1: ldr r0, [r1, #PXA3_MDCNFG]
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+ tst r0, #PXA3_MDCNFG_DMCEN
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beq 1b
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- ldr r0, [r1, #DDR_HCAL] @ set DDR_HCAL[HCRNG]
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+ ldr r0, [r1, #PXA3_DDR_HCAL] @ set PXA3_DDR_HCAL[HCRNG]
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orr r0, r0, #2 @ HCRNG
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- str r0, [r1, #DDR_HCAL]
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+ str r0, [r1, #PXA3_DDR_HCAL]
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- ldr r0, [r1, #DMCIER] @ Clear the interrupt
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+ ldr r0, [r1, #PXA3_DMCIER] @ Clear the interrupt
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bic r0, r0, #0x20000000
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- str r0, [r1, #DMCIER]
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+ str r0, [r1, #PXA3_DMCIER]
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mov pc, lr
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ENTRY(pm_enter_standby_end)
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