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@@ -87,11 +87,15 @@ static u64 intel_pmu_raw_event(u64 event)
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{
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#define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL
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#define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL
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+#define CORE_EVNTSEL_EDGE_MASK 0x00040000ULL
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+#define CORE_EVNTSEL_INV_MASK 0x00800000ULL
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#define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL
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#define CORE_EVNTSEL_MASK \
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(CORE_EVNTSEL_EVENT_MASK | \
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CORE_EVNTSEL_UNIT_MASK | \
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+ CORE_EVNTSEL_EDGE_MASK | \
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+ CORE_EVNTSEL_INV_MASK | \
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CORE_EVNTSEL_COUNTER_MASK)
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return event & CORE_EVNTSEL_MASK;
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@@ -119,11 +123,15 @@ static u64 amd_pmu_raw_event(u64 event)
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{
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#define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL
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#define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL
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+#define K7_EVNTSEL_EDGE_MASK 0x000040000ULL
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+#define K7_EVNTSEL_INV_MASK 0x000800000ULL
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#define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL
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#define K7_EVNTSEL_MASK \
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(K7_EVNTSEL_EVENT_MASK | \
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K7_EVNTSEL_UNIT_MASK | \
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+ K7_EVNTSEL_EDGE_MASK | \
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+ K7_EVNTSEL_INV_MASK | \
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K7_EVNTSEL_COUNTER_MASK)
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return event & K7_EVNTSEL_MASK;
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