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@@ -28,17 +28,18 @@
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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-/* Specifics for the Au1xxx Descriptor-Based DMA Controllers, first
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- * seen in the AU1550 part.
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+/*
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+ * Specifics for the Au1xxx Descriptor-Based DMA Controller,
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+ * first seen in the AU1550 part.
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*/
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#ifndef _AU1000_DBDMA_H_
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#define _AU1000_DBDMA_H_
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-
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#ifndef _LANGUAGE_ASSEMBLY
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-/* The DMA base addresses.
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- * The Channels are every 256 bytes (0x0100) from the channel 0 base.
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+/*
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+ * The DMA base addresses.
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+ * The channels are every 256 bytes (0x0100) from the channel 0 base.
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* Interrupt status/enable is bits 15:0 for channels 15 to zero.
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*/
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#define DDMA_GLOBAL_BASE 0xb4003000
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@@ -51,16 +52,14 @@ typedef volatile struct dbdma_global {
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u32 ddma_inten;
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} dbdma_global_t;
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-/* General Configuration.
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-*/
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+/* General Configuration. */
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#define DDMA_CONFIG_AF (1 << 2)
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#define DDMA_CONFIG_AH (1 << 1)
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#define DDMA_CONFIG_AL (1 << 0)
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#define DDMA_THROTTLE_EN (1 << 31)
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-/* The structure of a DMA Channel.
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-*/
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+/* The structure of a DMA Channel. */
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typedef volatile struct au1xxx_dma_channel {
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u32 ddma_cfg; /* See below */
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u32 ddma_desptr; /* 32-byte aligned pointer to descriptor */
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@@ -69,8 +68,7 @@ typedef volatile struct au1xxx_dma_channel {
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u32 ddma_irq; /* If bit 0 set, interrupt pending */
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u32 ddma_stat; /* See below */
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u32 ddma_bytecnt; /* Byte count, valid only when chan idle */
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- /* Remainder, up to the 256 byte boundary, is reserved.
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- */
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+ /* Remainder, up to the 256 byte boundary, is reserved. */
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} au1x_dma_chan_t;
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#define DDMA_CFG_SED (1 << 9) /* source DMA level/edge detect */
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@@ -84,7 +82,8 @@ typedef volatile struct au1xxx_dma_channel {
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#define DDMA_CFG_DBE (1 << 1) /* Destination big endian */
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#define DDMA_CFG_EN (1 << 0) /* Channel enable */
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-/* Always set when descriptor processing done, regardless of
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+/*
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+ * Always set when descriptor processing done, regardless of
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* interrupt enable state. Reflected in global intstat, don't
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* clear this until global intstat is read/used.
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*/
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@@ -94,7 +93,8 @@ typedef volatile struct au1xxx_dma_channel {
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#define DDMA_STAT_V (1 << 1) /* Descriptor valid */
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#define DDMA_STAT_H (1 << 0) /* Channel Halted */
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-/* "Standard" DDMA Descriptor.
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+/*
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+ * "Standard" DDMA Descriptor.
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* Must be 32-byte aligned.
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*/
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typedef volatile struct au1xxx_ddma_desc {
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@@ -106,8 +106,9 @@ typedef volatile struct au1xxx_ddma_desc {
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u32 dscr_dest1; /* See below */
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u32 dscr_stat; /* completion status */
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u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */
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- /* First 32bytes are HW specific!!!
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- Lets have some SW data following.. make sure its 32bytes
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+ /*
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+ * First 32 bytes are HW specific!!!
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+ * Lets have some SW data following -- make sure it's 32 bytes.
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*/
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u32 sw_status;
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u32 sw_context;
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@@ -130,10 +131,9 @@ typedef volatile struct au1xxx_ddma_desc {
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#define DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */
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#define DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */
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-#define SW_STATUS_INUSE (1<<0)
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+#define SW_STATUS_INUSE (1 << 0)
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-/* Command 0 device IDs.
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-*/
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+/* Command 0 device IDs. */
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#ifdef CONFIG_SOC_AU1550
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#define DSCR_CMD0_UART0_TX 0
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#define DSCR_CMD0_UART0_RX 1
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@@ -198,16 +198,15 @@ typedef volatile struct au1xxx_ddma_desc {
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#define DSCR_CMD0_THROTTLE 30
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#define DSCR_CMD0_ALWAYS 31
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#define DSCR_NDEV_IDS 32
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-/* THis macro is used to find/create custom device types */
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-#define DSCR_DEV2CUSTOM_ID(x, d) (((((x)&0xFFFF)<<8)|0x32000000)|((d)&0xFF))
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-#define DSCR_CUSTOM2DEV_ID(x) ((x)&0xFF)
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-
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+/* This macro is used to find/create custom device types */
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+#define DSCR_DEV2CUSTOM_ID(x, d) (((((x) & 0xFFFF) << 8) | 0x32000000) | \
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+ ((d) & 0xFF))
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+#define DSCR_CUSTOM2DEV_ID(x) ((x) & 0xFF)
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#define DSCR_CMD0_SID(x) (((x) & 0x1f) << 25)
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#define DSCR_CMD0_DID(x) (((x) & 0x1f) << 20)
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-/* Source/Destination transfer width.
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-*/
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+/* Source/Destination transfer width. */
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#define DSCR_CMD0_BYTE 0
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#define DSCR_CMD0_HALFWORD 1
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#define DSCR_CMD0_WORD 2
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@@ -215,16 +214,14 @@ typedef volatile struct au1xxx_ddma_desc {
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#define DSCR_CMD0_SW(x) (((x) & 0x3) << 18)
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#define DSCR_CMD0_DW(x) (((x) & 0x3) << 16)
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-/* DDMA Descriptor Type.
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-*/
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+/* DDMA Descriptor Type. */
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#define DSCR_CMD0_STANDARD 0
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#define DSCR_CMD0_LITERAL 1
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#define DSCR_CMD0_CMP_BRANCH 2
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#define DSCR_CMD0_DT(x) (((x) & 0x3) << 13)
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-/* Status Instruction.
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-*/
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+/* Status Instruction. */
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#define DSCR_CMD0_ST_NOCHANGE 0 /* Don't change */
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#define DSCR_CMD0_ST_CURRENT 1 /* Write current status */
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#define DSCR_CMD0_ST_CMD0 2 /* Write cmd0 with V cleared */
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@@ -232,23 +229,20 @@ typedef volatile struct au1xxx_ddma_desc {
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#define DSCR_CMD0_ST(x) (((x) & 0x3) << 0)
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-/* Descriptor Command 1
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-*/
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+/* Descriptor Command 1. */
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#define DSCR_CMD1_SUPTR_MASK (0xf << 28) /* upper 4 bits of src addr */
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#define DSCR_CMD1_DUPTR_MASK (0xf << 24) /* upper 4 bits of dest addr */
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#define DSCR_CMD1_FL_MASK (0x3 << 22) /* Flag bits */
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#define DSCR_CMD1_BC_MASK (0x3fffff) /* Byte count */
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-/* Flag description.
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-*/
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+/* Flag description. */
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#define DSCR_CMD1_FL_MEM_STRIDE0 0
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#define DSCR_CMD1_FL_MEM_STRIDE1 1
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#define DSCR_CMD1_FL_MEM_STRIDE2 2
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#define DSCR_CMD1_FL(x) (((x) & 0x3) << 22)
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-/* Source1, 1-dimensional stride.
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-*/
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+/* Source1, 1-dimensional stride. */
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#define DSCR_SRC1_STS_MASK (3 << 30) /* Src xfer size */
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#define DSCR_SRC1_SAM_MASK (3 << 28) /* Src xfer movement */
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#define DSCR_SRC1_SB_MASK (0x3fff << 14) /* Block size */
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@@ -256,8 +250,7 @@ typedef volatile struct au1xxx_ddma_desc {
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#define DSCR_SRC1_SS_MASK (0x3fff << 0) /* Stride */
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#define DSCR_SRC1_SS(x) (((x) & 0x3fff) << 0)
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-/* Dest1, 1-dimensional stride.
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-*/
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+/* Dest1, 1-dimensional stride. */
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#define DSCR_DEST1_DTS_MASK (3 << 30) /* Dest xfer size */
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#define DSCR_DEST1_DAM_MASK (3 << 28) /* Dest xfer movement */
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#define DSCR_DEST1_DB_MASK (0x3fff << 14) /* Block size */
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@@ -279,29 +272,27 @@ typedef volatile struct au1xxx_ddma_desc {
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#define DSCR_SRC1_SAM(x) (((x) & 3) << 28)
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#define DSCR_DEST1_DAM(x) (((x) & 3) << 28)
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-/* The next descriptor pointer.
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-*/
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+/* The next descriptor pointer. */
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#define DSCR_NXTPTR_MASK (0x07ffffff)
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#define DSCR_NXTPTR(x) ((x) >> 5)
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#define DSCR_GET_NXTPTR(x) ((x) << 5)
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#define DSCR_NXTPTR_MS (1 << 27)
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-/* The number of DBDMA channels.
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-*/
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+/* The number of DBDMA channels. */
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#define NUM_DBDMA_CHANS 16
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/*
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- * Ddma API definitions
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+ * DDMA API definitions
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* FIXME: may not fit to this header file
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*/
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typedef struct dbdma_device_table {
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- u32 dev_id;
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- u32 dev_flags;
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- u32 dev_tsize;
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- u32 dev_devwidth;
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- u32 dev_physaddr; /* If FIFO */
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- u32 dev_intlevel;
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- u32 dev_intpolarity;
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+ u32 dev_id;
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+ u32 dev_flags;
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+ u32 dev_tsize;
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+ u32 dev_devwidth;
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+ u32 dev_physaddr; /* If FIFO */
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+ u32 dev_intlevel;
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+ u32 dev_intpolarity;
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} dbdev_tab_t;
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@@ -316,44 +307,41 @@ typedef struct dbdma_chan_config {
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au1x_ddma_desc_t *chan_desc_base;
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au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr;
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void *chan_callparam;
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- void (*chan_callback)(int, void *);
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+ void (*chan_callback)(int, void *);
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} chan_tab_t;
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#define DEV_FLAGS_INUSE (1 << 0)
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#define DEV_FLAGS_ANYUSE (1 << 1)
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#define DEV_FLAGS_OUT (1 << 2)
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#define DEV_FLAGS_IN (1 << 3)
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-#define DEV_FLAGS_BURSTABLE (1 << 4)
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+#define DEV_FLAGS_BURSTABLE (1 << 4)
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#define DEV_FLAGS_SYNC (1 << 5)
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-/* end Ddma API definitions */
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+/* end DDMA API definitions */
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-/* External functions for drivers to use.
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-*/
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-/* Use this to allocate a dbdma channel. The device ids are one of the
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- * DSCR_CMD0 devices IDs, which is usually redefined to a more
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- * meaningful name. The 'callback' is called during dma completion
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+/*
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+ * External functions for drivers to use.
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+ * Use this to allocate a DBDMA channel. The device IDs are one of
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+ * the DSCR_CMD0 devices IDs, which is usually redefined to a more
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+ * meaningful name. The 'callback' is called during DMA completion
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* interrupt.
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*/
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extern u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
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- void (*callback)(int, void *), void *callparam);
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+ void (*callback)(int, void *),
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+ void *callparam);
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#define DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS
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-/* Set the device width of a in/out fifo.
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-*/
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+/* Set the device width of an in/out FIFO. */
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u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
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-/* Allocate a ring of descriptors for dbdma.
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-*/
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+/* Allocate a ring of descriptors for DBDMA. */
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u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries);
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-/* Put buffers on source/destination descriptors.
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-*/
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+/* Put buffers on source/destination descriptors. */
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u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags);
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u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags);
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-/* Get a buffer from the destination descriptor.
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-*/
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+/* Get a buffer from the destination descriptor. */
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u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes);
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void au1xxx_dbdma_stop(u32 chanid);
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@@ -364,29 +352,34 @@ u32 au1xxx_get_dma_residue(u32 chanid);
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void au1xxx_dbdma_chan_free(u32 chanid);
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void au1xxx_dbdma_dump(u32 chanid);
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-u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr );
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+u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr);
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-u32 au1xxx_ddma_add_device( dbdev_tab_t *dev );
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-void * au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp);
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+u32 au1xxx_ddma_add_device(dbdev_tab_t *dev);
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+void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp);
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/*
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- Some compatibilty macros --
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- Needed to make changes to API without breaking existing drivers
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-*/
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-#define au1xxx_dbdma_put_source(chanid, buf, nbytes)_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE)
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-#define au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags)
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-#define put_source_flags(chanid, buf, nbytes, flags) au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags)
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-
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-
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-#define au1xxx_dbdma_put_dest(chanid, buf, nbytes) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE)
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-#define au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags)
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-#define put_dest_flags(chanid, buf, nbytes, flags) au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags)
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+ * Some compatibilty macros -- needed to make changes to API
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+ * without breaking existing drivers.
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+ */
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+#define au1xxx_dbdma_put_source(chanid, buf, nbytes) \
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+ _au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE)
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+#define au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) \
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+ _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags)
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+#define put_source_flags(chanid, buf, nbytes, flags) \
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+ au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags)
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+
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+#define au1xxx_dbdma_put_dest(chanid, buf, nbytes) \
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+ _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE)
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+#define au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) \
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+ _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags)
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+#define put_dest_flags(chanid, buf, nbytes, flags) \
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+ au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags)
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/*
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* Flags for the put_source/put_dest functions.
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*/
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-#define DDMA_FLAGS_IE (1<<0)
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-#define DDMA_FLAGS_NOIE (1<<1)
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+#define DDMA_FLAGS_IE (1 << 0)
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+#define DDMA_FLAGS_NOIE (1 << 1)
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#endif /* _LANGUAGE_ASSEMBLY */
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#endif /* _AU1000_DBDMA_H_ */
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Sergei Shtylyov