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+/*
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+ * Copyright 2013 Red Hat Inc.
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+ *
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+ * Permission is hereby granted, free of charge, to any person obtaining a
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+ * copy of this software and associated documentation files (the "Software"),
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+ * to deal in the Software without restriction, including without limitation
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+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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+ * and/or sell copies of the Software, and to permit persons to whom the
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+ * Software is furnished to do so, subject to the following conditions:
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+ *
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+ * The above copyright notice and this permission notice shall be included in
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+ * all copies or substantial portions of the Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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+ * OTHER DEALINGS IN THE SOFTWARE.
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+ *
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+ * Authors: Ben Skeggs
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+ */
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+
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+#include <subdev/pwr.h>
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+#include <subdev/timer.h>
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+
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+static int
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+nouveau_pwr_send(struct nouveau_pwr *ppwr, u32 reply[2],
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+ u32 process, u32 message, u32 data0, u32 data1)
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+{
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+ struct nouveau_subdev *subdev = nv_subdev(ppwr);
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+ u32 addr;
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+
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+ /* we currently only support a single process at a time waiting
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+ * on a synchronous reply, take the PPWR mutex and tell the
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+ * receive handler what we're waiting for
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+ */
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+ if (reply) {
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+ mutex_lock(&subdev->mutex);
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+ ppwr->recv.message = message;
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+ ppwr->recv.process = process;
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+ }
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+
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+ /* wait for a free slot in the fifo */
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+ addr = nv_rd32(ppwr, 0x10a4a0);
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+ if (!nv_wait_ne(ppwr, 0x10a4b0, 0xffffffff, addr ^ 8))
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+ return -EBUSY;
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+
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+ /* acquire data segment access */
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+ do {
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+ nv_wr32(ppwr, 0x10a580, 0x00000001);
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+ } while (nv_rd32(ppwr, 0x10a580) != 0x00000001);
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+
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+ /* write the packet */
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+ nv_wr32(ppwr, 0x10a1c0, 0x01000000 | (((addr & 0x07) << 4) +
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+ ppwr->send.base));
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+ nv_wr32(ppwr, 0x10a1c4, process);
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+ nv_wr32(ppwr, 0x10a1c4, message);
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+ nv_wr32(ppwr, 0x10a1c4, data0);
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+ nv_wr32(ppwr, 0x10a1c4, data1);
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+ nv_wr32(ppwr, 0x10a4a0, (addr + 1) & 0x0f);
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+
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+ /* release data segment access */
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+ nv_wr32(ppwr, 0x10a580, 0x00000000);
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+
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+ /* wait for reply, if requested */
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+ if (reply) {
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+ wait_event(ppwr->recv.wait, (ppwr->recv.process == 0));
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+ reply[0] = ppwr->recv.data[0];
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+ reply[1] = ppwr->recv.data[1];
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+ mutex_unlock(&subdev->mutex);
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+ }
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+
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+ return 0;
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+}
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+
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+static void
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+nouveau_pwr_recv(struct work_struct *work)
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+{
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+ struct nouveau_pwr *ppwr =
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+ container_of(work, struct nouveau_pwr, recv.work);
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+ u32 process, message, data0, data1;
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+
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+ /* nothing to do if GET == PUT */
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+ u32 addr = nv_rd32(ppwr, 0x10a4cc);
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+ if (addr == nv_rd32(ppwr, 0x10a4c8))
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+ return;
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+
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+ /* acquire data segment access */
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+ do {
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+ nv_wr32(ppwr, 0x10a580, 0x00000002);
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+ } while (nv_rd32(ppwr, 0x10a580) != 0x00000002);
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+
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+ /* read the packet */
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+ nv_wr32(ppwr, 0x10a1c0, 0x02000000 | (((addr & 0x07) << 4) +
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+ ppwr->recv.base));
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+ process = nv_rd32(ppwr, 0x10a1c4);
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+ message = nv_rd32(ppwr, 0x10a1c4);
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+ data0 = nv_rd32(ppwr, 0x10a1c4);
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+ data1 = nv_rd32(ppwr, 0x10a1c4);
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+ nv_wr32(ppwr, 0x10a4cc, (addr + 1) & 0x0f);
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+
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+ /* release data segment access */
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+ nv_wr32(ppwr, 0x10a580, 0x00000000);
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+
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+ /* wake process if it's waiting on a synchronous reply */
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+ if (ppwr->recv.process) {
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+ if (process == ppwr->recv.process &&
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+ message == ppwr->recv.message) {
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+ ppwr->recv.data[0] = data0;
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+ ppwr->recv.data[1] = data1;
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+ ppwr->recv.process = 0;
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+ wake_up(&ppwr->recv.wait);
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+ return;
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+ }
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+ }
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+
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+ /* right now there's no other expected responses from the engine,
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+ * so assume that any unexpected message is an error.
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+ */
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+ nv_warn(ppwr, "%c%c%c%c 0x%08x 0x%08x 0x%08x 0x%08x\n",
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+ (char)((process & 0x000000ff) >> 0),
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+ (char)((process & 0x0000ff00) >> 8),
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+ (char)((process & 0x00ff0000) >> 16),
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+ (char)((process & 0xff000000) >> 24),
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+ process, message, data0, data1);
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+}
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+
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+static void
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+nouveau_pwr_intr(struct nouveau_subdev *subdev)
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+{
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+ struct nouveau_pwr *ppwr = (void *)subdev;
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+ u32 disp = nv_rd32(ppwr, 0x10a01c);
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+ u32 intr = nv_rd32(ppwr, 0x10a008) & disp & ~(disp >> 16);
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+
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+ if (intr & 0x00000020) {
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+ u32 stat = nv_rd32(ppwr, 0x10a16c);
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+ if (stat & 0x80000000) {
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+ nv_error(ppwr, "UAS fault at 0x%06x addr 0x%08x\n",
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+ stat & 0x00ffffff, nv_rd32(ppwr, 0x10a168));
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+ nv_wr32(ppwr, 0x10a16c, 0x00000000);
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+ intr &= ~0x00000020;
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+ }
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+ }
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+
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+ if (intr & 0x00000040) {
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+ schedule_work(&ppwr->recv.work);
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+ nv_wr32(ppwr, 0x10a004, 0x00000040);
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+ intr &= ~0x00000040;
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+ }
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+
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+ if (intr & 0x00000080) {
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+ nv_info(ppwr, "wr32 0x%06x 0x%08x\n", nv_rd32(ppwr, 0x10a7a0),
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+ nv_rd32(ppwr, 0x10a7a4));
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+ nv_wr32(ppwr, 0x10a004, 0x00000080);
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+ intr &= ~0x00000080;
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+ }
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+
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+ if (intr) {
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+ nv_error(ppwr, "intr 0x%08x\n", intr);
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+ nv_wr32(ppwr, 0x10a004, intr);
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+ }
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+}
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+
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+int
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+_nouveau_pwr_fini(struct nouveau_object *object, bool suspend)
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+{
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+ struct nouveau_pwr *ppwr = (void *)object;
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+
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+ nv_wr32(ppwr, 0x10a014, 0x00000060);
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+ flush_work(&ppwr->recv.work);
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+
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+ return nouveau_subdev_fini(&ppwr->base, suspend);
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+}
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+
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+int
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+_nouveau_pwr_init(struct nouveau_object *object)
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+{
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+ struct nouveau_pwr *ppwr = (void *)object;
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+ int ret, i;
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+
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+ ret = nouveau_subdev_init(&ppwr->base);
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+ if (ret)
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+ return ret;
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+
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+ nv_subdev(ppwr)->intr = nouveau_pwr_intr;
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+ ppwr->message = nouveau_pwr_send;
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+
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+ /* prevent previous ucode from running, wait for idle, reset */
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+ nv_wr32(ppwr, 0x10a014, 0x0000ffff); /* INTR_EN_CLR = ALL */
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+ nv_wait(ppwr, 0x10a04c, 0xffffffff, 0x00000000);
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+ nv_mask(ppwr, 0x000200, 0x00002000, 0x00000000);
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+ nv_mask(ppwr, 0x000200, 0x00002000, 0x00002000);
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+
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+ /* upload data segment */
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+ nv_wr32(ppwr, 0x10a1c0, 0x01000000);
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+ for (i = 0; i < ppwr->data.size / 4; i++)
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+ nv_wr32(ppwr, 0x10a1c4, ppwr->data.data[i]);
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+
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+ /* upload code segment */
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+ nv_wr32(ppwr, 0x10a180, 0x01000000);
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+ for (i = 0; i < ppwr->code.size / 4; i++) {
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+ if ((i & 0x3f) == 0)
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+ nv_wr32(ppwr, 0x10a188, i >> 6);
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+ nv_wr32(ppwr, 0x10a184, ppwr->code.data[i]);
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+ }
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+
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+ /* start it running */
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+ nv_wr32(ppwr, 0x10a10c, 0x00000000);
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+ nv_wr32(ppwr, 0x10a104, 0x00000000);
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+ nv_wr32(ppwr, 0x10a100, 0x00000002);
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+
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+ /* wait for valid host->pwr ring configuration */
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+ if (!nv_wait_ne(ppwr, 0x10a4d0, 0xffffffff, 0x00000000))
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+ return -EBUSY;
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+ ppwr->send.base = nv_rd32(ppwr, 0x10a4d0) & 0x0000ffff;
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+ ppwr->send.size = nv_rd32(ppwr, 0x10a4d0) >> 16;
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+
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+ /* wait for valid pwr->host ring configuration */
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+ if (!nv_wait_ne(ppwr, 0x10a4dc, 0xffffffff, 0x00000000))
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+ return -EBUSY;
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+ ppwr->recv.base = nv_rd32(ppwr, 0x10a4dc) & 0x0000ffff;
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+ ppwr->recv.size = nv_rd32(ppwr, 0x10a4dc) >> 16;
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+
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+ nv_wr32(ppwr, 0x10a010, 0x000000e0);
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+ return 0;
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+}
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+
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+int
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+nouveau_pwr_create_(struct nouveau_object *parent,
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+ struct nouveau_object *engine,
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+ struct nouveau_oclass *oclass, int length, void **pobject)
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+{
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+ struct nouveau_pwr *ppwr;
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+ int ret;
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+
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+ ret = nouveau_subdev_create_(parent, engine, oclass, 0, "PPWR",
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+ "pwr", length, pobject);
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+ ppwr = *pobject;
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+ if (ret)
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+ return ret;
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+
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+ INIT_WORK(&ppwr->recv.work, nouveau_pwr_recv);
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+ init_waitqueue_head(&ppwr->recv.wait);
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+ return 0;
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+}
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