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@@ -10,8 +10,8 @@ Currently this network device driver is for all STM embedded MAC/GMAC
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(i.e. 7xxx/5xxx SoCs), SPEAr (arm), Loongson1B (mips) and XLINX XC2V3000
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FF1152AMT0221 D1215994A VIRTEX FPGA board.
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-DWC Ether MAC 10/100/1000 Universal version 3.60a (and older) and DWC Ether MAC 10/100
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-Universal version 4.0 have been used for developing this driver.
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+DWC Ether MAC 10/100/1000 Universal version 3.60a (and older) and DWC Ether
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+MAC 10/100 Universal version 4.0 have been used for developing this driver.
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This driver supports both the platform bus and PCI.
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@@ -54,27 +54,27 @@ net_device structure enabling the scatter/gather feature.
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When one or more packets are received, an interrupt happens. The interrupts
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are not queued so the driver has to scan all the descriptors in the ring during
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the receive process.
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-This is based on NAPI so the interrupt handler signals only if there is work to be
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-done, and it exits.
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+This is based on NAPI so the interrupt handler signals only if there is work
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+to be done, and it exits.
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Then the poll method will be scheduled at some future point.
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The incoming packets are stored, by the DMA, in a list of pre-allocated socket
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buffers in order to avoid the memcpy (Zero-copy).
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4.3) Timer-Driver Interrupt
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-Instead of having the device that asynchronously notifies the frame receptions, the
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-driver configures a timer to generate an interrupt at regular intervals.
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-Based on the granularity of the timer, the frames that are received by the device
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-will experience different levels of latency. Some NICs have dedicated timer
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-device to perform this task. STMMAC can use either the RTC device or the TMU
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-channel 2 on STLinux platforms.
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+Instead of having the device that asynchronously notifies the frame receptions,
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+the driver configures a timer to generate an interrupt at regular intervals.
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+Based on the granularity of the timer, the frames that are received by the
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+device will experience different levels of latency. Some NICs have dedicated
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+timer device to perform this task. STMMAC can use either the RTC device or the
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+TMU channel 2 on STLinux platforms.
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The timers frequency can be passed to the driver as parameter; when change it,
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take care of both hardware capability and network stability/performance impact.
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-Several performance tests on STM platforms showed this optimisation allows to spare
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-the CPU while having the maximum throughput.
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+Several performance tests on STM platforms showed this optimisation allows to
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+spare the CPU while having the maximum throughput.
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4.4) WOL
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-Wake up on Lan feature through Magic and Unicast frames are supported for the GMAC
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-core.
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+Wake up on Lan feature through Magic and Unicast frames are supported for the
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+GMAC core.
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4.5) DMA descriptors
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Driver handles both normal and enhanced descriptors. The latter has been only
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@@ -106,7 +106,8 @@ Several driver's information can be passed through the platform
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These are included in the include/linux/stmmac.h header file
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and detailed below as well:
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- struct plat_stmmacenet_data {
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+struct plat_stmmacenet_data {
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+ char *phy_bus_name;
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int bus_id;
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int phy_addr;
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int interface;
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@@ -124,19 +125,24 @@ and detailed below as well:
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void (*bus_setup)(void __iomem *ioaddr);
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int (*init)(struct platform_device *pdev);
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void (*exit)(struct platform_device *pdev);
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+ void *custom_cfg;
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+ void *custom_data;
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void *bsp_priv;
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};
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Where:
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+ o phy_bus_name: phy bus name to attach to the stmmac.
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o bus_id: bus identifier.
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o phy_addr: the physical address can be passed from the platform.
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If it is set to -1 the driver will automatically
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detect it at run-time by probing all the 32 addresses.
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o interface: PHY device's interface.
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o mdio_bus_data: specific platform fields for the MDIO bus.
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- o pbl: the Programmable Burst Length is maximum number of beats to
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+ o dma_cfg: internal DMA parameters
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+ o pbl: the Programmable Burst Length is maximum number of beats to
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be transferred in one DMA transaction.
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GMAC also enables the 4xPBL by default.
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+ o fixed_burst/mixed_burst/burst_len
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o clk_csr: fixed CSR Clock range selection.
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o has_gmac: uses the GMAC core.
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o enh_desc: if sets the MAC will use the enhanced descriptor structure.
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@@ -160,8 +166,9 @@ Where:
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this is sometime necessary on some platforms (e.g. ST boxes)
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where the HW needs to have set some PIO lines or system cfg
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registers.
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- o custom_cfg: this is a custom configuration that can be passed while
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- initialising the resources.
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+ o custom_cfg/custom_data: this is a custom configuration that can be passed
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+ while initialising the resources.
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+ o bsp_priv: another private poiter.
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For MDIO bus The we have:
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@@ -180,7 +187,6 @@ Where:
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o irqs: list of IRQs, one per PHY.
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o probed_phy_irq: if irqs is NULL, use this for probed PHY.
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-
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For DMA engine we have the following internal fields that should be
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tuned according to the HW capabilities.
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