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@@ -26,9 +26,13 @@
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#include <asm/rtc.h>
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#define DRV_NAME "sh-rtc"
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-#define DRV_VERSION "0.1.4"
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+#define DRV_VERSION "0.1.5"
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-#ifdef CONFIG_CPU_SH3
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+#ifdef CONFIG_CPU_SH2A
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+#define rtc_reg_size sizeof(u16)
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+#define RTC_BIT_INVERTED 0
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+#define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR
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+#elif defined(CONFIG_CPU_SH3)
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#define rtc_reg_size sizeof(u16)
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#define RTC_BIT_INVERTED 0 /* No bug on SH7708, SH7709A */
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#define RTC_DEF_CAPABILITIES 0UL
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@@ -62,6 +66,18 @@
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#define RCR1 RTC_REG(14) /* Control */
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#define RCR2 RTC_REG(15) /* Control */
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+/*
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+ * Note on RYRAR and RCR3: Up until this point most of the register
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+ * definitions are consistent across all of the available parts. However,
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+ * the placement of the optional RYRAR and RCR3 (the RYRAR control
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+ * register used to control RYRCNT/RYRAR compare) varies considerably
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+ * across various parts, occasionally being mapped in to a completely
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+ * unrelated address space. For proper RYRAR support a separate resource
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+ * would have to be handed off, but as this is purely optional in
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+ * practice, we simply opt not to support it, thereby keeping the code
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+ * quite a bit more simplified.
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+ */
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+
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/* ALARM Bits - or with BCD encoded value */
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#define AR_ENB 0x80 /* Enable for alarm cmp */
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