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@@ -128,6 +128,8 @@ static void b44_init_rings(struct b44 *);
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#define B44_FULL_RESET 1
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#define B44_FULL_RESET_SKIP_PHY 2
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#define B44_PARTIAL_RESET 3
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+#define B44_CHIP_RESET_FULL 4
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+#define B44_CHIP_RESET_PARTIAL 5
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static void b44_init_hw(struct b44 *, int);
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@@ -1259,7 +1261,7 @@ static void b44_clear_stats(struct b44 *bp)
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}
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/* bp->lock is held. */
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-static void b44_chip_reset(struct b44 *bp)
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+static void b44_chip_reset(struct b44 *bp, int reset_kind)
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{
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struct ssb_device *sdev = bp->sdev;
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@@ -1281,6 +1283,13 @@ static void b44_chip_reset(struct b44 *bp)
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ssb_device_enable(bp->sdev, 0);
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b44_clear_stats(bp);
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+ /*
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+ * Don't enable PHY if we are doing a partial reset
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+ * we are probably going to power down
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+ */
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+ if (reset_kind == B44_CHIP_RESET_PARTIAL)
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+ return;
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+
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switch (sdev->bus->bustype) {
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case SSB_BUSTYPE_SSB:
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bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
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@@ -1316,7 +1325,14 @@ static void b44_chip_reset(struct b44 *bp)
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static void b44_halt(struct b44 *bp)
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{
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b44_disable_ints(bp);
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- b44_chip_reset(bp);
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+ /* reset PHY */
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+ b44_phy_reset(bp);
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+ /* power down PHY */
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+ printk(KERN_INFO PFX "%s: powering down PHY\n", bp->dev->name);
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+ bw32(bp, B44_MAC_CTRL, MAC_CTRL_PHY_PDOWN);
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+ /* now reset the chip, but without enabling the MAC&PHY
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+ * part of it. This has to be done _after_ we shut down the PHY */
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+ b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
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}
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/* bp->lock is held. */
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@@ -1365,7 +1381,7 @@ static void b44_init_hw(struct b44 *bp, int reset_kind)
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{
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u32 val;
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- b44_chip_reset(bp);
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+ b44_chip_reset(bp, B44_CHIP_RESET_FULL);
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if (reset_kind == B44_FULL_RESET) {
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b44_phy_reset(bp);
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b44_setup_phy(bp);
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@@ -1422,7 +1438,7 @@ static int b44_open(struct net_device *dev)
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err = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
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if (unlikely(err < 0)) {
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napi_disable(&bp->napi);
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- b44_chip_reset(bp);
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+ b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
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b44_free_rings(bp);
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b44_free_consistent(bp);
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goto out;
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@@ -2188,7 +2204,7 @@ static int __devinit b44_init_one(struct ssb_device *sdev,
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/* Chip reset provides power to the b44 MAC & PCI cores, which
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* is necessary for MAC register access.
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*/
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- b44_chip_reset(bp);
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+ b44_chip_reset(bp, B44_CHIP_RESET_FULL);
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printk(KERN_INFO "%s: Broadcom 44xx/47xx 10/100BaseT Ethernet %s\n",
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dev->name, print_mac(mac, dev->dev_addr));
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@@ -2212,6 +2228,7 @@ static void __devexit b44_remove_one(struct ssb_device *sdev)
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unregister_netdev(dev);
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ssb_bus_may_powerdown(sdev->bus);
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free_netdev(dev);
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+ ssb_pcihost_set_power_state(sdev, PCI_D3hot);
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ssb_set_drvdata(sdev, NULL);
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}
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@@ -2240,6 +2257,7 @@ static int b44_suspend(struct ssb_device *sdev, pm_message_t state)
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b44_setup_wol(bp);
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}
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+ ssb_pcihost_set_power_state(sdev, PCI_D3hot);
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return 0;
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}
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