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@@ -110,9 +110,10 @@
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/*
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* iwl_rxq_space - Return number of free slots available in queue.
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*/
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-static int iwl_rxq_space(const struct iwl_rxq *q)
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+static int iwl_rxq_space(const struct iwl_rxq *rxq)
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{
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- int s = q->read - q->write;
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+ int s = rxq->read - rxq->write;
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+
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if (s <= 0)
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s += RX_QUEUE_SIZE;
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/* keep some buffer to not confuse full and empty queue */
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@@ -143,21 +144,22 @@ int iwl_pcie_rx_stop(struct iwl_trans *trans)
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/*
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* iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue
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*/
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-static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_rxq *q)
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+static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans,
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+ struct iwl_rxq *rxq)
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{
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unsigned long flags;
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u32 reg;
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- spin_lock_irqsave(&q->lock, flags);
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+ spin_lock_irqsave(&rxq->lock, flags);
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- if (q->need_update == 0)
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+ if (rxq->need_update == 0)
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goto exit_unlock;
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if (trans->cfg->base_params->shadow_reg_enable) {
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/* shadow register enabled */
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/* Device expects a multiple of 8 */
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- q->write_actual = (q->write & ~0x7);
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- iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, q->write_actual);
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+ rxq->write_actual = (rxq->write & ~0x7);
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+ iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual);
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} else {
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struct iwl_trans_pcie *trans_pcie =
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IWL_TRANS_GET_PCIE_TRANS(trans);
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@@ -175,22 +177,22 @@ static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_rxq *q)
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goto exit_unlock;
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}
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- q->write_actual = (q->write & ~0x7);
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+ rxq->write_actual = (rxq->write & ~0x7);
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iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
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- q->write_actual);
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+ rxq->write_actual);
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/* Else device is assumed to be awake */
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} else {
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/* Device expects a multiple of 8 */
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- q->write_actual = (q->write & ~0x7);
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+ rxq->write_actual = (rxq->write & ~0x7);
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iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
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- q->write_actual);
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+ rxq->write_actual);
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}
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}
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- q->need_update = 0;
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+ rxq->need_update = 0;
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exit_unlock:
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- spin_unlock_irqrestore(&q->lock, flags);
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+ spin_unlock_irqrestore(&rxq->lock, flags);
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}
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/*
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