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@@ -149,8 +149,6 @@ enum StirFifoCtlMask {
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FIFOCTL_DIR = 0x10,
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FIFOCTL_CLR = 0x08,
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FIFOCTL_EMPTY = 0x04,
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- FIFOCTL_RXERR = 0x02,
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- FIFOCTL_TXERR = 0x01,
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};
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enum StirDiagMask {
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@@ -615,19 +613,6 @@ static int fifo_txwait(struct stir_cb *stir, int space)
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pr_debug("fifo status 0x%lx count %lu\n", status, count);
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- /* error when receive/transmit fifo gets confused */
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- if (status & FIFOCTL_RXERR) {
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- stir->stats.rx_fifo_errors++;
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- stir->stats.rx_errors++;
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- break;
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- }
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-
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- if (status & FIFOCTL_TXERR) {
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- stir->stats.tx_fifo_errors++;
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- stir->stats.tx_errors++;
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- break;
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- }
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-
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/* is fifo receiving already, or empty */
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if (!(status & FIFOCTL_DIR)
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|| (status & FIFOCTL_EMPTY))
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