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@@ -886,7 +886,10 @@ void NVCalcStateExt(struct nvidia_par *par,
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case NV_ARCH_20:
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case NV_ARCH_30:
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default:
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- if (((par->Chipset & 0xffff) == 0x01A0) ||
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+ if ((par->Chipset & 0xfff0) == 0x0240) {
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+ state->arbitration0 = 256;
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+ state->arbitration1 = 0x0480;
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+ } else if (((par->Chipset & 0xffff) == 0x01A0) ||
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((par->Chipset & 0xffff) == 0x01f0)) {
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nForceUpdateArbitrationSettings(VClk,
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pixelDepth * 8,
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@@ -1235,6 +1238,7 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
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break;
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case 0x0160:
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case 0x01D0:
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+ case 0x0240:
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NV_WR32(par->PMC, 0x1700,
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NV_RD32(par->PFB, 0x020C));
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NV_WR32(par->PMC, 0x1704, 0);
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@@ -1359,7 +1363,9 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
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if(((par->Chipset & 0xfff0)
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!= 0x0160) &&
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((par->Chipset & 0xfff0)
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- != 0x0220))
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+ != 0x0220) &&
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+ ((par->Chipset & 0xfff0)
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+ != 0x240))
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NV_WR32(par->PGRAPH,
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0x6900 + i*4,
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NV_RD32(par->PFB,
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