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@@ -39,6 +39,7 @@
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#define MDSTAT 0x800
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#define MDSTAT 0x800
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#define MDCTL 0xA00
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#define MDCTL 0xA00
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+#define MDSTAT_STATE_MASK 0x1f
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/* Return nonzero iff the domain's clock is active */
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/* Return nonzero iff the domain's clock is active */
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int __init davinci_psc_is_clk_active(unsigned int id)
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int __init davinci_psc_is_clk_active(unsigned int id)
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@@ -53,14 +54,13 @@ int __init davinci_psc_is_clk_active(unsigned int id)
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/* Enable or disable a PSC domain */
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/* Enable or disable a PSC domain */
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void davinci_psc_config(unsigned int domain, unsigned int id, char enable)
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void davinci_psc_config(unsigned int domain, unsigned int id, char enable)
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{
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{
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- u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl, mdstat_mask;
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+ u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl;
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void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE);
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void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE);
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+ u32 next_state = enable ? 0x3 : 0x2; /* 0x3 enables, 0x2 disables */
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mdctl = __raw_readl(psc_base + MDCTL + 4 * id);
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mdctl = __raw_readl(psc_base + MDCTL + 4 * id);
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- if (enable)
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- mdctl |= 0x00000003; /* Enable Module */
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- else
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- mdctl &= 0xFFFFFFE2; /* Disable Module */
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+ mdctl &= ~MDSTAT_STATE_MASK;
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+ mdctl |= next_state;
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__raw_writel(mdctl, psc_base + MDCTL + 4 * id);
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__raw_writel(mdctl, psc_base + MDCTL + 4 * id);
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pdstat = __raw_readl(psc_base + PDSTAT);
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pdstat = __raw_readl(psc_base + PDSTAT);
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@@ -93,12 +93,7 @@ void davinci_psc_config(unsigned int domain, unsigned int id, char enable)
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} while (!(((ptstat >> domain) & 1) == 0));
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} while (!(((ptstat >> domain) & 1) == 0));
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}
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}
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- if (enable)
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- mdstat_mask = 0x3;
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- else
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- mdstat_mask = 0x2;
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-
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do {
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do {
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mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
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mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
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- } while (!((mdstat & 0x0000001F) == mdstat_mask));
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+ } while (!((mdstat & MDSTAT_STATE_MASK) == next_state));
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}
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}
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