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@@ -7298,7 +7298,7 @@ void intel_enable_clock_gating(struct drm_device *dev)
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_3D_CHICKEN2_WM_READ_PIPELINED);
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}
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- if (IS_GEN6(dev)) {
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+ if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
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I915_WRITE(WM3_LP_ILK, 0);
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I915_WRITE(WM2_LP_ILK, 0);
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I915_WRITE(WM1_LP_ILK, 0);
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@@ -7560,6 +7560,13 @@ static void intel_init_display(struct drm_device *dev)
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} else if (IS_IVYBRIDGE(dev)) {
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/* FIXME: detect B0+ stepping and use auto training */
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dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
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+ if (SNB_READ_WM0_LATENCY()) {
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+ dev_priv->display.update_wm = sandybridge_update_wm;
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+ } else {
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+ DRM_DEBUG_KMS("Failed to read display plane latency. "
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+ "Disable CxSR\n");
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+ dev_priv->display.update_wm = NULL;
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+ }
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} else
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dev_priv->display.update_wm = NULL;
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} else if (IS_PINEVIEW(dev)) {
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