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@@ -0,0 +1,572 @@
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+/*
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+ * omap_uwire.c -- MicroWire interface driver for OMAP
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+ *
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+ * Copyright 2003 MontaVista Software Inc. <source@mvista.com>
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+ *
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+ * Ported to 2.6 OMAP uwire interface.
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+ * Copyright (C) 2004 Texas Instruments.
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+ *
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+ * Generalization patches by Juha Yrjola <juha.yrjola@nokia.com>
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+ *
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+ * Copyright (C) 2005 David Brownell (ported to 2.6 SPI interface)
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+ * Copyright (C) 2006 Nokia
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+ *
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+ * Many updates by Imre Deak <imre.deak@nokia.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the
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+ * Free Software Foundation; either version 2 of the License, or (at your
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+ * option) any later version.
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+ *
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+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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+ *
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+ * You should have received a copy of the GNU General Public License along
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+ * with this program; if not, write to the Free Software Foundation, Inc.,
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+ * 675 Mass Ave, Cambridge, MA 02139, USA.
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+ */
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+#include <linux/kernel.h>
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+#include <linux/init.h>
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+#include <linux/delay.h>
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+#include <linux/platform_device.h>
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+#include <linux/workqueue.h>
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+#include <linux/interrupt.h>
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+#include <linux/err.h>
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+#include <linux/clk.h>
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+
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+#include <linux/spi/spi.h>
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+#include <linux/spi/spi_bitbang.h>
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+
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+#include <asm/system.h>
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+#include <asm/irq.h>
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+#include <asm/hardware.h>
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+#include <asm/io.h>
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+#include <asm/mach-types.h>
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+
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+#include <asm/arch/mux.h>
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+#include <asm/arch/omap730.h> /* OMAP730_IO_CONF registers */
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+
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+
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+/* FIXME address is now a platform device resource,
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+ * and irqs should show there too...
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+ */
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+#define UWIRE_BASE_PHYS 0xFFFB3000
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+#define UWIRE_BASE ((void *__iomem)IO_ADDRESS(UWIRE_BASE_PHYS))
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+
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+/* uWire Registers: */
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+#define UWIRE_IO_SIZE 0x20
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+#define UWIRE_TDR 0x00
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+#define UWIRE_RDR 0x00
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+#define UWIRE_CSR 0x01
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+#define UWIRE_SR1 0x02
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+#define UWIRE_SR2 0x03
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+#define UWIRE_SR3 0x04
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+#define UWIRE_SR4 0x05
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+#define UWIRE_SR5 0x06
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+
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+/* CSR bits */
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+#define RDRB (1 << 15)
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+#define CSRB (1 << 14)
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+#define START (1 << 13)
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+#define CS_CMD (1 << 12)
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+
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+/* SR1 or SR2 bits */
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+#define UWIRE_READ_FALLING_EDGE 0x0001
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+#define UWIRE_READ_RISING_EDGE 0x0000
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+#define UWIRE_WRITE_FALLING_EDGE 0x0000
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+#define UWIRE_WRITE_RISING_EDGE 0x0002
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+#define UWIRE_CS_ACTIVE_LOW 0x0000
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+#define UWIRE_CS_ACTIVE_HIGH 0x0004
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+#define UWIRE_FREQ_DIV_2 0x0000
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+#define UWIRE_FREQ_DIV_4 0x0008
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+#define UWIRE_FREQ_DIV_8 0x0010
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+#define UWIRE_CHK_READY 0x0020
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+#define UWIRE_CLK_INVERTED 0x0040
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+
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+
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+struct uwire_spi {
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+ struct spi_bitbang bitbang;
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+ struct clk *ck;
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+};
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+
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+struct uwire_state {
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+ unsigned bits_per_word;
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+ unsigned div1_idx;
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+};
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+
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+/* REVISIT compile time constant for idx_shift? */
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+static unsigned int uwire_idx_shift;
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+
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+static inline void uwire_write_reg(int idx, u16 val)
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+{
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+ __raw_writew(val, UWIRE_BASE + (idx << uwire_idx_shift));
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+}
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+
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+static inline u16 uwire_read_reg(int idx)
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+{
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+ return __raw_readw(UWIRE_BASE + (idx << uwire_idx_shift));
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+}
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+
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+static inline void omap_uwire_configure_mode(u8 cs, unsigned long flags)
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+{
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+ u16 w, val = 0;
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+ int shift, reg;
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+
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+ if (flags & UWIRE_CLK_INVERTED)
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+ val ^= 0x03;
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+ val = flags & 0x3f;
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+ if (cs & 1)
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+ shift = 6;
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+ else
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+ shift = 0;
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+ if (cs <= 1)
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+ reg = UWIRE_SR1;
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+ else
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+ reg = UWIRE_SR2;
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+
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+ w = uwire_read_reg(reg);
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+ w &= ~(0x3f << shift);
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+ w |= val << shift;
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+ uwire_write_reg(reg, w);
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+}
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+
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+static int wait_uwire_csr_flag(u16 mask, u16 val, int might_not_catch)
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+{
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+ u16 w;
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+ int c = 0;
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+ unsigned long max_jiffies = jiffies + HZ;
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+
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+ for (;;) {
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+ w = uwire_read_reg(UWIRE_CSR);
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+ if ((w & mask) == val)
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+ break;
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+ if (time_after(jiffies, max_jiffies)) {
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+ printk(KERN_ERR "%s: timeout. reg=%#06x "
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+ "mask=%#06x val=%#06x\n",
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+ __FUNCTION__, w, mask, val);
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+ return -1;
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+ }
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+ c++;
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+ if (might_not_catch && c > 64)
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+ break;
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+ }
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+ return 0;
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+}
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+
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+static void uwire_set_clk1_div(int div1_idx)
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+{
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+ u16 w;
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+
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+ w = uwire_read_reg(UWIRE_SR3);
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+ w &= ~(0x03 << 1);
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+ w |= div1_idx << 1;
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+ uwire_write_reg(UWIRE_SR3, w);
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+}
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+
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+static void uwire_chipselect(struct spi_device *spi, int value)
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+{
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+ struct uwire_state *ust = spi->controller_state;
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+ u16 w;
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+ int old_cs;
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+
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+
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+ BUG_ON(wait_uwire_csr_flag(CSRB, 0, 0));
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+
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+ w = uwire_read_reg(UWIRE_CSR);
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+ old_cs = (w >> 10) & 0x03;
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+ if (value == BITBANG_CS_INACTIVE || old_cs != spi->chip_select) {
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+ /* Deselect this CS, or the previous CS */
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+ w &= ~CS_CMD;
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+ uwire_write_reg(UWIRE_CSR, w);
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+ }
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+ /* activate specfied chipselect */
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+ if (value == BITBANG_CS_ACTIVE) {
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+ uwire_set_clk1_div(ust->div1_idx);
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+ /* invert clock? */
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+ if (spi->mode & SPI_CPOL)
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+ uwire_write_reg(UWIRE_SR4, 1);
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+ else
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+ uwire_write_reg(UWIRE_SR4, 0);
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+
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+ w = spi->chip_select << 10;
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+ w |= CS_CMD;
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+ uwire_write_reg(UWIRE_CSR, w);
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+ }
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+}
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+
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+static int uwire_txrx(struct spi_device *spi, struct spi_transfer *t)
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+{
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+ struct uwire_state *ust = spi->controller_state;
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+ unsigned len = t->len;
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+ unsigned bits = ust->bits_per_word;
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+ unsigned bytes;
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+ u16 val, w;
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+ int status = 0;;
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+
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+ if (!t->tx_buf && !t->rx_buf)
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+ return 0;
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+
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+ /* Microwire doesn't read and write concurrently */
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+ if (t->tx_buf && t->rx_buf)
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+ return -EPERM;
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+
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+ w = spi->chip_select << 10;
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+ w |= CS_CMD;
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+
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+ if (t->tx_buf) {
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+ const u8 *buf = t->tx_buf;
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+
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+ /* NOTE: DMA could be used for TX transfers */
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+
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+ /* write one or two bytes at a time */
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+ while (len >= 1) {
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+ /* tx bit 15 is first sent; we byteswap multibyte words
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+ * (msb-first) on the way out from memory.
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+ */
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+ val = *buf++;
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+ if (bits > 8) {
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+ bytes = 2;
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+ val |= *buf++ << 8;
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+ } else
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+ bytes = 1;
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+ val <<= 16 - bits;
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+
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+#ifdef VERBOSE
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+ pr_debug("%s: write-%d =%04x\n",
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+ spi->dev.bus_id, bits, val);
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+#endif
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+ if (wait_uwire_csr_flag(CSRB, 0, 0))
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+ goto eio;
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+
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+ uwire_write_reg(UWIRE_TDR, val);
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+
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+ /* start write */
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+ val = START | w | (bits << 5);
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+
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+ uwire_write_reg(UWIRE_CSR, val);
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+ len -= bytes;
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+
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+ /* Wait till write actually starts.
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+ * This is needed with MPU clock 60+ MHz.
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+ * REVISIT: we may not have time to catch it...
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+ */
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+ if (wait_uwire_csr_flag(CSRB, CSRB, 1))
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+ goto eio;
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+
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+ status += bytes;
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+ }
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+
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+ /* REVISIT: save this for later to get more i/o overlap */
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+ if (wait_uwire_csr_flag(CSRB, 0, 0))
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+ goto eio;
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+
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+ } else if (t->rx_buf) {
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+ u8 *buf = t->rx_buf;
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+
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+ /* read one or two bytes at a time */
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+ while (len) {
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+ if (bits > 8) {
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+ bytes = 2;
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+ } else
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+ bytes = 1;
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+
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+ /* start read */
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+ val = START | w | (bits << 0);
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+ uwire_write_reg(UWIRE_CSR, val);
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+ len -= bytes;
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+
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+ /* Wait till read actually starts */
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+ (void) wait_uwire_csr_flag(CSRB, CSRB, 1);
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+
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+ if (wait_uwire_csr_flag(RDRB | CSRB,
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+ RDRB, 0))
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+ goto eio;
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+
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+ /* rx bit 0 is last received; multibyte words will
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+ * be properly byteswapped on the way to memory.
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+ */
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+ val = uwire_read_reg(UWIRE_RDR);
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+ val &= (1 << bits) - 1;
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+ *buf++ = (u8) val;
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+ if (bytes == 2)
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+ *buf++ = val >> 8;
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+ status += bytes;
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+#ifdef VERBOSE
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+ pr_debug("%s: read-%d =%04x\n",
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+ spi->dev.bus_id, bits, val);
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+#endif
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+
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+ }
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+ }
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+ return status;
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+eio:
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+ return -EIO;
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+}
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+
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+static int uwire_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
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+{
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+ struct uwire_state *ust = spi->controller_state;
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+ struct uwire_spi *uwire;
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+ unsigned flags = 0;
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+ unsigned bits;
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+ unsigned hz;
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+ unsigned long rate;
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+ int div1_idx;
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+ int div1;
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+ int div2;
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+ int status;
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+
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+ uwire = spi_master_get_devdata(spi->master);
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+
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+ if (spi->chip_select > 3) {
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+ pr_debug("%s: cs%d?\n", spi->dev.bus_id, spi->chip_select);
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+ status = -ENODEV;
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+ goto done;
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+ }
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+
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+ bits = spi->bits_per_word;
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+ if (t != NULL && t->bits_per_word)
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+ bits = t->bits_per_word;
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+ if (!bits)
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+ bits = 8;
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+
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+ if (bits > 16) {
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+ pr_debug("%s: wordsize %d?\n", spi->dev.bus_id, bits);
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+ status = -ENODEV;
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+ goto done;
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+ }
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+ ust->bits_per_word = bits;
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+
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+ /* mode 0..3, clock inverted separately;
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+ * standard nCS signaling;
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+ * don't treat DI=high as "not ready"
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+ */
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+ if (spi->mode & SPI_CS_HIGH)
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+ flags |= UWIRE_CS_ACTIVE_HIGH;
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+
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+ if (spi->mode & SPI_CPOL)
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+ flags |= UWIRE_CLK_INVERTED;
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+
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+ switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
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+ case SPI_MODE_0:
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+ case SPI_MODE_3:
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+ flags |= UWIRE_WRITE_RISING_EDGE | UWIRE_READ_FALLING_EDGE;
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+ break;
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+ case SPI_MODE_1:
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+ case SPI_MODE_2:
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+ flags |= UWIRE_WRITE_FALLING_EDGE | UWIRE_READ_RISING_EDGE;
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+ break;
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+ }
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+
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+ /* assume it's already enabled */
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+ rate = clk_get_rate(uwire->ck);
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+
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+ hz = spi->max_speed_hz;
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+ if (t != NULL && t->speed_hz)
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+ hz = t->speed_hz;
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+
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+ if (!hz) {
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+ pr_debug("%s: zero speed?\n", spi->dev.bus_id);
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+ status = -EINVAL;
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+ goto done;
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+ }
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+
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+ /* F_INT = mpu_xor_clk / DIV1 */
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+ for (div1_idx = 0; div1_idx < 4; div1_idx++) {
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+ switch (div1_idx) {
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+ case 0:
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+ div1 = 2;
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+ break;
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+ case 1:
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+ div1 = 4;
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+ break;
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+ case 2:
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+ div1 = 7;
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+ break;
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+ default:
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+ case 3:
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+ div1 = 10;
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+ break;
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+ }
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+ div2 = (rate / div1 + hz - 1) / hz;
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+ if (div2 <= 8)
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+ break;
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+ }
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+ if (div1_idx == 4) {
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+ pr_debug("%s: lowest clock %ld, need %d\n",
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+ spi->dev.bus_id, rate / 10 / 8, hz);
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+ status = -EDOM;
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+ goto done;
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+ }
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+
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+ /* we have to cache this and reset in uwire_chipselect as this is a
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+ * global parameter and another uwire device can change it under
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|
|
+ * us */
|
|
|
+ ust->div1_idx = div1_idx;
|
|
|
+ uwire_set_clk1_div(div1_idx);
|
|
|
+
|
|
|
+ rate /= div1;
|
|
|
+
|
|
|
+ switch (div2) {
|
|
|
+ case 0:
|
|
|
+ case 1:
|
|
|
+ case 2:
|
|
|
+ flags |= UWIRE_FREQ_DIV_2;
|
|
|
+ rate /= 2;
|
|
|
+ break;
|
|
|
+ case 3:
|
|
|
+ case 4:
|
|
|
+ flags |= UWIRE_FREQ_DIV_4;
|
|
|
+ rate /= 4;
|
|
|
+ break;
|
|
|
+ case 5:
|
|
|
+ case 6:
|
|
|
+ case 7:
|
|
|
+ case 8:
|
|
|
+ flags |= UWIRE_FREQ_DIV_8;
|
|
|
+ rate /= 8;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ omap_uwire_configure_mode(spi->chip_select, flags);
|
|
|
+ pr_debug("%s: uwire flags %02x, armxor %lu KHz, SCK %lu KHz\n",
|
|
|
+ __FUNCTION__, flags,
|
|
|
+ clk_get_rate(uwire->ck) / 1000,
|
|
|
+ rate / 1000);
|
|
|
+ status = 0;
|
|
|
+done:
|
|
|
+ return status;
|
|
|
+}
|
|
|
+
|
|
|
+static int uwire_setup(struct spi_device *spi)
|
|
|
+{
|
|
|
+ struct uwire_state *ust = spi->controller_state;
|
|
|
+
|
|
|
+ if (ust == NULL) {
|
|
|
+ ust = kzalloc(sizeof(*ust), GFP_KERNEL);
|
|
|
+ if (ust == NULL)
|
|
|
+ return -ENOMEM;
|
|
|
+ spi->controller_state = ust;
|
|
|
+ }
|
|
|
+
|
|
|
+ return uwire_setup_transfer(spi, NULL);
|
|
|
+}
|
|
|
+
|
|
|
+static void uwire_cleanup(const struct spi_device *spi)
|
|
|
+{
|
|
|
+ kfree(spi->controller_state);
|
|
|
+}
|
|
|
+
|
|
|
+static void uwire_off(struct uwire_spi *uwire)
|
|
|
+{
|
|
|
+ uwire_write_reg(UWIRE_SR3, 0);
|
|
|
+ clk_disable(uwire->ck);
|
|
|
+ clk_put(uwire->ck);
|
|
|
+ spi_master_put(uwire->bitbang.master);
|
|
|
+}
|
|
|
+
|
|
|
+static int uwire_probe(struct platform_device *pdev)
|
|
|
+{
|
|
|
+ struct spi_master *master;
|
|
|
+ struct uwire_spi *uwire;
|
|
|
+ int status;
|
|
|
+
|
|
|
+ master = spi_alloc_master(&pdev->dev, sizeof *uwire);
|
|
|
+ if (!master)
|
|
|
+ return -ENODEV;
|
|
|
+
|
|
|
+ uwire = spi_master_get_devdata(master);
|
|
|
+ dev_set_drvdata(&pdev->dev, uwire);
|
|
|
+
|
|
|
+ uwire->ck = clk_get(&pdev->dev, "armxor_ck");
|
|
|
+ if (!uwire->ck || IS_ERR(uwire->ck)) {
|
|
|
+ dev_dbg(&pdev->dev, "no mpu_xor_clk ?\n");
|
|
|
+ spi_master_put(master);
|
|
|
+ return -ENODEV;
|
|
|
+ }
|
|
|
+ clk_enable(uwire->ck);
|
|
|
+
|
|
|
+ if (cpu_is_omap730())
|
|
|
+ uwire_idx_shift = 1;
|
|
|
+ else
|
|
|
+ uwire_idx_shift = 2;
|
|
|
+
|
|
|
+ uwire_write_reg(UWIRE_SR3, 1);
|
|
|
+
|
|
|
+ master->bus_num = 2; /* "official" */
|
|
|
+ master->num_chipselect = 4;
|
|
|
+ master->setup = uwire_setup;
|
|
|
+ master->cleanup = uwire_cleanup;
|
|
|
+
|
|
|
+ uwire->bitbang.master = master;
|
|
|
+ uwire->bitbang.chipselect = uwire_chipselect;
|
|
|
+ uwire->bitbang.setup_transfer = uwire_setup_transfer;
|
|
|
+ uwire->bitbang.txrx_bufs = uwire_txrx;
|
|
|
+
|
|
|
+ status = spi_bitbang_start(&uwire->bitbang);
|
|
|
+ if (status < 0)
|
|
|
+ uwire_off(uwire);
|
|
|
+ return status;
|
|
|
+}
|
|
|
+
|
|
|
+static int uwire_remove(struct platform_device *pdev)
|
|
|
+{
|
|
|
+ struct uwire_spi *uwire = dev_get_drvdata(&pdev->dev);
|
|
|
+ int status;
|
|
|
+
|
|
|
+ // FIXME remove all child devices, somewhere ...
|
|
|
+
|
|
|
+ status = spi_bitbang_stop(&uwire->bitbang);
|
|
|
+ uwire_off(uwire);
|
|
|
+ return status;
|
|
|
+}
|
|
|
+
|
|
|
+static struct platform_driver uwire_driver = {
|
|
|
+ .driver = {
|
|
|
+ .name = "omap_uwire",
|
|
|
+ .bus = &platform_bus_type,
|
|
|
+ .owner = THIS_MODULE,
|
|
|
+ },
|
|
|
+ .probe = uwire_probe,
|
|
|
+ .remove = uwire_remove,
|
|
|
+ // suspend ... unuse ck
|
|
|
+ // resume ... use ck
|
|
|
+};
|
|
|
+
|
|
|
+static int __init omap_uwire_init(void)
|
|
|
+{
|
|
|
+ /* FIXME move these into the relevant board init code. also, include
|
|
|
+ * H3 support; it uses tsc2101 like H2 (on a different chipselect).
|
|
|
+ */
|
|
|
+
|
|
|
+ if (machine_is_omap_h2()) {
|
|
|
+ /* defaults: W21 SDO, U18 SDI, V19 SCL */
|
|
|
+ omap_cfg_reg(N14_1610_UWIRE_CS0);
|
|
|
+ omap_cfg_reg(N15_1610_UWIRE_CS1);
|
|
|
+ }
|
|
|
+ if (machine_is_omap_perseus2()) {
|
|
|
+ /* configure pins: MPU_UW_nSCS1, MPU_UW_SDO, MPU_UW_SCLK */
|
|
|
+ int val = omap_readl(OMAP730_IO_CONF_9) & ~0x00EEE000;
|
|
|
+ omap_writel(val | 0x00AAA000, OMAP730_IO_CONF_9);
|
|
|
+ }
|
|
|
+
|
|
|
+ return platform_driver_register(&uwire_driver);
|
|
|
+}
|
|
|
+
|
|
|
+static void __exit omap_uwire_exit(void)
|
|
|
+{
|
|
|
+ platform_driver_unregister(&uwire_driver);
|
|
|
+}
|
|
|
+
|
|
|
+subsys_initcall(omap_uwire_init);
|
|
|
+module_exit(omap_uwire_exit);
|
|
|
+
|
|
|
+MODULE_LICENSE("GPL");
|
|
|
+
|