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@@ -65,8 +65,10 @@ static unsigned long reset_value[NUM_COUNTERS];
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#define IBS_FETCH_BEGIN 3
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#define IBS_FETCH_BEGIN 3
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#define IBS_OP_BEGIN 4
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#define IBS_OP_BEGIN 4
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-/* The function interface needs to be fixed, something like add
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- data. Should then be added to linux/oprofile.h. */
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+/*
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+ * The function interface needs to be fixed, something like add
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+ * data. Should then be added to linux/oprofile.h.
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+ */
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extern void
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extern void
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oprofile_add_ibs_sample(struct pt_regs *const regs,
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oprofile_add_ibs_sample(struct pt_regs *const regs,
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unsigned int *const ibs_sample, int ibs_code);
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unsigned int *const ibs_sample, int ibs_code);
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@@ -106,7 +108,7 @@ struct ibs_op_sample {
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/*
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/*
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* unitialize the APIC for the IBS interrupts if needed on AMD Family10h+
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* unitialize the APIC for the IBS interrupts if needed on AMD Family10h+
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-*/
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+ */
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static void clear_ibs_nmi(void);
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static void clear_ibs_nmi(void);
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static int ibs_allowed; /* AMD Family10h and later */
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static int ibs_allowed; /* AMD Family10h and later */
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@@ -223,7 +225,7 @@ op_amd_handle_ibs(struct pt_regs * const regs,
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(unsigned int *)&ibs_fetch,
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(unsigned int *)&ibs_fetch,
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IBS_FETCH_BEGIN);
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IBS_FETCH_BEGIN);
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- /*reenable the IRQ */
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+ /* reenable the IRQ */
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rdmsr(MSR_AMD64_IBSFETCHCTL, low, high);
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rdmsr(MSR_AMD64_IBSFETCHCTL, low, high);
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high &= ~IBS_FETCH_HIGH_VALID_BIT;
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high &= ~IBS_FETCH_HIGH_VALID_BIT;
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high |= IBS_FETCH_HIGH_ENABLE;
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high |= IBS_FETCH_HIGH_ENABLE;
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@@ -331,8 +333,10 @@ static void op_amd_stop(struct op_msrs const * const msrs)
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unsigned int low, high;
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unsigned int low, high;
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int i;
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int i;
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- /* Subtle: stop on all counters to avoid race with
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- * setting our pm callback */
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+ /*
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+ * Subtle: stop on all counters to avoid race with setting our
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+ * pm callback
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+ */
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for (i = 0 ; i < NUM_COUNTERS ; ++i) {
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for (i = 0 ; i < NUM_COUNTERS ; ++i) {
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if (!reset_value[i])
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if (!reset_value[i])
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continue;
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continue;
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@@ -343,13 +347,15 @@ static void op_amd_stop(struct op_msrs const * const msrs)
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#ifdef CONFIG_OPROFILE_IBS
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#ifdef CONFIG_OPROFILE_IBS
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if (ibs_allowed && ibs_config.fetch_enabled) {
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if (ibs_allowed && ibs_config.fetch_enabled) {
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- low = 0; /* clear max count and enable */
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+ /* clear max count and enable */
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+ low = 0;
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high = 0;
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high = 0;
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wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
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wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
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}
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}
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if (ibs_allowed && ibs_config.op_enabled) {
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if (ibs_allowed && ibs_config.op_enabled) {
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- low = 0; /* clear max count and enable */
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+ /* clear max count and enable */
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+ low = 0;
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high = 0;
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high = 0;
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wrmsr(MSR_AMD64_IBSOPCTL, low, high);
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wrmsr(MSR_AMD64_IBSOPCTL, low, high);
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}
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}
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@@ -443,10 +449,7 @@ static int pfm_amd64_setup_eilvt(void)
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return 0;
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return 0;
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}
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}
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-/*
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- * initialize the APIC for the IBS interrupts
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- * if available (AMD Family10h rev B0 and later)
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- */
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+/* initialize the APIC for the IBS interrupts if available */
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static void setup_ibs(void)
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static void setup_ibs(void)
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{
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{
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ibs_allowed = boot_cpu_has(X86_FEATURE_IBS);
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ibs_allowed = boot_cpu_has(X86_FEATURE_IBS);
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@@ -463,9 +466,7 @@ static void setup_ibs(void)
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}
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}
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-/*
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- * unitialize the APIC for the IBS interrupts if needed on AMD Family10h
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- * rev B0 and later */
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+/* uninitialize the APIC for the IBS interrupts if needed */
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static void clear_ibs_nmi(void)
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static void clear_ibs_nmi(void)
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{
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{
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if (ibs_allowed)
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if (ibs_allowed)
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