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@@ -29,6 +29,24 @@
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#include "nv50_display.h"
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static void nv50_gpio_isr(struct drm_device *dev);
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+static void nv50_gpio_isr_bh(struct work_struct *work);
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+
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+struct nv50_gpio_priv {
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+ struct list_head handlers;
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+ spinlock_t lock;
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+};
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+
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+struct nv50_gpio_handler {
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+ struct drm_device *dev;
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+ struct list_head head;
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+ struct work_struct work;
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+ bool inhibit;
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+
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+ struct dcb_gpio_entry *gpio;
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+
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+ void (*handler)(void *data, int state);
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+ void *data;
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+};
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static int
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nv50_gpio_location(struct dcb_gpio_entry *gpio, uint32_t *reg, uint32_t *shift)
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@@ -79,29 +97,123 @@ nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state)
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return 0;
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}
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+int
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+nv50_gpio_irq_register(struct drm_device *dev, enum dcb_gpio_tag tag,
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+ void (*handler)(void *, int), void *data)
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+{
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+ struct drm_nouveau_private *dev_priv = dev->dev_private;
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+ struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
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+ struct nv50_gpio_priv *priv = pgpio->priv;
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+ struct nv50_gpio_handler *gpioh;
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+ struct dcb_gpio_entry *gpio;
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+ unsigned long flags;
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+
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+ gpio = nouveau_bios_gpio_entry(dev, tag);
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+ if (!gpio)
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+ return -ENOENT;
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+
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+ gpioh = kzalloc(sizeof(*gpioh), GFP_KERNEL);
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+ if (!gpioh)
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+ return -ENOMEM;
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+
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+ INIT_WORK(&gpioh->work, nv50_gpio_isr_bh);
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+ gpioh->dev = dev;
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+ gpioh->gpio = gpio;
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+ gpioh->handler = handler;
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+ gpioh->data = data;
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+
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+ spin_lock_irqsave(&priv->lock, flags);
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+ list_add(&gpioh->head, &priv->handlers);
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+ spin_unlock_irqrestore(&priv->lock, flags);
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+ return 0;
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+}
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+
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void
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-nv50_gpio_irq_enable(struct drm_device *dev, enum dcb_gpio_tag tag, bool on)
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+nv50_gpio_irq_unregister(struct drm_device *dev, enum dcb_gpio_tag tag,
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+ void (*handler)(void *, int), void *data)
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{
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+ struct drm_nouveau_private *dev_priv = dev->dev_private;
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+ struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
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+ struct nv50_gpio_priv *priv = pgpio->priv;
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+ struct nv50_gpio_handler *gpioh, *tmp;
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struct dcb_gpio_entry *gpio;
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- u32 reg, mask;
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+ unsigned long flags;
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gpio = nouveau_bios_gpio_entry(dev, tag);
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- if (!gpio) {
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- NV_ERROR(dev, "gpio tag 0x%02x not found\n", tag);
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+ if (!gpio)
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return;
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+
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+ spin_lock_irqsave(&priv->lock, flags);
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+ list_for_each_entry_safe(gpioh, tmp, &priv->handlers, head) {
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+ if (gpioh->gpio != gpio ||
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+ gpioh->handler != handler ||
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+ gpioh->data != data)
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+ continue;
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+ list_del(&gpioh->head);
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+ kfree(gpioh);
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}
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+ spin_unlock_irqrestore(&priv->lock, flags);
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+}
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+
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+bool
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+nv50_gpio_irq_enable(struct drm_device *dev, enum dcb_gpio_tag tag, bool on)
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+{
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+ struct dcb_gpio_entry *gpio;
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+ u32 reg, mask;
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+
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+ gpio = nouveau_bios_gpio_entry(dev, tag);
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+ if (!gpio)
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+ return false;
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reg = gpio->line < 16 ? 0xe050 : 0xe070;
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mask = 0x00010001 << (gpio->line & 0xf);
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nv_wr32(dev, reg + 4, mask);
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- nv_mask(dev, reg + 0, mask, on ? mask : 0);
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+ reg = nv_mask(dev, reg + 0, mask, on ? mask : 0);
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+ return (reg & mask) == mask;
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+}
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+
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+static int
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+nv50_gpio_create(struct drm_device *dev)
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+{
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+ struct drm_nouveau_private *dev_priv = dev->dev_private;
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+ struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
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+ struct nv50_gpio_priv *priv;
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+
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+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
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+ if (!priv)
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+ return -ENOMEM;
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+
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+ INIT_LIST_HEAD(&priv->handlers);
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+ spin_lock_init(&priv->lock);
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+ pgpio->priv = priv;
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+ return 0;
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+}
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+
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+static void
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+nv50_gpio_destroy(struct drm_device *dev)
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+{
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+ struct drm_nouveau_private *dev_priv = dev->dev_private;
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+ struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
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+
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+ kfree(pgpio->priv);
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+ pgpio->priv = NULL;
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}
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int
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nv50_gpio_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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+ struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
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+ struct nv50_gpio_priv *priv;
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+ int ret;
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+
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+ if (!pgpio->priv) {
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+ ret = nv50_gpio_create(dev);
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+ if (ret)
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+ return ret;
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+ }
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+ priv = pgpio->priv;
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/* disable, and ack any pending gpio interrupts */
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nv_wr32(dev, 0xe050, 0x00000000);
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@@ -111,8 +223,6 @@ nv50_gpio_init(struct drm_device *dev)
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nv_wr32(dev, 0xe074, 0xffffffff);
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}
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- INIT_WORK(&dev_priv->hpd_work, nv50_display_irq_hotplug_bh);
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- spin_lock_init(&dev_priv->hpd_state.lock);
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nouveau_irq_register(dev, 21, nv50_gpio_isr);
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return 0;
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}
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@@ -126,26 +236,64 @@ nv50_gpio_fini(struct drm_device *dev)
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if (dev_priv->chipset >= 0x90)
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nv_wr32(dev, 0xe070, 0x00000000);
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nouveau_irq_unregister(dev, 21);
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+
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+ nv50_gpio_destroy(dev);
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+}
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+
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+static void
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+nv50_gpio_isr_bh(struct work_struct *work)
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+{
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+ struct nv50_gpio_handler *gpioh =
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+ container_of(work, struct nv50_gpio_handler, work);
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+ struct drm_nouveau_private *dev_priv = gpioh->dev->dev_private;
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+ struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
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+ struct nv50_gpio_priv *priv = pgpio->priv;
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+ unsigned long flags;
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+ int state;
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+
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+ state = pgpio->get(gpioh->dev, gpioh->gpio->tag);
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+ if (state < 0)
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+ return;
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+
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+ gpioh->handler(gpioh->data, state);
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+
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+ spin_lock_irqsave(&priv->lock, flags);
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+ gpioh->inhibit = false;
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+ spin_unlock_irqrestore(&priv->lock, flags);
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}
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static void
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nv50_gpio_isr(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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- uint32_t hpd0_bits, hpd1_bits = 0;
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+ struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
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+ struct nv50_gpio_priv *priv = pgpio->priv;
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+ struct nv50_gpio_handler *gpioh;
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+ u32 intr0, intr1 = 0;
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+ u32 hi, lo, ch;
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- hpd0_bits = nv_rd32(dev, 0xe054);
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- nv_wr32(dev, 0xe054, hpd0_bits);
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+ intr0 = nv_rd32(dev, 0xe054) & nv_rd32(dev, 0xe050);
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+ if (dev_priv->chipset >= 0x90)
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+ intr1 = nv_rd32(dev, 0xe074) & nv_rd32(dev, 0xe070);
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- if (dev_priv->chipset >= 0x90) {
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- hpd1_bits = nv_rd32(dev, 0xe074);
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- nv_wr32(dev, 0xe074, hpd1_bits);
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- }
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+ hi = (intr0 & 0x0000ffff) | (intr1 << 16);
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+ lo = (intr0 >> 16) | (intr1 & 0xffff0000);
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+ ch = hi | lo;
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- spin_lock(&dev_priv->hpd_state.lock);
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- dev_priv->hpd_state.hpd0_bits |= hpd0_bits;
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- dev_priv->hpd_state.hpd1_bits |= hpd1_bits;
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- spin_unlock(&dev_priv->hpd_state.lock);
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+ nv_wr32(dev, 0xe054, intr0);
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+ if (dev_priv->chipset >= 0x90)
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+ nv_wr32(dev, 0xe074, intr1);
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+
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+ spin_lock(&priv->lock);
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+ list_for_each_entry(gpioh, &priv->handlers, head) {
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+ if (!(ch & (1 << gpioh->gpio->line)))
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+ continue;
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- queue_work(dev_priv->wq, &dev_priv->hpd_work);
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+ if (gpioh->inhibit)
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+ continue;
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+ gpioh->inhibit = true;
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+
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+ queue_work(dev_priv->wq, &gpioh->work);
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+ }
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+ spin_unlock(&priv->lock);
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}
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