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@@ -196,30 +196,15 @@ void unmask_msi_irq(unsigned int irq)
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void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg)
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void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg)
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{
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{
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struct msi_desc *entry = get_irq_desc_msi(desc);
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struct msi_desc *entry = get_irq_desc_msi(desc);
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- if (entry->msi_attrib.is_msix) {
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- void __iomem *base = entry->mask_base +
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- entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
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- msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
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- msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
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- msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
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- } else {
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- struct pci_dev *dev = entry->dev;
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- int pos = entry->msi_attrib.pos;
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- u16 data;
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+ /* We do not touch the hardware (which may not even be
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+ * accessible at the moment) but return the last message
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+ * written. Assert that this is valid, assuming that
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+ * valid messages are not all-zeroes. */
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+ BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo |
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+ entry->msg.data));
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- pci_read_config_dword(dev, msi_lower_address_reg(pos),
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- &msg->address_lo);
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- if (entry->msi_attrib.is_64) {
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- pci_read_config_dword(dev, msi_upper_address_reg(pos),
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- &msg->address_hi);
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- pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
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- } else {
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- msg->address_hi = 0;
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- pci_read_config_word(dev, msi_data_reg(pos, 0), &data);
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- }
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- msg->data = data;
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- }
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+ *msg = entry->msg;
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}
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}
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void read_msi_msg(unsigned int irq, struct msi_msg *msg)
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void read_msi_msg(unsigned int irq, struct msi_msg *msg)
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@@ -232,7 +217,10 @@ void read_msi_msg(unsigned int irq, struct msi_msg *msg)
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void write_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg)
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void write_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg)
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{
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{
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struct msi_desc *entry = get_irq_desc_msi(desc);
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struct msi_desc *entry = get_irq_desc_msi(desc);
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- if (entry->msi_attrib.is_msix) {
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+
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+ if (entry->dev->current_state != PCI_D0) {
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+ /* Don't touch the hardware now */
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+ } else if (entry->msi_attrib.is_msix) {
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void __iomem *base;
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void __iomem *base;
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base = entry->mask_base +
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base = entry->mask_base +
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entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
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entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
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