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@@ -2849,7 +2849,7 @@ static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
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mutex_unlock(&dev->struct_mutex);
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}
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-static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
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+static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct intel_encoder *intel_encoder;
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@@ -2859,23 +2859,6 @@ static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
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* must be driven by its own crtc; no sharing is possible.
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*/
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for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
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-
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- /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
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- * CPU handles all others */
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- if (IS_HASWELL(dev)) {
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- /* It is still unclear how this will work on PPT, so throw up a warning */
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- WARN_ON(!HAS_PCH_LPT(dev));
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-
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- if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
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- DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
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- return true;
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- } else {
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- DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
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- intel_encoder->type);
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- return false;
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- }
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- }
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-
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switch (intel_encoder->type) {
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case INTEL_OUTPUT_EDP:
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if (!intel_encoder_is_pch_edp(&intel_encoder->base))
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@@ -2887,6 +2870,11 @@ static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
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return true;
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}
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+static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
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+{
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+ return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
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+}
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+
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/* Program iCLKIP clock to the desired frequency */
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static void lpt_program_iclkip(struct drm_crtc *crtc)
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{
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@@ -3215,7 +3203,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
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I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
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}
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- is_pch_port = intel_crtc_driving_pch(crtc);
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+ is_pch_port = ironlake_crtc_driving_pch(crtc);
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if (is_pch_port) {
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ironlake_fdi_pll_enable(intel_crtc);
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@@ -3293,7 +3281,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
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intel_crtc->active = true;
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intel_update_watermarks(dev);
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- is_pch_port = intel_crtc_driving_pch(crtc);
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+ is_pch_port = haswell_crtc_driving_pch(crtc);
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if (is_pch_port) {
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ironlake_fdi_pll_enable(intel_crtc);
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