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@@ -75,6 +75,10 @@
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extern const char gfar_driver_name[];
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extern const char gfar_driver_version[];
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+/* MAXIMUM NUMBER OF QUEUES SUPPORTED */
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+#define MAX_TX_QS 0x8
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+#define MAX_RX_QS 0x8
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+
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/* These need to be powers of 2 for this driver */
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#define DEFAULT_TX_RING_SIZE 256
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#define DEFAULT_RX_RING_SIZE 256
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@@ -172,12 +176,63 @@ extern const char gfar_driver_version[];
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#define MINFLR_INIT_SETTINGS 0x00000040
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+/* Tqueue control */
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+#define TQUEUE_EN0 0x00008000
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+#define TQUEUE_EN1 0x00004000
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+#define TQUEUE_EN2 0x00002000
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+#define TQUEUE_EN3 0x00001000
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+#define TQUEUE_EN4 0x00000800
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+#define TQUEUE_EN5 0x00000400
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+#define TQUEUE_EN6 0x00000200
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+#define TQUEUE_EN7 0x00000100
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+#define TQUEUE_EN_ALL 0x0000FF00
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+
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+#define TR03WT_WT0_MASK 0xFF000000
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+#define TR03WT_WT1_MASK 0x00FF0000
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+#define TR03WT_WT2_MASK 0x0000FF00
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+#define TR03WT_WT3_MASK 0x000000FF
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+
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+#define TR47WT_WT4_MASK 0xFF000000
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+#define TR47WT_WT5_MASK 0x00FF0000
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+#define TR47WT_WT6_MASK 0x0000FF00
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+#define TR47WT_WT7_MASK 0x000000FF
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+
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+/* Rqueue control */
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+#define RQUEUE_EX0 0x00800000
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+#define RQUEUE_EX1 0x00400000
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+#define RQUEUE_EX2 0x00200000
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+#define RQUEUE_EX3 0x00100000
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+#define RQUEUE_EX4 0x00080000
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+#define RQUEUE_EX5 0x00040000
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+#define RQUEUE_EX6 0x00020000
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+#define RQUEUE_EX7 0x00010000
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+#define RQUEUE_EX_ALL 0x00FF0000
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+
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+#define RQUEUE_EN0 0x00000080
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+#define RQUEUE_EN1 0x00000040
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+#define RQUEUE_EN2 0x00000020
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+#define RQUEUE_EN3 0x00000010
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+#define RQUEUE_EN4 0x00000008
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+#define RQUEUE_EN5 0x00000004
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+#define RQUEUE_EN6 0x00000002
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+#define RQUEUE_EN7 0x00000001
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+#define RQUEUE_EN_ALL 0x000000FF
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+
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/* Init to do tx snooping for buffers and descriptors */
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#define DMACTRL_INIT_SETTINGS 0x000000c3
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#define DMACTRL_GRS 0x00000010
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#define DMACTRL_GTS 0x00000008
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-#define TSTAT_CLEAR_THALT 0x80000000
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+#define TSTAT_CLEAR_THALT_ALL 0xFF000000
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+#define TSTAT_CLEAR_THALT 0x80000000
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+#define TSTAT_CLEAR_THALT0 0x80000000
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+#define TSTAT_CLEAR_THALT1 0x40000000
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+#define TSTAT_CLEAR_THALT2 0x20000000
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+#define TSTAT_CLEAR_THALT3 0x10000000
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+#define TSTAT_CLEAR_THALT4 0x08000000
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+#define TSTAT_CLEAR_THALT5 0x04000000
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+#define TSTAT_CLEAR_THALT6 0x02000000
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+#define TSTAT_CLEAR_THALT7 0x01000000
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/* Interrupt coalescing macros */
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#define IC_ICEN 0x80000000
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@@ -228,6 +283,13 @@ extern const char gfar_driver_version[];
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#define TCTRL_IPCSEN 0x00004000
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#define TCTRL_TUCSEN 0x00002000
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#define TCTRL_VLINS 0x00001000
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+#define TCTRL_THDF 0x00000800
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+#define TCTRL_RFCPAUSE 0x00000010
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+#define TCTRL_TFCPAUSE 0x00000008
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+#define TCTRL_TXSCHED_MASK 0x00000006
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+#define TCTRL_TXSCHED_INIT 0x00000000
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+#define TCTRL_TXSCHED_PRIO 0x00000002
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+#define TCTRL_TXSCHED_WRRS 0x00000004
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#define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN)
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#define IEVENT_INIT_CLEAR 0xffffffff
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@@ -700,6 +762,8 @@ struct gfar {
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#define FSL_GIANFAR_DEV_HAS_BD_STASHING 0x00000200
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#define FSL_GIANFAR_DEV_HAS_BUF_STASHING 0x00000400
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+#define DEFAULT_MAPPING 0xFF
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+
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/**
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* struct gfar_priv_tx_q - per tx queue structure
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* @txlock: per queue tx spin lock
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@@ -743,7 +807,6 @@ struct gfar_priv_tx_q {
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/**
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* struct gfar_priv_rx_q - per rx queue structure
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* @rxlock: per queue rx spin lock
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- * @napi: the napi poll function
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* @rx_skbuff: skb pointers
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* @skb_currx: currently use skb pointer
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* @rx_bd_base: First rx buffer descriptor
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@@ -757,8 +820,8 @@ struct gfar_priv_tx_q {
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struct gfar_priv_rx_q {
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spinlock_t rxlock __attribute__ ((aligned (SMP_CACHE_BYTES)));
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- struct napi_struct napi;
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struct sk_buff ** rx_skbuff;
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+ dma_addr_t rx_bd_dma_base;
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struct rxbd8 *rx_bd_base;
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struct rxbd8 *cur_rx;
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struct net_device *dev;
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@@ -772,6 +835,7 @@ struct gfar_priv_rx_q {
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/**
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* struct gfar_priv_grp - per group structure
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+ * @napi: the napi poll function
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* @priv: back pointer to the priv structure
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* @regs: the ioremapped register space for this group
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* @grp_id: group id for this group
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@@ -785,8 +849,17 @@ struct gfar_priv_rx_q {
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struct gfar_priv_grp {
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spinlock_t grplock __attribute__ ((aligned (SMP_CACHE_BYTES)));
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+ struct napi_struct napi;
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struct gfar_private *priv;
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struct gfar __iomem *regs;
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+ unsigned int rx_bit_map;
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+ unsigned int tx_bit_map;
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+ unsigned int num_tx_queues;
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+ unsigned int num_rx_queues;
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+ unsigned int rstat;
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+ unsigned int tstat;
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+ unsigned int imask;
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+ unsigned int ievent;
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unsigned int interruptTransmit;
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unsigned int interruptReceive;
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unsigned int interruptError;
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@@ -807,13 +880,21 @@ struct gfar_priv_grp {
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*/
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struct gfar_private {
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+ /* Indicates how many tx, rx queues are enabled */
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+ unsigned int num_tx_queues;
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+ unsigned int num_rx_queues;
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+
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+ /* The total tx and rx ring size for the enabled queues */
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+ unsigned int total_tx_ring_size;
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+ unsigned int total_rx_ring_size;
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+
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struct device_node *node;
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struct net_device *ndev;
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struct of_device *ofdev;
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struct gfar_priv_grp gfargrp;
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- struct gfar_priv_tx_q *tx_queue;
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- struct gfar_priv_rx_q *rx_queue;
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+ struct gfar_priv_tx_q *tx_queue[MAX_TX_QS];
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+ struct gfar_priv_rx_q *rx_queue[MAX_RX_QS];
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/* RX per device parameters */
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unsigned int rx_buffer_size;
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@@ -844,6 +925,7 @@ struct gfar_private {
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unsigned char rx_csum_enable:1,
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extended_hash:1,
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bd_stash_en:1,
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+ rx_filer_enable:1,
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wol_en:1; /* Wake-on-LAN enabled */
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unsigned short padding;
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@@ -874,6 +956,10 @@ static inline void gfar_write(volatile unsigned __iomem *addr, u32 val)
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out_be32(addr, val);
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}
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+extern void lock_rx_qs(struct gfar_private *priv);
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+extern void lock_tx_qs(struct gfar_private *priv);
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+extern void unlock_rx_qs(struct gfar_private *priv);
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+extern void unlock_tx_qs(struct gfar_private *priv);
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extern irqreturn_t gfar_receive(int irq, void *dev_id);
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extern int startup_gfar(struct net_device *dev);
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extern void stop_gfar(struct net_device *dev);
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